JP2001231284A - Motor and disk device having motor - Google Patents

Abstract

[PROBLEMS] To provide a power-efficient motor and a disk device which are driven to rotate in a predetermined direction with low vibration and low noise without using a position detecting element. SOLUTION: While a power transistor of a power supply unit 20 performs a high-frequency switching operation, a three-phase coil 11, 3
A current path to the coils 12, 13 is formed, and the voltage detecting unit 30 converts the terminal voltages V 1, V
2 and V3, and outputs a detection pulse signal Dt corresponding to these terminal voltages. The state transition unit 31 changes the holding state after the first adjustment time and after the second adjustment time in response to the occurrence of the edge of the detection pulse signal, and outputs a state signal. The switching control unit 22 outputs the current detection signal and the command. A PWM pulse signal is generated in response to the signal comparison result. The energization control unit 32 includes the state transition unit 31 and the switching control unit 2
In response to the output signal of No. 2, the power transistor is turned on and off by a high-frequency switching operation. Voltage detector 30
Responds to the PWM operation by the switching control unit 22 to stop or execute the detection of the terminal voltage, thereby preventing erroneous detection due to PWM noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a motor, and
The present invention relates to a disk device including a motor.

[0002]

2. Description of the Related Art In recent years, motors for electronically switching a current path using a plurality of transistors have been widely used as motors for driving OA equipment and AV equipment. Disk devices such as an optical disk device (DVD device, CD device, etc.) and a magnetic disk device (HDD device, FDD device, etc.) are configured to include such a motor. As an example of such a motor, there is a motor that switches a current path to a coil using a PNP power transistor and an NPN power transistor.

FIG. 26 shows a conventional motor, and its operation will be described. The rotor 2011 has a field part made of a permanent magnet, and the position detector 2041 detects the magnetic field of the field part of the rotor 2011 with three position detecting elements. That is,
From the three-phase output signals of the three position detecting elements responding to the rotation of the rotor 2011, the position detector 2041 determines two sets of three-phase voltage signals Kp1, Kp2, Kp3 and Kp4, Kp5.
Generates Kp6. The first distributor 2042 receives the voltage signal K
Lower signal Mp of three phases responding to p1, Kp2 and Kp3
1, Mp2, and Mp3, and controls the energization of the lower NPN-type power transistors 2021, 2022, and 2023. The second distributor 2043 supplies the voltage signals Kp4 and Kp
5, three-phase upper signals Mp4, Mp5 in response to Kp6
Mp6 is generated to control the energization of the upper PNP power transistors 2025, 2026, and 2027. As a result, three-phase driving voltages are supplied to the coils 2012, 2013, and 2014.

[0004]

In the conventional configuration, power loss in the power transistor is large, and heat generation of the motor and the disk device has become a problem. NPN power transistors 2021, 2022, 2023 and PNP power transistors 2025, 2026, 20
Reference numeral 27 controls the voltage between the emitter and the collector in an analog manner, and supplies a drive voltage having a necessary amplitude to the coils 2012, 2013, and 2014. Therefore, the residual voltage of each power transistor is large, and large power loss and heat generation occur due to the product of the residual voltage and the drive current to the coil. Recordable disks (RAM disks, RW disks, etc.) are vulnerable to heat, and there is a demand for minimizing the heat generated by the disk device in order to improve the reliability of recording or reproduction of the recordable disks.

The position detector 2041 is connected to the rotor 201
It includes three position detecting elements for detecting one rotational position. For this reason, the position detector 2041 requires a space for mounting the position detecting element, and wiring and the like become complicated, resulting in an increase in cost. Therefore, by eliminating such a position detecting element, it is possible to reduce the size of the motor and to reduce the thickness of the disk device. In a rewritable disk device such as a DVD-RAM / RW device, information is recorded / reproduced on / from a high-density disk. Therefore, it is necessary to rotate the disk at low vibration in recording and reproducing on the disk. Further, in reproducing a DVD-ROM / CD-ROM disc, it is necessary to rotate the disc at a high speed with low noise. However, it has been very difficult to drive the rotor and disk with low vibration and low noise while eliminating the position detection element and reducing heat generation.

[0006] Solving the above various problems has been a problem in this type of motor and disk device.
An object of the present invention is to provide a motor and a disk device that solve the above-mentioned problems individually or simultaneously.

[0007]

According to the present invention, there is provided a motor comprising a rotor having a field portion for generating a field magnetic flux, and a Q-phase (Q is an integer of 3 or more) disposed on a stator.
, A voltage supply means having two output terminals for supplying a DC voltage, and Q first power supplies for supplying power from the first output terminal side of the voltage supply means to one end of the coil.
A power transistor comprising: Q power transistors for supplying power from the second output terminal side of the voltage supply means to one end of the coil; and a terminal of the coil. Voltage detection means for generating a detection pulse signal responsive to a voltage; state transition means for transitioning a holding state in response to the detection pulse signal of the voltage detection means; and electric power in response to a holding state of the state transition means. Energization control means for controlling energization of the power transistor of the supply means, and at least one of the Q first power transistors and the Q second power transistors of the power supply means responsive to a command signal Switching operation means for performing a high-frequency switching operation. Create a first second activation control signals of the activation control signals and Q-phase of the response was Q-phase, first the Q-phase
And controlling the energization state of the Q first power transistors and the Q second power transistors in response to the energization control signal of the Q phase and the second energization control signal of the Q phase. A power transistor and means for making an energizing section of each of the second power transistors larger than 360 / Q degrees in electrical angle, wherein the switching operation means generates a switching pulse signal in response to the command signal; The Q first power transistors and the Q
Means for causing at least one of the second power transistors to perform a high-frequency switching operation in response to the switching pulse signal, wherein the voltage detecting means includes a power supply for the at least one power transistor. The detection of the detection pulse signal is performed during at least one of a first stop time including a change time point of the high-frequency switching operation from off to on and a second stop time including a change time point from on to off. Means for stopping operation and performing a detection operation of the detection pulse signal in response to a terminal voltage of the coil at least when the at least one power transistor is turned on except for the at least one stop time. I have.

With this configuration, since the switching operation means causes the power transistor of the power supply means to perform high-frequency switching, the power loss of the power transistor of the power supply means can be greatly reduced, and the heat generation of the motor can be greatly reduced. Can be reduced. Further, the voltage detecting means, the state transition means, and the energization control means generate a detection pulse signal in response to the terminal voltage of the coil, and in response to the detection pulse signal, transition the energization phase to the coil, and move the rotor in a predetermined direction. It is rotating. Therefore, the position detecting element becomes unnecessary, and the configuration of the motor is simplified. Further, the energizing section of the first power transistor and the second power transistor is set to be larger than 360 / Q degree in electrical angle, and the two power transistors are simultaneously energized when the current path is switched. As a result, the switching of the current path becomes smooth, and the pulsation of the generated driving force is reduced. As a result,
It becomes a motor with low noise. Further, the power transistor is caused to perform high-frequency switching operation by the switching pulse signal, and at least one of a first stop time including a time point when the power transistor changes from off to on and a second stop time including a time point when the power transistor changes from on to off. Since the detection operation of the detection pulse signal is stopped during one stop time, erroneous detection due to high frequency noise generated in the terminal voltage due to the high frequency switching operation of the power transistor can be prevented. In addition, since the detection operation of the detection pulse signal corresponding to the comparison result of the terminal voltage of the coil is performed at least at the time of the ON operation of the power transistor except at least one stop time, the detection pulse signal corresponding to the comparison result of the terminal voltage is performed. Can be created. That is, a detection pulse signal accurately responding to the terminal voltage can be obtained. Therefore,
In response to the detection pulse signal of the voltage detection means, the switching operation of the current path to the coil can be performed at an accurate timing,
The rotor can be driven to rotate with high accuracy. Further, for example, when speed control is performed in response to an output pulse signal of the voltage detection means, the rotation speed of the rotor can be controlled with high accuracy. That is, high-precision motor rotation can be realized without being affected by high-frequency switching noise. As a result, based on the present invention, a high-performance motor with low heat generation and low vibration and noise can be realized at low cost.

A motor according to another aspect of the present invention includes a rotor provided with a field portion for generating a field magnetic flux, and a Q-phase (Q is an integer of 3 or more) coil provided on a stator. A voltage supply means having two output terminals for supplying a DC voltage; Q first power transistors for supplying power from a first output terminal side of the voltage supply means to one end of the coil; Power supply means including Q second power transistors for supplying power from the second output terminal side of the voltage supply means to one end of the coil, and a detection pulse responsive to a terminal voltage of the coil Voltage detecting means for generating a signal, state transition means for transitioning a holding state in response to a detection pulse signal of the voltage detecting means, and power transition of the power supply means in response to the holding state of the state transition means. High-frequency switching in response to a command signal at least one of the Q first power transistors and the Q second power transistors of the power supply means. A switching operation means for operating the motor, wherein the energization control means includes a Q-phase first energization control signal responsive to a holding state of the state transition means and Q
A second energization control signal for the Q phase, and the Q first power transistors and the Q power supply corresponding to the first energization control signal for the Q phase and the second energization control signal for the Q phase. Means for controlling the energization state of the second power transistors, and making the energization section of each of the first power transistors and each of the second power transistors greater than 360 / Q degrees in electrical angle; The switching operation means,
A switching pulse signal is generated in response to the command signal, and at least one of the Q first power transistors and the Q second power transistors is driven in response to the switching pulse signal. A voltage comparing means for substantially comparing each terminal voltage of the Q-phase coil with a common voltage of the coil; and a voltage detecting means responsive to the switching pulse signal. The output signal of the voltage comparison means is logically gated by the noise removal signal thus obtained, and a second predetermined time including a time point when the switching pulse signal changes from off to on and a second time point including a time point when the switching pulse signal changes from on to off A noise canceller that invalidates the output signal of the voltage comparison means during at least one of the predetermined times. It is configured to include a means.

With this configuration, since the switching operation means switches the power transistor of the power supply means at high frequency, the power loss of the power transistor of the power supply means can be greatly reduced, and the heat generation of the motor is greatly reduced. Can be reduced. Further, the voltage detecting means, the state transition means, and the energization control means generate a detection pulse signal in response to the terminal voltage of the coil, and in response to the detection pulse signal, transition the energization phase to the coil, and move the rotor in a predetermined direction. It is rotating. Therefore, the position detecting element becomes unnecessary, and the configuration of the motor is simplified. Further, the energizing section of the first power transistor and the second power transistor is set to be larger than 360 / Q degree in electrical angle, and the two power transistors are simultaneously energized when the current path is switched. As a result, the switching of the current path becomes smooth, and the pulsation of the generated driving force is reduced. As a result,
It becomes a motor with low noise. Further, the voltage detecting means is constituted by the voltage comparing means and the noise removing means, and the output signal of the voltage comparing means is subjected to logic gate processing by the noise removing signal in response to the switching pulse signal. In particular, the output signal of the voltage comparison means is at least one of a first predetermined time including a time when the switching pulse signal changes from off to on and a second predetermined time including a time when the switching pulse signal changes from on to off. Is invalidated, it is possible to create a detection pulse signal in which the influence of noise accompanying the high-frequency switching operation of the power transistor is eliminated. Further, since the detection pulse signal corresponding to the output signal of the voltage comparison means is generated, a detection pulse signal corresponding to the comparison result of the terminal voltages of the coils can be obtained. Therefore, the switching operation of the current path to the coil can be performed at an accurate timing in response to the detection pulse signal of the voltage detection means, and the rotor can be rotationally driven with high accuracy. Also,
For example, when speed control is performed in response to the output pulse signal of the voltage detection means, the rotation speed of the rotor can be controlled with high accuracy. That is, high-precision motor rotation can be realized without being affected by high-frequency switching noise. as a result,
Based on the present invention, a high-performance motor with low heat generation and low vibration and noise can be realized at low cost.

A motor according to still another aspect of the present invention includes a rotor provided with a field portion for generating a field magnetic flux, and a Q phase (Q is an integer of 3 or more) disposed on a stator.
, A voltage supply means having two output terminals for supplying a DC voltage, and Q first power supplies for supplying power from the first output terminal side of the voltage supply means to one end of the coil.
A power transistor comprising: a power transistor configured to supply power to one end of the coil from a second output terminal side of the voltage supply unit; and a terminal of the coil. Voltage detection means for generating a detection pulse signal responsive to a voltage; state transition means for transitioning a holding state in response to the detection pulse signal of the voltage detection means; and electric power in response to a holding state of the state transition means. Energization control means for controlling energization of the power transistor of the supply means, and at least one of the Q first power transistors and the Q second power transistors of the power supply means responsive to a command signal And a switching operation means for performing a high-frequency switching operation, wherein the state transition means is a detection pulse of the voltage detection means. The holding state is changed from the first state to the second state after a first adjustment time from the arrival of the signal, and a second adjustment time (second adjustment time> first adjustment time) from the arrival of the detection pulse signal. A) further comprising means for further changing the holding state from the second state to the third state later, wherein the energization control means comprises a first energization control of the Q phase in response to the holding state of the state transition means. And generating a Q-phase second energization control signal, the Q-phase first power transistors corresponding to the Q-phase first energization control signal and the Q-phase second energization control signal. Means for controlling the energization state of the Q second power transistors to make the energization section of each of the first power transistors and each of the second power transistors greater than 360 / Q degrees in electrical angle. Said switching operation means A current detection means for obtaining a current detection signal responsive to a supply current to the Q-phase coil from the voltage supply means, and comparing the output signal of the current detection means with the command signal, and responding to the comparison result. A switching pulse signal is generated, and in response to the switching pulse signal, at least one of the Q first power transistors and the Q second power transistors of the power supply means is set to a high frequency. It is configured to include switching control means for performing a switching operation.

With this configuration, since the switching operation means causes the power transistor of the power supply means to perform high-frequency switching, the power loss of the power transistor of the power supply means can be greatly reduced, and the heat generation of the motor can be greatly reduced. Can be reduced. Further, the voltage detecting means, the state transition means, and the energization control means generate a detection pulse signal in response to the terminal voltage of the coil, and in response to the detection pulse signal, transition the energization phase to the coil, and move the rotor in a predetermined direction. It is rotating. Therefore, the position detecting element becomes unnecessary, and the configuration of the motor is simplified. Further, the state transition means changes the holding state from the first state to the second state after a first adjustment time from the arrival of the detection pulse signal of the voltage detection means, and a second adjustment time from the arrival of the detection pulse signal. After (second adjustment time> first adjustment time), the holding state is further changed from the second state to the third state. The energization control unit generates a Q-phase first energization control signal and a Q-phase second energization control signal in response to the holding state of the state transition unit, and generates the Q-phase first energization control signal.
Control the energization state of the Q first power transistors and the Q second power transistors in response to the energization control signal and the Q-phase second energization control signal. The energizing section of the second power transistor is made larger than 360 / Q degrees in electrical angle. Further, the switching operation means performs the high-frequency switching operation of at least one of the Q first power transistors and the Q second power transistors while transmitting the voltage from the voltage supply means to the Q-phase coil. The supply current is controlled in response to the command signal. Thereby, while the at least one power transistor controls the current of the high frequency switching operation, the Q first power transistors or Q
Two of the second power transistors are simultaneously energized. Therefore, the current supplied to the coil is accurately controlled in response to the command signal, and the pulsation of the generated driving force is reduced. Furthermore, in the switching of the current path, the two power transistors are simultaneously energized, the switching of the current path becomes smooth, and the pulsation of the generated driving force is further reduced. as a result,
Based on the present invention, a high-performance motor with low heat generation and low vibration and noise can be realized at low cost.

The switching operation means compares the output signal of the current detection means with a command signal for obtaining a current detection signal responsive to the supply current to the Q-phase coil from the voltage supply means, and A switching pulse signal responsive to the result is generated, and the Q first power transistors and Q
It is possible to include switching control means for causing at least one of the second power transistors to perform a high-frequency switching operation.
Accordingly, even when two of the Q first power transistors and the Q second power transistors are simultaneously turned on at the time of switching of the current path, the voltage from the voltage supply means is not changed. The current supplied to the Q-phase coil can be easily controlled in response to the command signal. As a result, a motor with low power consumption and low vibration and noise is obtained.

Also, for example, by changing the first adjustment time and the second adjustment time in response to the arrival interval of the detection pulse signal, even if the rotation speed of the rotor changes, the energizing section can be reliably performed. Can be greater than 360 / Q degrees. Thereby, even when the rotation speed of the rotor changes over a wide range, at least one power transistor controls the current of the high-frequency switching operation, and the Q first power transistors or 2 of the Q second power transistors
The power transistors can be energized simultaneously. As a result, the current supplied to the coil is controlled in response to the command signal, and a smooth switching operation is performed by the two power transistors when switching the current path, and the pulsation of the generated driving force is significantly reduced. . as a result,
Low power consumption, vibration and
A high-performance motor with low noise and variable rotation speed over a wide range can be realized at low cost.

According to the present invention, there is provided a disk drive having at least a head for reproducing a signal from a disk or recording a signal on the disk, and at least processing an output signal of the head to output a reproduced information signal. Information processing means for processing a recording information signal and outputting the signal to the head means; a rotor having a field portion for directly rotating and driving the disk to generate a field magnetic flux; and a stator. , A voltage supply unit having two output terminals for supplying a DC voltage, and a first output terminal side of the voltage supply unit. Q first power transistors for supplying power to one end, and a second
Power supply means including Q second power transistors for supplying power from the output terminal side to one end of the coil, and voltage detection for generating a detection pulse signal in response to a terminal voltage of the coil Means, state transition means for changing a holding state in response to a detection pulse signal of the voltage detection means, and energization control for controlling energization of a power transistor of the power supply means in response to the holding state of the state transition means. Means for switching at least one of the Q first power transistors and the Q second power transistors of the power supply means in response to a command signal to perform a high-frequency switching operation. The power supply control means, wherein:
A Q-phase first energization control signal and a Q-phase second energization control signal are generated in response to the holding state of the state transition means, and the Q-phase first energization control signal and the Q-phase second energization control signal are generated. Control the energization state of the Q first power transistors and the Q second power transistors in response to the energization control signals of The switching operation means generates a switching pulse signal in response to the command signal, wherein the switching operation means generates a switching pulse signal in response to the command signal, and includes the Q first power transistors and the Means for causing at least one of the Q second power transistors to perform a high-frequency switching operation in response to the switching pulse signal; The voltage detecting means may include a first stop time including a time point when the high-frequency switching operation of the at least one power transistor changes from off to on and a second stop time including a time point when the at least one power transistor changes from on to off. During at least one stop time, the detection operation of the detection pulse signal is stopped, and the detection pulse responded to the terminal voltage of the coil at least when the at least one power transistor is turned on except for the at least one stop time. It is configured to include means for performing a signal detecting operation.

With this configuration, since the switching operation means causes the power transistor of the power supply means to perform high-frequency switching, the power loss of the power transistor of the power supply means can be greatly reduced, and the heat generation of the disk drive can be greatly reduced. Can be reduced to Further, the voltage detecting means, the state transition means, and the energization control means create a detection pulse signal in response to the terminal voltage of the coil, and in response to the detection pulse signal, transition the energization phase to the coil, thereby moving the disk in a predetermined direction. It is rotating. Therefore, a position detecting element becomes unnecessary, and the configuration of the disk device is simplified. Further, the energizing section of the first power transistor and the second power transistor is set to be larger than 360 / Q degree in electrical angle, and the two power transistors are simultaneously energized when the current path is switched. As a result, the switching of the current path becomes smooth, and the pulsation of the generated driving force is reduced. As a result, a disk device with small vibration and noise is obtained. Further, the power transistor is caused to perform high-frequency switching operation by the switching pulse signal, and at least one of a first stop time including a time point when the power transistor changes from off to on and a second stop time including a time point when the power transistor changes from on to off. Since the detection operation of the detection pulse signal is stopped during one stop time, erroneous detection due to high frequency noise generated in the terminal voltage due to the high frequency switching operation of the power transistor can be prevented. In addition, since the detection operation of the detection pulse signal in response to the comparison result of the terminal voltage of the coil is performed at least at the time of the ON operation of the power transistor except for the at least one stop time, the detection pulse corresponding to the comparison result of the terminal voltage is performed. Can create signals. That is, a detection pulse signal accurately responding to the terminal voltage can be obtained. Therefore, the switching operation of the current path to the coil can be performed at an accurate timing in response to the detection pulse signal of the voltage detection means, and the disk can be driven to rotate with high accuracy. Further, for example, when speed control is performed in response to an output pulse signal of the voltage detection means, the rotation speed of the disk can be controlled with high accuracy. That is, high-precision disk rotation can be realized without the influence of high-frequency switching noise. As a result, based on the present invention, heat generation is small,
A high-performance disk device with low vibration and noise can be realized at low cost.

According to another aspect of the present invention, there is provided a disk apparatus that reproduces a signal from the disk or records a signal on the disk, and processes at least an output signal of the head. An information processing means for outputting a reproduction information signal or a signal processing of a recording information signal to output to the head means, and a field portion for directly rotating and driving the disk to generate a field magnetic flux. Rotor and the Q arranged on the stator
A coil having a phase (Q is an integer of 3 or more), voltage supply means having two output terminals for supplying a DC voltage, and power supply from a first output terminal side of the voltage supply means to one end of the coil. Power supply means comprising: Q first power transistors to perform power supply; and Q second power transistors to supply power from the second output terminal side of the voltage supply means to one end of the coil. Voltage detection means for generating a detection pulse signal in response to a terminal voltage of the coil; state transition means for transitioning a holding state in response to the detection pulse signal of the voltage detection means; and a holding state of the state transition means. Energization control means for controlling energization of the power transistors of the power supply means in response to the power supply means, the Q first power transistors and the Q second power transistors of the power supply means. A disk apparatus comprising a switching operation means for high-frequency switching operation, the in response to at least one command signal among the static,
The energization control unit generates a Q-phase first energization control signal and a Q-phase second energization control signal in response to the holding state of the state transition unit, and generates the Q-phase first energization control signal. The energization state of the Q first power transistors and the Q second power transistors is controlled in response to the Q-phase second energization control signal, and each of the first power transistors and each of the first power transistors are controlled. A switching section configured to generate a switching pulse signal in response to the command signal, wherein the switching operation section generates a switching pulse signal in response to the command signal; 1
And a means for causing at least one of the Q second power transistors to perform a high-frequency switching operation in response to the switching pulse signal. A voltage comparing means for substantially comparing each terminal voltage of the phase coil with a common voltage of the coil, and a logic gate processing of an output signal of the voltage comparing means by a noise removal signal in response to the switching pulse signal; The output signal of the voltage comparison means is provided at least one of a first predetermined time including a time point when the switching pulse signal changes from off to on and a second predetermined time including a time point when the switching pulse signal changes from on to off. And noise removing means for invalidating the noise.

With this configuration, since the switching operation means switches the power transistor of the power supply means at high frequency, the power loss of the power transistor of the power supply means can be greatly reduced, and the heat generation of the disk drive can be greatly reduced. Can be reduced. Further, the voltage detecting means, the state transition means, and the energization control means create a detection pulse signal in response to the terminal voltage of the coil, and in response to the detection pulse signal, transition the energization phase to the coil, thereby moving the disk in a predetermined direction. It is rotating. Therefore, a position detecting element becomes unnecessary, and the configuration of the disk device is simplified. Further, the energizing section of the first power transistor and the second power transistor is set to be larger than 360 / Q degree in electrical angle, and the two power transistors are simultaneously energized when the current path is switched. As a result, the switching of the current path becomes smooth, and the pulsation of the generated driving force is reduced. As a result, a disk device with small vibration and noise is obtained. Further, the voltage detecting means is constituted by the voltage comparing means and the noise removing means, and the output signal of the voltage comparing means is subjected to logic gate processing by the noise removing signal in response to the switching pulse signal. In particular, the output signal of the voltage comparison means is at least one of a first predetermined time including a time when the switching pulse signal changes from off to on and a second predetermined time including a time when the switching pulse signal changes from on to off. Is invalidated, it is possible to create a detection pulse signal in which the influence of noise accompanying the high-frequency switching operation of the power transistor is eliminated. Further, since the detection pulse signal corresponding to the output signal of the voltage comparison means is generated, a detection pulse signal corresponding to the comparison result of the terminal voltages of the coils can be obtained. Therefore, the switching operation of the current path to the coil can be performed at an accurate timing in response to the detection pulse signal of the voltage detection means, and the disk can be driven to rotate with high accuracy. Further, for example, when speed control is performed in response to an output pulse signal of the voltage detection means, the rotation speed of the disk can be controlled with high accuracy. That is, high-precision disk rotation can be realized without the influence of high-frequency switching noise. As a result, based on the present invention, a high-performance disk device that generates less heat and has less vibration and noise can be realized at low cost.

According to another aspect of the present invention, there is provided a disk apparatus that reproduces a signal from the disk or records a signal on the disk, and processes at least an output signal of the head. And outputs a reproduction information signal, or information processing means for performing signal processing on the recording information signal and outputting the signal to the head means, and a field portion for directly rotating and driving the disk to generate a field magnetic flux. Voltage supply means having a mounted rotor, a Q-phase (Q is an integer of 3 or more) coil disposed on the stator, two output terminals for supplying a DC voltage, and a first of the voltage supply means Q first power transistors for supplying power from the output terminal side to one end of the coil, and power supply from the second output terminal side of the voltage supply means to one end of the coil A power supply means including Q second power transistors, a voltage detection means for generating a detection pulse signal responsive to a terminal voltage of the coil, and a power supply means responsive to a detection pulse signal of the voltage detection means. State transition means for transitioning the holding state of the power supply means, energization control means for controlling energization of a power transistor of the power supply means in response to the holding state of the state transition means, and the Q first power supply means. At least one of the Q power transistors and the Q second power transistors.
A switching operation means for performing a high-frequency switching operation in response to a command signal, wherein the state transition means holds the state after a first adjustment time from the arrival of the detection pulse signal of the voltage detection means. State 1
From the second state to the second state, and after the second adjustment time (second adjustment time> first adjustment time) from the arrival of the detection pulse signal, the holding state is changed from the second state to the third state. The energization control means creates a Q-phase first energization control signal and a Q-phase second energization control signal in response to the holding state of the state transition means, The first energization control signal of the Q phase and the second energization control signal of the Q phase
Control the energization state of the Q first power transistors and the Q second power transistors in response to the energization control signals of Energized section in electrical angle 36
The switching operation means includes a current detection means for obtaining a current detection signal in response to a current supplied from the voltage supply means to the Q-phase coil; Comparing the output signal of the means with the command signal, creating a switching pulse signal in response to the comparison result, and in response to the switching pulse signal, the Q first power transistors of the power supply means and the It is configured to include switching control means for causing at least one of the Q second power transistors to perform a high-frequency switching operation.

With this configuration, since the switching operation means switches the power transistor of the power supply means at a high frequency, the power loss of the power transistor of the power supply means can be greatly reduced, and the heat generation of the disk drive can be greatly reduced. Can be reduced. Further, the voltage detecting means, the state transition means, and the energization control means generate a detection pulse signal in response to the terminal voltage of the coil, and in response to the detection pulse signal, transition the energization phase to the coil, and move the rotor in a predetermined direction. It is rotating. Therefore, a position detecting element becomes unnecessary, and the configuration of the disk device is simplified. In addition, the state transition means is configured to perform the first state from the arrival of the detection pulse signal of the voltage detection means.
After the adjustment time, the holding state is changed from the first state to the second state, and the holding state is changed to the second state after a second adjustment time (second adjustment time> first adjustment time) from the arrival of the detection pulse signal. Is further changed to the third state. The energization control unit generates a Q-phase first energization control signal and a Q-phase second energization control signal in response to the holding state of the state transition unit, and generates the Q-phase first energization control signal and the Q-phase The energization state of the Q first power transistors and the Q second power transistors is controlled in response to the second energization control signal, and the energization section of each first power transistor and each second power transistor is controlled. Is greater than 360 / Q degrees in electrical angle. Further, the switching operation means performs the high-frequency switching operation of at least one of the Q first power transistors and the Q second power transistors while transmitting the voltage from the voltage supply means to the Q-phase coil. The supply current is controlled in response to the command signal. Thus, while at least one power transistor controls the current of the high-frequency switching operation, two of the Q first power transistors or the Q second power transistors are switched at the time of switching the current path.
The power transistors are in the energized state at the same time.
Therefore, the current supplied to the coil is accurately controlled in response to the command signal, and the pulsation of the generated driving force is reduced. Furthermore, in the switching of the current path, the two power transistors are simultaneously energized, the switching of the current path becomes smooth, and the pulsation of the generated driving force is further reduced.
Therefore, the disk can be rotationally driven with low vibration and low noise and with high precision. As a result, based on the present invention, a high-performance disk device that generates less heat and has less vibration and noise can be realized at low cost.

The switching operation means compares the output signal of the current detection means with a command signal for obtaining a current detection signal corresponding to the supply current to the Q-phase coil from the voltage supply means, and A switching pulse signal responsive to the result is generated, and the Q first power transistors and Q
It is possible to include switching control means for causing at least one of the second power transistors to perform a high-frequency switching operation.
Accordingly, even when two of the Q first power transistors and the Q second power transistors are simultaneously turned on at the time of switching of the current path, the voltage from the voltage supply means is not changed. The current supplied to the Q-phase coil can be easily controlled in response to the command signal. As a result, a disk device with low power consumption and low vibration and noise can be obtained.

Further, for example, by changing the first adjustment time and the second adjustment time in response to the arrival interval of the detection pulse signal, even if the rotational speed of the disk changes, the energizing section can be reliably performed. Can be greater than 360 / Q degrees. Thereby, even in the case of a disk device in which the rotation speed of the disk is changed over a wide range, at least one power transistor controls the current of the high-frequency switching operation while the Q first transistors are switched in the current path. Two of the power transistors or the Q second power transistors can be simultaneously turned on. As a result, the current supplied to the coil is controlled in response to the command signal, and a smooth switching operation is performed by the two power transistors when switching the current path, and the pulsation of the generated driving force is significantly reduced. . As a result, a high-performance disk drive that can reduce power consumption, reduce disk vibration and noise, and change the disk rotation speed in a wide range can be realized at low cost without using a position detection element. These and other configurations and operations will be described in detail in the description of the embodiments.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a motor and a disk device including the motor according to the present invention will be described with reference to the accompanying drawings.

First Embodiment FIGS. 1 to 12 show a motor according to a first embodiment of the present invention and a disk device including the motor. FIG. 1 is a block diagram showing the overall configuration of the disk device according to the first embodiment. Rotor 1
1 is provided with a field part for generating a field magnetic flux of a plurality of poles by a magnet magnetic flux. Here, a field portion formed by a two-pole permanent magnet magnetic flux is shown, but a multipolar field portion formed by a magnet magnetic flux can be generally configured. Three-phase coil 12, 1
The reference numerals 3 and 14 are disposed on the stator, and are electrically displaced from each other by 120 degrees relative to the rotor 11. Here, the electrical angle of 360 degrees corresponds to a pair of angular widths of the north pole and the south pole of the rotor. Each coil 12, 13,
One end of 14 is connected in common, and the other end is connected to the output terminal side of the power supply unit 20 as a power supply terminal. Three
The phase coils 12, 13, and 14 are driven by three-phase drive currents I1, I
A two-phase magnetic flux is generated by I2 and I3, and a driving force is generated by an interaction with the field portion of the rotor 11 to give the driving force to the rotor 11. The disk 1 is integrally fixedly attached to the rotor 11, and is directly rotated by the rotor 11.

A digital information signal (for example, a high-quality audio / video signal) is recorded on the disk 1, and a signal from the disk 1 is reproduced by the head 2 composed of an optical head or a magnetic head. ing. The information processing section 3 processes an output signal from the head 2 and reproduces a reproduction information signal (for example, a high-quality audio / video signal).
Is output. The disk device of the first embodiment can record digital information signals on the disk 1.
A head 2 composed of an optical head or a magnetic head performs signal recording on the disk 1. The information processing section 3 supplies a recording signal obtained by subjecting an input recording information signal (for example, a high-quality audio / video signal) to signal processing to the head 2, and causes the head 2 to record the signal on the disk 1.

FIG. 24A shows an example of a disk device for reproducing a signal. The disk 1 is directly driven to rotate integrally with the rotor 11. Digital information signals are recorded on the disk 1 at high density. The head 2 reproduces an information signal on the rotating disk 1 and outputs a reproduction signal Pf. The information processing section 3 digitally processes the reproduction signal Pf from the head 2 and outputs the reproduction information signal Pf.
Output g. Here, illustration of the stator and the coil is omitted. FIG. 24B shows an example of a disk device that performs signal recording. The disk 1 is directly driven to rotate integrally with the rotor 11. The disc 1 is a recordable disc, and can record digital information signals at high density.
The information processing section 3 digitally processes the input recording information signal Rg, and outputs a recording signal Rf to the head 2. The head 2 records the recording signal Rf on the rotating disk 1 at a high density, and transmits a new information signal to the disk 1.
Form on top. As the head 2, a read-only head, a recording / playback head, or a recording-only head is used depending on the situation.

The power supply unit 20 shown in FIG.
In response to the lower energization control signal M (M1, M2, M3) and the upper energization control signal N (N1, N2, N3) from the voltage supply unit 25 to the three-phase coils 12, 13, and 14. Then, power is supplied to the coils 12, 13, and 14. FIG. 2 shows a specific configuration of the power supply unit 20. FIG.
The three lower power transistors 101 forming a power supply path between the negative terminal side (ground side) of the voltage supply section 25 and the respective power supply terminal sides of the coils 12, 13 and 14 , 102, 103 and three upper power transistors 105, 106 forming a power supply path between the positive terminal side (Vm side) of the voltage supply section 25 and the respective power supply terminal sides of the coils 12, 13, 14. , 107 are included. The upper power transistors 105, 106,
107 includes upper power diodes 105d and 10 in parallel.
6d and 107d are reverse-connected, and the lower power diodes 101d, 102d and 103d are reverse-connected in parallel with the lower power transistors 101, 102 and 103. Here, the lower power transistors 101, 102, 10
3 and N-channel MOS field-effect power transistors are used for the upper power transistors 105, 106, and 107, and the upper field-effect power transistors 10
Parasitic diodes formed in reverse connection from the current outflow terminal side to the current inflow terminal side of 5, 106, 107 are used as upper power diodes 105d, 106d, 107d, and lower field-effect power transistor 101,
Parasitic diodes formed by being reversely connected from the current outflow terminal side to the current inflow terminal side of 102 and 103 are used as lower power diodes 101d, 102d and 103d.

In the first embodiment, a field effect transistor is used as the upper power transistor and the lower power transistor. However, the present invention is not limited to this.
A transistor may be used. Further, the present invention is not limited to the field effect transistors having the same polarity, and field effect transistors having different polarities may be used. For example, a field-effect power transistor having a P-channel MOS structure can be used for the upper power transistor, and a field-effect power transistor having an N-channel MOS structure can be used for the lower power transistor.

In the power supply section 20, the lower operation circuits 111, to which the lower energization control signals M1, M2, M3 are input,
112 and 113 are lower energization control signals M1, M2 and M3
The lower power transistors 101, 102, 1
03 on / off operation. The lower power transistors 101, 102, and 103 form a current path for supplying the negative currents of the drive currents I1, I2, and I3 to the coils 12, 13, and 14. Lower energization control signals M1, M2, M3
Is a digital PWM signal (pulse width modulation signal) in each energization section, and the lower energization control signal M
Lower power transistor 1 to which 1, M2 and M3 are input
01, 102, and 103 perform on / off high-frequency switching operations. For example, the lower power transistor 101
Is ON, the terminal voltage V1 of the coil 12 becomes 0 V or substantially 0 V, and the driving current I1
Supply. When the lower power transistor 101 is turned off, the upper power diode 105d or the upper power transistor 105 is turned on, and the terminal voltage V1 of the coil 12 becomes equal to or higher than Vm or substantially Vm.
2, a negative drive current I1 is continuously supplied. As a result, the terminal voltage V1 of the coil 12 becomes a PWM voltage that digitally changes between approximately 0 V and approximately Vm. As described above, in each energizing section of the lower power transistors 101, 102, 103, the coils 12, 13, 14
Terminal voltages V1, V2, and V3 are PWM voltages.

In the power supply section 20, the upper operation circuit 115, to which the upper energization control signals N1, N2, N3 are input,
116, 117 are upper side energization control signals N1, N2, N3
The upper power transistors 105, 106, 1
07 on / off operation. Normally, the upper power transistors 105, 106, 107
A current path for supplying the positive currents of the drive currents I1, I2, and I3 to the power supply 14 is formed. The high-voltage output circuit 120 in the power supply unit 20 generates and outputs a high potential Vu that is higher than the positive potential Vm of the voltage supply unit 25 by a predetermined value. As a result, the high potential Vu can be applied to the control terminals of the upper power transistors 105, 106, and 107, and the N-channel field-effect power transistor can be fully turned on. In the first embodiment, the upper power transistors 105, 106, and 107 having the same phase as the lower power transistors 101, 102, and 103 that perform on-off high-frequency switching operations are complementarily operated to perform on-off high-frequency switching operations. It is possible to reduce the power loss of the upper power diodes 105d, 106d, 107d.

As shown in FIG. 12, the current detector 21
It is configured to include a current detection resistor 125, and the lower power transistors 101, 102, 10
3, a current detection signal Ad proportional to a supply current or a supply current Ig supplied to the three-phase coils 12, 13, and 14
Is output. As shown in FIG. 1, the voltage detection unit 30 includes a voltage comparator 41 and a detection pulse generator 42. The voltage comparator 41 includes three-phase coils 12, 13,
14, three-phase terminal voltages V1, V2, V3,
Further, the common voltage Vc of the commonly connected midpoint terminals of the coils 12, 13, 14 is input. The voltage comparator 41
Substantially three-phase terminal voltages V1, V2, V3 and common voltage V
c, and selectively compares them directly, and outputs a selection voltage comparison signal Bj corresponding to the comparison result. Detection pulse generator 42
Outputs a detection pulse signal Dt from which the high-frequency switching noise included in the selection voltage comparison signal Bj has been removed. 3 and 4 are circuit diagrams each showing a specific configuration of the voltage comparator 41. FIG. 5 is a circuit diagram showing a specific configuration of the detection pulse generator 42.

The three comparator circuits 151, 152, 153 of the voltage comparator 41 shown in FIG.
1, V2, and V3 are compared with the common voltage Vc, and three-phase comparison pulse signals b1, b2, and b3 corresponding to the comparison result are output. The inverter circuits 155, 156, 157
The pulse signals b5, b6, and b7 are output by inverting the comparison pulse signals b1, b2, and b3. Switches 161, 162, 163, 164, 165, 1 of signal selection circuit 160
66 selects any one of the pulse signals b1, b2, b3, b5, b6 and b7 according to the selection command signal Bs1 of the selection command circuit 150, and outputs it as a selection voltage comparison signal Bj. The selection command circuit 150 outputs a selection command signal Bs1 corresponding to the holding state of the state transition unit 31, which will be described later, and substantially compares the terminal voltage reflecting the energization state to the coils 12, 13, and 14 with the common voltage. A pulse signal is selected and output as a selected voltage comparison signal Bj.

FIG. 4 is a circuit diagram showing another configuration of the voltage comparator 41. The composite voltage circuit 17 of the voltage comparator 41 in FIG.
0 means that the three-phase terminal voltages V1, V2, V3
172, 173 to create a combined common voltage Vcr. Switch 18 of first signal selection circuit 180
1, 182, 183 selectively input any of the terminal voltages V1, V2, V3 to the comparator circuit 185 in accordance with the first selection command signal Bs2 of the selection command circuit 195. The comparator circuit 185 compares the selected terminal voltage with the combined common voltage Vcr, and outputs a comparison pulse signal b8. The inverter circuit 186 outputs a pulse signal b9 obtained by inverting the comparison pulse signal b8. The switch 191 of the second signal selection circuit 190 switches the pulse signals b8 and b9 according to the second selection command signal Bs3 of the selection command circuit 195.
And outputs it as a selected voltage comparison signal Bj. The selection command circuit 195 outputs a first selection command signal Bs2 and a second selection command signal Bs3 in response to the holding state of the state transition unit 31 described later, and outputs the three-phase coils 12, 1
A pulse signal that substantially compares the terminal voltage reflecting the energization state to the terminals 3 and 14 with the common voltage is selected and output as a selected voltage comparison signal Bj.

FIG. 5 is a circuit diagram of the detection pulse generator 42 of the voltage detector 30. As shown in FIG. 5, the noise removal circuit 201 of the detection pulse generator 42 uses the high-frequency switching operation of the power supply unit 20 to perform the selection voltage comparison signal Bj.
And functions to prevent noise pulses corresponding to the switching operation from being generated in the output signal Ca of the noise removing circuit 201. The noise removal circuit 201
For example, it is configured by an AND circuit 211, and logically synthesizes a selection voltage comparison signal Bj and a noise removal signal Wx of a switching control unit 22 described later. That is, the output signal Bj of the voltage comparator 41 is logically gated by the noise removal signal Wx. Thereby, the noise removal circuit 20
1 is independent of the selection voltage comparison signal Bj when the noise removal signal Wx is "L" (low potential state) and is selected when the noise removal signal Wx is "H" (high potential state). The level of the voltage comparison signal Bj is directly output. As a result, even if a noise pulse is generated in the selection voltage comparison signal Bj by the high-frequency switching operation of the power supply unit 20, the noise pulse is removed from the output signal Ca of the noise removal circuit 201, and the terminal of the coil is removed. It outputs an accurate pulse signal in response to the voltage comparison result.

The pulse generation circuit 202 of the voltage detector 30
Changes the detection pulse signal Dt to “H” at the time when the rising edge of the output signal Ca of the noise removal circuit 201 arrives.
To change. The pulse generation circuit 202 is constituted by, for example, a D-type flip-flop 212, and triggers the "H" level input to the data terminal by the output signal Ca of the noise removal circuit 201 input to the clock terminal. As a result, the detection pulse signal Dt changes to “H” at the rising edge of the output signal Ca of the noise removal circuit 201, and holds that state. The state transition unit 31 described later generates a third timing adjustment signal F3 after a required time from the rise of the detection pulse signal Dt, and the D-type flip-flop 21 of the pulse generation circuit 202
2 is reset to "L". Accordingly, the state of the detection pulse signal Dt changes in direct response to the rising edge of the selection voltage comparison signal Bj from which the noise pulse has been removed, and the state of the detection pulse signal Dt changes to that state until the arrival of the next third timing adjustment signal F3. Hold.

As shown in FIG. 1, the state transition section 31 includes a timing adjuster 43 and a state holder 44. Each time the rising edge of the detection pulse signal Dt of the voltage detection unit 30 arrives, the timing adjuster 43
A first timing adjustment signal F1 delayed by the second adjustment time T2, a second timing adjustment signal F2 delayed by the second adjustment time T2, and a third timing adjustment signal F3 delayed by the third adjustment time T3. Is output. The state holder 44 changes the holding state in response to the first timing adjustment signal F1 and the second timing adjustment signal F2, and changes the first state signals P1 to P6 and the second state signal corresponding to the holding state. Q1 to Q6 are output.

FIG. 6 is a block diagram showing a specific configuration of the timing adjuster 43. FIG. 7 is a circuit diagram showing a specific configuration of the state holder 44. The edge detection circuit 301 of the timing adjuster 43 shown in FIG. 6 generates a first differential pulse signal Da and a second differential pulse signal Db in response to a rising edge of the detection pulse signal Dt. The second differentiated pulse signal Db is output as a pulse immediately after the first differentiated pulse signal Da. The second counter circuit 304 and the third
The counter circuit 305 loads a value corresponding to the internal data signal Dc of the first counter circuit 303 at that time at the pulse generation edge of the first differential pulse signal Da. Thereafter, when the edge of the second differential pulse signal Db occurs, the first counter circuit 303 is reset. That is, due to the occurrence of the rising edge of the detection pulse signal Dt, the internal data of the second counter circuit 304 and the third counter circuit 305 have a value corresponding to the internal data signal Dc of the first counter circuit 303 at that time. Loaded, the first counter circuit 303 resets the internal state to zero or a predetermined value.

The clock circuit 30 of the timing adjuster 43
2 outputs a first clock signal CK1, a second clock signal CK2, and a third clock signal CK3. The first counter circuit 303 receives the clock of the first clock signal CK1 and counts up the internal data every time a pulse of the first clock signal CK1 arrives. When the internal data increases to a predetermined value, the first counter circuit 303 stops counting up further and holds that value. The second counter circuit 304 receives the clock of the second clock signal CK2 and outputs the second clock signal C2.
The internal data is counted down every time the K2 pulse arrives. When the internal data is reduced to zero or a predetermined value, the second counter circuit 304 stops counting down further and outputs a first zero pulse signal Df. The first pulsing circuit 307 differentiates the first zero pulse signal Df and outputs a first timing adjustment signal F1.
Before the generation of the first zero pulse signal Df, the logic gate circuit 306 keeps the output clock signal Dk in the “L” state,
After the generation of the zero pulse signal Df, the third clock signal CK
3 is output as the output clock signal Dk and supplied to the third counter circuit 305. Third counter circuit 305
When the output clock signal Dk is clocked, the internal data is counted down every time a pulse of the output clock signal Dk arrives. When the internal data is reduced to zero or a predetermined value, the third counter circuit 305 stops counting down any further and outputs a second zero pulse signal Dg. The second pulsing circuit 308 differentiates the second zero pulse signal Dg to generate a second timing adjustment signal F2.
Is output. The delay pulsing circuit 310 differentiates a signal delayed for a required time from the generation of the second zero pulse signal Dg, and outputs a third timing adjustment signal F3 which is a differentiated pulse signal. The delay pulsing circuit 310 has the same configuration as the circuit configured by the third counter circuit 305 and the second pulsing circuit 308. That is, the value corresponding to the internal data signal Dc of the first counter circuit 303 is loaded into the fourth counter circuit, and after the generation of the second zero pulse signal Dg, the data loaded into the fourth counter circuit is required. When the internal data of the fourth counter circuit is reduced to zero or a predetermined value, further counting down is stopped and a third zero pulse signal is generated. The third pulsing circuit differentiates the third zero pulse signal and outputs a third timing adjustment signal F3. Note that the delay pulsing circuit 3
10 may generate a delayed pulse signal delayed by a predetermined time after the generation of the second zero pulse signal Dg, and differentiate the delayed pulse signal to output a third timing adjustment signal F3.

FIG. 13 illustrates the relationship between these signal waveforms. In FIG. 13, the horizontal axis is time. A count value corresponding to a time interval T0 (pulse interval T0) between rising edges of the detection pulse signal Dt in FIG. 13A is counted by the first counter circuit 303. The second counter circuit 304 outputs the first zero pulse signal Df with a delay by a first adjustment time T1 (T1 <T0) proportional to the time interval T0 (see FIG. 13B). As a result, the first timing adjustment signal F1 becomes a pulse signal delayed by a first adjustment time T1 substantially proportional to the time interval T0 from the time of occurrence of the rising edge of the detection pulse signal Dt ((FIG. c)). After the rising edge of the first zero pulse signal Df occurs, the third counter circuit 305 outputs the second zero pulse signal Dg with a delay of a required time proportional to the time interval T0 (FIG. 1).
3 (d)). As a result, the second timing adjustment signal F2 is a pulse signal delayed by a second adjustment time T2 (T1 <T2 <T0) substantially proportional to the time interval T0 from the time when the rising edge of the detection pulse signal Dt occurs. (See FIG. 13E). Similarly, the delay pulsing circuit 310 outputs a third timing adjustment signal F3 delayed by a required time from the time when the rising edge of the second zero pulse signal Dg occurs (see FIG. 13 (f)). As a result, the third timing adjustment signal F3 has a time interval T from the time when the rising edge of the detection pulse signal Dt occurs.
A third adjustment time T3 (T2 <T3
The pulse signal is delayed by <T0). The third timing adjustment signal F3 is input to the pulse generation circuit 202 of the detection pulse generator 42, and the third timing adjustment signal F3
3, the detection pulse signal Dt is reset (see FIG. 13A).

The state holder 44 shown in FIG. 7 includes a first state holding circuit 320 and a second state holding circuit 330. The first state holding circuit 320 has six D
Type flip-flops 321,322,323,324,
325 and 326, and one of the flip-flops is in the “H” state, and the other flip-flops are in the “L” state.
It is configured to be in a state. At the rising edge of the first timing adjustment signal F1, the states of the flip-flops 321, 322, 323, 324, 325, and 326 change, and the “H” state moves like a ring counter. The first state holding circuit 320 includes six flip-flops 321, 322, 323, 324, 3
25, 326 are first state signals P1, P2,
Output as P3, P4, P5, P6. The second state holding circuit 330 includes six D-type flip-flops 331,
332, 333, 334, 335, 336, and flip-flops 331, 332, 333, 33
The first state signals P1, P2, P3, P4, P5, and P6 are input to data input terminals of 4,335 and 336, respectively. At the rising edge of the second timing adjustment signal F2, the flip-flops 331, 332, 3
33, 334, 335, 336 are the first state signals P1,
P2, P3, P4, P5, and P6 are input to the internal state, and the output is changed. The second state holding circuit 330
Flip-flops 331, 332, 333, 33
4, 335, 336 as second state signals Q1,
Output as Q2, Q3, Q4, Q5, Q6. As described above, the holding state of the state holder 44 (P1 to P6 and Q1 to Q6)
Q6) is the first timing adjustment signal F
The transition from the first holding state to the second holding state by the arrival of 1 and the transition from the second holding state to the third holding state by the subsequent arrival of the second timing adjustment signal F2. Then, a total of 12 holding states are sequentially transited.

The energization control unit 32 shown in FIG. 1 includes the first state signals P1 to P6 of the state transition unit 31 and the second state signal Q
Lower energization control signals M1, M2, M3 responsive to 1 to Q6
And the upper energization control signals N1, N2, N3. Therefore, the section for energizing the coil is determined by the first state signal and the second state signal. In addition, the energization control unit 32
In response to the main PWM pulse signal Wm and the auxiliary PWM pulse signal Wh of the switching controller 22, the lower energization control signal M
1, M2, M3 and the upper energization control signals N1, N2, N3 are converted into PWM pulses.

FIG. 8 is a circuit diagram showing a specific configuration of the energization control unit 32. In FIG. 8, a first selection circuit 401
Are the first state signals P1 to P6 of the state transition unit 31 and the second
The first selection signal Mm using the state signals Q1 to Q6 of FIG.
1, Mm2 and Mm3 are created. First selection signal Mm
1, Mm2, Mm3 are in the “H” state during the lower power transistors 101, 102, 1 of the power supply unit 20.
The operation 03 corresponds to an energization section in which the negative currents of the drive currents I1, I2, and I3 are supplied to the coils 12, 13, and 14, respectively. The second selection circuit 402 includes the state transition unit 31
First state signals P1 to P6 and second state signals Q1 to Q6
6 to generate the second selection signals Nn1, Nn2, Nn3. During the period in which the second selection signals Nn1, Nn2, and Nn3 are in the “H” state, the drive currents I1, I2, This corresponds to an energizing section in which a positive current of I3 flows.

The first pulse synthesizing circuit 403 logically synthesizes the main PWM pulse signal Wm of the switching control section 22 and the first selection signals Mm1, Mm2, Mm3, respectively, and forms a pulse in the lower energization section within the energization section. Signals M1, M2,
M3 is output. Depending on the connection state of the switch circuit 461 in the auxiliary selection circuit 406, the upper auxiliary signal Wj becomes a signal that matches the auxiliary PWM pulse signal Wh of the switching control unit 22 or becomes an “L” state.

The second pulse synthesizing circuit 404 logically synthesizes the upper auxiliary signal Wj and the first selection signals Mm1, Mm2, Mm3, respectively, and generates auxiliary energization control signals Mm5, Mm6,
Mm7 is output. When the switch circuit 461 of the auxiliary selection circuit 406 is connected to the Sa side, the upper auxiliary signal W
j coincides with the auxiliary PWM pulse signal Wh, and the second pulse synthesizing circuit 404 outputs the first selection signals Mm1, Mm2, Mm
Auxiliary energization control signal Mm pulsed in the "H" section of No. 3
5, Mm6 and Mm7 are output. When the switch circuit 461 of the auxiliary selection circuit 406 is connected to the Sb side, the upper auxiliary signal Wj becomes “L”, and the auxiliary energization control signals Mm5, Mm6, Mm7 of the second pulse synthesis circuit 404 are set.
Becomes "L". The third pulse synthesizing circuit 405 is connected to the second
The upper energization control signals N1, N2, and N3 obtained by combining the selection signals Nn1, Nn2, and Nn3 with the auxiliary energization control signals Mm5, Mm6, and Mm7 by logical OR for each phase are output.

FIG. 14 shows the first selection signals Mm1, Mm2,
Mm3 and the second selection signals Nn1, Nn2, Nn3 and the first
FIG. 7 is a waveform diagram showing a signal relationship between the state signals P1 to P6 and the second state signals Q1 to Q6. In FIG. 14, the horizontal axis is time. The first state signals P1 to P6 are six-phase signals in which a signal that becomes “H” shifts at each generation timing of the first timing adjustment signal F1 ((a) to (b) of FIG. 14).
(F)). The second state signals Q1 to Q6 are six-phase signals in which the signal that becomes “H” shifts at each generation timing of the second timing adjustment signal F2 ((g) in FIG. 14).
To (l)). First selection signals Mm1, Mm2, Mm
3 is a first state signal P1 to P6 and a second state signal Q1
To Q6, and is a three-phase signal having an “H” interval greater than 120 degrees in electrical angle (see (p) to (r) in FIG. 14). Specifically, the first selection signal M
m1, Mm2, and Mm3 are three-phase signals having an "H" section of about 140 degrees. Here, the electrical angle of 360 degrees corresponds to a pair of rotation angles of the north pole and the south pole of the rotor. Similarly,
The second selection signals Nn1, Nn2, and Nn3 are created by logically synthesizing the first state signals P1 to P6 and the second state signals Q1 to Q6, and are “H” greater than 120 degrees in electrical angle.
This is a three-phase signal having a section (see (m) to (o) in FIG. 14). Specifically, the second selection signals Nn1, Nn2, N
n3 is a three-phase signal having an "H" section of about 140 degrees. Further, the first selection signals Mm1, Mm2, M
m3 and the second selection signal Nn1, Nn2, Nn3 are inverted signals having a phase difference of 180 degrees in electrical angle (for example, Mm1 and Nn1).

The command section 35 shown in FIG. 1 includes, for example, a speed detection mechanism, and has a command signal A of the command section 35.
c is a voltage signal created by the speed detection mechanism.
The speed detection mechanism of the command unit 35 includes, for example, the voltage detection unit 3
The rotational speeds of the disk 1 and the rotor 11 are detected by the detection pulse signal Dt of 0, and a command signal Ac corresponding to the difference between the rotational speed of the disk 1 and the target speed is created. Therefore, the command signal Ac of the command unit 35 is a voltage signal corresponding to the output pulse signal Dt of the voltage detection unit 30. In addition,
Not only the detection pulse signal Dt, but also a rotation speed can be detected and a command signal can be generated by a pulse signal corresponding to the result of comparison of the terminal voltages of the voltage detection unit 30.

The switching control unit 22 shown in FIG.
The main PWM which compares the current detection signal Ad of the current detection unit 21 with the command signal Ac of the command unit 35 and responds to the comparison result
It outputs a pulse signal Wm, an auxiliary PWM pulse signal Wh, and a noise removal signal Wx. Main P of the switching controller 22
The WM pulse signal Wm and the auxiliary PWM pulse signal Wh are input to the energization control unit 32, and the noise removal signal Wx of the switching control unit 22 is output to the detection pulse generator 4 of the voltage detection unit 30.
2 is input.

FIG. 9 is a block diagram showing a specific configuration of the switching control unit 22. As shown in FIG. 9, the switching control unit 22 includes a comparison pulse unit 501 and a PWM pulse unit 502. Comparison pulser 50
1 compares the command signal Ac with the current detection signal Ad and outputs a basic PWM pulse signal Wp corresponding to the comparison result. The PWM pulse generator 502 generates a main PWM pulse signal Wm, an auxiliary PWM pulse signal Wh, and a noise removal signal Wx from the basic PWM pulse signal Wp. FIG. 10 and FIG.
1 is a block diagram showing a specific configuration of the comparison pulser 501, and FIG. 12 is a block diagram showing a specific configuration of the PWM pulser 502.

The comparison pulse device 501 shown in FIG. 10 includes a comparison circuit 511 and a time delay circuit 512. The comparison circuit 511 includes a command signal Ac and a current detection signal A.
d, and when the current detection signal Ad becomes larger than the command signal Ac, the comparison signal Ap is changed to “H”. The basic PWM pulse signal Wp of the time delay circuit 512 becomes “L” for a predetermined time Tf triggered by the arrival of the rising edge of the comparison signal Ap, and changes to “H” after the predetermined time Tf elapses.

FIGS. 15A and 15B are waveform diagrams showing the signal relationship between the comparison signal Ap and the basic PWM pulse signal Wp. In FIG. 15, the horizontal axis is time. Comparison signal Ap
Is "L" when the current detection signal Ad is smaller than the command signal Ac, and changes to "H" when the current detection signal Ad becomes larger than the command signal Ac. The basic PWM pulse signal Wp becomes "L" for a predetermined time Tf from the time when the comparison signal Ap changes to "H". When the basic PWM pulse signal Wp becomes "L", the energization by the lower power transistor is stopped, the current detection signal Ad becomes zero, and the comparison signal Ap
Becomes "L". When the required time Tf has elapsed, the basic PW
The M pulse signal Wp changes to “H”, and the lower power transistors 101, 102, 103 form the coils 12, 1.
The energization to 3 and 14 is restarted. In this way, the basic P
The WM pulse signal Wp includes the current detection signal Ad and the command signal Ac.
PWM signal (pulse width modulation signal) responding to the comparison result of
become.

FIG. 11 shows a comparison pulse generator 5 having another configuration.
It is a block diagram showing No. 01. Comparison pulser 5 of FIG.
01 includes a comparison circuit 521, a reference pulse circuit 522, and a basic PWM pulse circuit 523. The comparison circuit 521 compares the command signal Ac with the current detection signal Ad, and changes the comparison signal Ap to “H” when the current detection signal Ad becomes larger than the command signal Ac. The reference pulse circuit 522 outputs a reference pulse signal Ar at predetermined time intervals. The basic PWM pulse circuit 523 includes, for example, a flip-flop, and sets the internal state to “H” and sets the basic PWM pulse signal Wp to “H” by the occurrence of a rising edge of the reference pulse signal Ar. The basic PWM pulse circuit 523 sets the internal state to “L” and sets the basic PWM pulse signal Wp to “L” by the occurrence of the rising edge of the comparison signal Ap. 16A to 16C show the reference pulse signal Ar, the comparison signal Ap, and the basic PWM pulse signal W.
It is a waveform diagram which shows the signal relationship of p. In FIG. 16, the horizontal axis is time. When the rising edge of the reference pulse signal Ar occurs, the basic PWM pulse signal Wp becomes “H”.
, And the basic PWM pulse signal Wp becomes “L” when the rising edge of the comparison signal Ap occurs. In this way, the basic PWM pulse signal Wp becomes the current detection signal A
It becomes a PWM signal responsive to the result of comparison between d and the command signal Ac. Further, in a section where the reference pulse signal Ar becomes “H”, the basic PWM pulse signal Wp is forcibly set to “L”,
The basic PWM pulse signal Wp is reliably transmitted at predetermined time intervals.
The switching signal changes between H "and" L ".

The PWM pulse generator 502 shown in FIG.
First overall delay circuit 551 and second overall delay circuit 552
And a logic synthesis output circuit 553. The first overall delay circuit 551 delays the basic PWM pulse signal Wp of the comparison pulser 501 by a first predetermined time Ta or approximately Ta as a whole.
a is output. The second overall delay circuit 552 delays the first overall delay pulse signal Wa by a second predetermined time Tb or about Tb as a whole.
b is output. The logic synthesis output circuit 553 has a basic PWM
The pulse signal Wp, the first overall delay pulse signal Wa and the second
Are logically synthesized to output a main PWM pulse signal Wm, an auxiliary PWM pulse signal Wh, and a noise removal signal Wx.

FIGS. 17A to 17F show the basic PWM pulse signal Wp, the first whole delay pulse signal Wa, the second whole delay pulse signal Wb, the main PWM pulse signal Wm, the auxiliary PWM pulse signal Wh, FIG. 5 is a waveform diagram showing a signal relationship between the noise reduction signal Wx and a noise removal signal Wx. In FIG. 17, the horizontal axis is time. The first whole delay pulse signal Wa is a basic PWM.
The pulse signal Wp is a signal that is entirely delayed by a first predetermined time Ta, and the second whole delay pulse signal Wb is a signal obtained by totally delaying the first whole delay pulse signal Wa by a second predetermined time Tb. (A) of FIG.
(C)). Since the main PWM pulse signal Wm output from the logic synthesis output circuit 553 is obtained by outputting the first whole delay pulse signal Wa via the buffer circuit 561, the main PWM pulse signal Wm has the same waveform as the first whole delay pulse signal Wa. (See (b) and (d) of FIG. 17).

The auxiliary PWM pulse signal Wh output from the logic synthesis output circuit 553 is the basic PWM pulse signal Wp
And the second overall delay pulse signal Wb are logically synthesized by the NOR circuit 562, and have a waveform shown in FIG. The “H” level of the auxiliary PWM pulse signal Wh
The section is in the “L” section of the main PWM pulse signal Wm,
Both the main PWM pulse signal Wm and the auxiliary PWM pulse signal Wh do not go "H" at the same time. That is, a time difference of the first predetermined time Ta or the second predetermined time Tb is provided between the “H” section of the auxiliary PWM pulse signal Wh and the “H” section of the main PWM pulse signal Wm.

The noise removal signal Wx output from the logic synthesis output circuit 553 is the same as the basic PWM pulse signal Wp and the second
17 is logically synthesized by the exclusive NOR circuit 563, and has the waveform shown in FIG. The “L” section of the noise removal signal Wx is
It includes a point in time at which the main PWM pulse signal Wm changes, and has at least a predetermined time width Tb from the point in time of the change. The noise elimination signal Wx is input to the noise elimination circuit 201 of the detection pulse generator 42 of the voltage detection unit 30, and removes noise mixed in the comparison detection signal of the terminal voltage of the coil with the high-frequency switching operation of the power transistor. I do. Note that the noise removal signal Wx may be created by logically synthesizing the main PWM pulse signal Wm and the second overall delay pulse signal Wb using an exclusive NOR circuit. The “L” section of the noise removal signal Wx at this time substantially includes a point in time when the switching operation of the power transistor changes from off to on and a point in time from on to off. That is, the noise removal signal Wx is generated in response to the basic PWM pulse signal Wp, and is set to be “L” during a predetermined time including a change time point of the switching operation of the power transistor. The time ratio at which the noise removal signal Wx becomes “L” is about 20% (less than 50%), and the time for detecting the terminal voltage of the coil is longer than the time for noise removal.

Next, the overall operation and advantages of the first embodiment will be described. In response to the first state signals P1 to P6 and the second state signals Q1 to Q6 of the state transition unit 31,
The energization control unit 32 outputs lower energization control signals M1, M2, M3 and upper energization control signals N1, N2, N3, and selects a coil to be energized. The power supply unit 20 includes the power supply control unit 3
2, the lower power transistors 101, 102, 103 and the upper power transistor 1 in response to the lower energization control signals M1, M2, M3 and the upper energization control signals N1, N2, N3.
05, 106, and 107 are turned on and off to supply power to the three-phase coils 12, 13, and 14.

Switching control section 22 and current detection section 21
Forms a switching operation block, and a three-phase coil 1
The pulse-like drive voltage V converted to PWM in 2, 13, and 14
1, V2 and V3 are supplied. In response to the main PWM pulse signal Wm of the switching control unit 22,
The lower energization control signals M1, M2, and M3 of the energization controller 32 become PWM pulse signals. One or two lower power transistors 10 of the power supply unit 20 selected by the lower energization control signals M1, M2, M3 of the energization controller 32
1, 102, and 103 simultaneously perform high-frequency switching operations of on and off, and drive current I
1, I2 and I3 are supplied. Power supply unit 2
0, when the lower power transistors 101, 102, 103 are turned off, one or two upper power diodes 105d, 10d connected to the coil of the current-carrying phase due to the inductance action of the coils 12, 13, 14.
6d and 107d are turned on to supply continuous negative side drive currents I1, I2 and I3 to the coils 12, 13, and 14. As a result, the drive voltages V1, V2, and V3 to the three-phase coils 12, 13, and 14 become PWM voltages. Thereby, the lower power transistors 101,
The power loss of 102 and 103 is significantly reduced.

The upper power transistors 105, 106, and 107 of the power supply unit 20 include three-phase coils 12, 13,
14 is supplied with the positive currents of the drive currents I1, I2 and I3. First, the upper auxiliary signal Wj of the energization control unit 32 becomes “L”.
Will be described. This corresponds to a case where the switch circuit 461 of the auxiliary selection circuit 406 is connected to the Sb side. In this case, one or two upper power transistors 1 of the power supply unit 20 selected by the upper energization control signals N1, N2, N3 of the energization control unit 32
05, 106, and 107 are simultaneously turned on (no PWM operation is performed), and drive currents I1, I
2 and I3 are supplied. As a result, the driving currents I1, I in both directions alternating between the positive polarity and the negative polarity are applied to the three-phase coils 12, 13, 14 with the rotation of the rotor 11.
2, I3 are supplied. Further, the power loss of the upper power transistors 105, 106, 107 of the power supply unit 20 is significantly reduced.

Next, the upper auxiliary signal Wj of the power supply controller 32
Is the auxiliary PWM pulse signal Wh of the switching controller 22.
Will be described. This corresponds to the case where the switch circuit 461 of the auxiliary selection circuit 406 is connected to the Sa side. The auxiliary PWM pulse signal Wh is the main PWM
This is a PWM signal that turns off and on complementarily to the on / off PWM of the pulse signal Wm. The upper energization control signals N1, N2, and N3 of the energization controller 32 are the auxiliary PWM pulse signals Wh
In the section where the above-mentioned upper power diodes 105d, 106d, and 107d are turned on, the upper-side power transistors 105 and 1 having the same phase are included.
06, 107 are turned on. That is, the lower power transistor 10 that performs on / off high-frequency switching operation
The upper power transistors 105, 106, and 107 having the same phase as that of the lower power transistors 1
The on / off high-frequency switching operation is performed in a complementary manner to the on / off high-frequency switching operations of 01, 102, and 103. Thereby, the upper power diode 105d,
The power loss generated at 106d and 107d can be reduced, and the power loss and heat generation can be further reduced. Note that the auxiliary PWM pulse signal Wh is auxiliary and its operation may be eliminated as described above. That is, the switch circuit 461
Is connected to the Sb side.

The current detector 21 detects the current or supply current Ig supplied by the voltage supply unit 25 to the coils 12, 13 and 14 via the three lower power transistors 101, 102 and 103 of the power supply unit 20. And outputs a current detection signal Ad. This supply current Ig is a three-phase coil 1
It corresponds to the combined value of the negative-side currents of the three-phase drive currents I1, I2, and I3 to 2, 3, and 14. Switching control unit 2
2 compares the current detection signal Ad with the command signal Ac, and responds to the comparison result with the main PWM pulse signal Wm and the auxiliary Pm signal Wm.
It outputs a WM pulse signal Wh. The lower power transistors 101, 102, and 103 of the power supply unit 20 include a main PWM.
In response to the pulse signal Wm, a high-frequency switching operation of ON / OFF is performed, and drive voltages (terminal voltages) V1, V2, and V3 to the coils 12, 13, and 14 are set to PWM voltages. As a result, the supply current Ig is controlled in response to the command signal Ac. As a result, the drive currents I1, I2, and I3 to the three-phase coils 12, 13, and 14 can be accurately controlled in response to the command signal Ac, and pulsation of the generated drive force can be reduced. That is, vibration and noise of the disk 1 and the rotor 11 can be significantly reduced.

The lower power transistors 101, 102, and 103 of the power supply unit 20 supply the main PWM pulse signal Wm, which is a single pulse signal of the switching control unit 22.
In response to this, the high-frequency switching operation of ON / OFF is performed at the same time, so that the configuration is simple. When the upper auxiliary signal Wj is fixed at “L”, the power supply unit 20
The upper power transistors 105, 106 and 107 of P
Since no WM operation is performed, the energization switching is extremely easy. Further, the upper power transistor 1 of the power supply unit 20
Even when the switches 05, 106, and 107 are turned on and off at a high frequency in response to the auxiliary PWM pulse signal Wh, they operate in response to a single pulse signal.
A gap time can be easily provided between the main PWM pulse signal Wm and the auxiliary PWM pulse signal Wh, and it is easy to simultaneously turn on the lower power transistors 101, 102, 103 and the upper power transistors 105, 106, 107 in the same phase. Can be prevented.

The voltage comparator 41 of the voltage detection unit 30 is configured to output substantially three-phase terminal voltages V1, V2, and V3 and a common terminal voltage V
and c directly. In response to the first state signals P1 to P6 and / or the second state signals Q1 to Q6 of the state transition unit 31, the selection command circuit 195 outputs a selection command signal. A comparison result of the terminal voltages selected by the selection command signal is output as a selection voltage comparison signal Bj. Thereby, the coil 1 corresponding to the holding state of the state transition unit 31
The terminal voltages 2, 13, and 14 can be easily selected, detected and compared, and a pulse-like selection voltage comparison signal Bj corresponding to the selected and detected comparison result is obtained. That is, the coil 1 to be detected and compared with the rotation of the disk 1 and the rotor 11
2, 13 and 14 are selected, and the selected voltage comparison signal Bj directly responds to the comparison result of the selected and detected terminal voltages.
Can be obtained.

The noise elimination circuit 201 of the detection pulse creator 42 of the voltage detection unit 30 performs logic gate processing on the selected voltage comparison signal Bj of the voltage comparator 41 with the noise elimination signal Wx, and performs the PWM included in the selected voltage comparison signal Bj. An output signal Ca from which the influence of noise has been removed is obtained. That is, the noise removal signal Wx of the switching control unit 22 is
It is kept at “L” for at least a predetermined time from the time point of change including the time point of change of the pulse signal Wm. Therefore, by taking the AND logic of the noise removal signal Wx and the selection voltage comparison signal Bj, noise mixed in the selection voltage comparison signal Bj accompanying the PWM operation of the power transistor is removed. As a result, the output signal Ca of the noise elimination circuit 201 accurately reflects the comparison result of the terminal voltages of the coils. In particular, since the power transistor of the power supply unit 20 performs a high-frequency switching operation in response to the main PWM pulse signal Wm which is a single pulse signal, the noise removal signal Wx for removing the influence of the PWM noise can be easily created. .

The pulse generation circuit 2 of the detection pulse generator 42
02, the detection pulse signal Dt is set to “H” by the arrival of the rising edge of the output signal Ca of the noise removal circuit 201.
, And the detection pulse signal Dt is reset to “L” by the third timing adjustment signal F3 generated after the third adjustment time T3 from the time of the change. Thereby, for example, even if the rising edge of the output signal Ca of the noise removal circuit 201 is erroneously generated twice or more due to chattering in the comparison output of the terminal voltage, the detection pulse signal Dt of the pulse generation circuit 202 changes only once. Not configured. Therefore, malfunction prevention of the command signal Ac of the command unit 35 using the detection pulse signal Dt and malfunction prevention of the state transition unit 31 using the detection pulse signal Dt are performed.

The timing adjuster 43 of the state transition unit 31
Detects the arrival of the rising edge of the detection pulse signal Dt, and measures the time interval T0 of the arrival of the detection edge of the detection pulse signal Dt by the first counter circuit 303. Second
The first adjustment time T corresponding to the time interval T0 from the time when the edge of the detection pulse signal Dt arrives
A first timing adjustment signal F1 delayed by one is output. In addition, the second counter circuit 304 and the third counter circuit 305 delay the second timing adjustment signal F2 delayed by a second adjustment time T2 corresponding to the time interval T0 from the arrival of the edge of the detection pulse signal Dt. Output. Further, the delay pulsing circuit 310 detects the detection pulse signal Dt.
The third timing adjustment signal F3 delayed by the third adjustment time T3 corresponding to the time interval T0 from the time when the edge of the edge occurs.
Is output (see FIG. 13). These times are T1 <T
2 <T3 <T0.

The state holder 44 of the state transition section 31 has the first
The state of the first state holding circuit 320 is changed in response to the timing adjustment signal F1 of
Shift P6. Further, the state holder 44 of the state transition unit 31 changes the holding state of the second state holding circuit 330 in response to the second timing adjustment signal F2, and shifts the second state signals Q1 to Q6. Each time the first timing adjustment signal F1 and the second timing adjustment signal F2 arrive, the first state signals P1 to P6 and the second state signals Q1 to Q1
Q6 is sequentially shifted (see FIG. 14).

The first selection circuit 401 and the second selection circuit 402 of the energization control section 32 respond to the first and second state signals P1 to P6 and the second state signals Q1 to Q6 of the state transition section 31, respectively. One selection signal Mm1, Mm2, Mm3 and the second selection signal Nn1, Nn2, Nn3 are created. The first selection signals Mm1, Mm2, Mm3 and the second selection signals Nn1, Nn
2 and Nn3 determine the energizing section of the lower power transistors 101, 102 and 103 and the upper power transistors 105, 106 and 107, respectively. The energization control unit 32 outputs the first selection signals Mm1, Mm2, Mm
3 and the main PWM pulse signal Wm of the switching control unit 22
Are logically synthesized to generate lower energization control signals M1, M2, and M3, and the lower power transistor 10
1, 102 and 103 are turned on and off by a PWM switching operation. Thereby, power loss and heat generation of the lower power transistor are significantly reduced.

Switch circuit 461 of auxiliary selection circuit 406
Is connected to the Sb side, the upper auxiliary signal Wj
Becomes “L”, and the auxiliary energization control signals Mm5, Mm6, M
m7 also becomes “L”. Therefore, the energization control unit 32
The upper power supply control signals N1, N2, and N3 that match the selection signals Nn1, Nn2, and Nn3 are generated, and the upper power transistors 105, 106, and 107 of the power supply unit 20 are turned on and off (high-frequency switching operation is not performed). This reduces power loss and heat generation in the upper power transistor. Further, when the switch circuit 461 of the auxiliary selection circuit 406 is connected to the Sa side, the upper auxiliary signal Wj matches the auxiliary PWM pulse signal Wh, and “H” of the first selection signals Mm1, Mm2, Mm3. The auxiliary energization control signals Mm5, Mm6, and Mm7 are generated by pulsing the section. Third pulse synthesis circuit 405 of energization control unit 32
Logically synthesizes the second selection signals Nn1, Nn2, Nn3 and the auxiliary energization control signals Mm5, Mm6, Mm7 to create the upper energization control signals N1, N2, N3. In a section corresponding to the second selection signals Nn1, Nn2, Nn3,
Upper power transistors 105 and 10 of power supply unit 20
6, 107 are turned on / off (no high-frequency switching operation is performed). First selection signals Mm1, Mm2, M
m3, the upper power transistor 1 of the power supply unit 20 responds to the auxiliary PWM pulse signal Wh.
05, 106 and 107 are turned on and off by a high-frequency switching operation. Thereby, the upper power transistor 1
05, 106, 107 and upper power diode 105
Power loss and heat generation due to d, 106d, and 107d are greatly reduced.

In the first embodiment, as understood from the above description, the terminal paths of the coils 12, 13, and 14 are detected to switch the current path, thereby eliminating the need for the position detecting element. In addition, the power transistor that supplies drive current in both directions to the coil is turned on and off by high-frequency switching to greatly reduce power loss. That is, the lower power transistors 101, 102, and 103 are subjected to high-frequency switching operation of full on / off, and the upper power transistors 105, 106, and 107 are fully on / off to switch the current path, thereby significantly reducing power loss of the power transistors and power diodes. I made it smaller. As a result, heat generation of the motor and the disk device is significantly reduced, and recording / reproducing to / from a recordable disk can be stably performed.

In the first embodiment, the state transition unit changes the holding state from the first holding state in response to the first timing adjustment signal F1 generated after the first adjustment time T1 from the arrival of the detection pulse signal. Transition to the second holding state. Next, a second adjustment time T2 (T
2> T1) In response to the second timing adjustment signal F2 that occurs after T1), the state transition unit changes the holding state from the second holding state to the third holding state. The energization control unit generates a three-phase lower energization control signal and a three-phase upper energization control signal in response to the holding state of the state transition unit, and generates three lower power transistors 101, 102, 103 and three Of the upper power transistors 105, 106, 107 are controlled. Thereby, the three lower power transistors 10
1, 102, 103 and three upper power transistors 1
Each energizing section of 05, 106 and 107 is 360 / electrical angle.
3 = greater than 120 degrees. Further, the switching operation block includes three lower power transistors 10
1, 102, 103 and three upper power transistors 1
The current supplied from the voltage supply unit to the three-phase coils 12, 13, and 14 is controlled in response to a command signal while at least one of the power transistors 05, 106, and 107 performs high-frequency switching operation. In this way, at least one of the lower power transistors 101, 102, 103 or three of the three lower power transistors is controlled in the current path switching operation while controlling the supply current in response to the command signal by causing at least one power transistor to perform high-frequency switching operation. Out of the upper power transistors 105, 106, and 107 are simultaneously turned on. That is, even when the two power transistors are simultaneously energized, the current supplied to the three-phase coil is accurately controlled in response to the command signal. As a result, the pulsation of the generated driving force is reduced. Further, since the switching operation of the current path is made smooth by simultaneously turning on the two power transistors, the pulsation of the generated driving force is further reduced. As a result, a position detecting element is not required, power consumption is small, disk vibration and noise are small, and a high-performance motor or disk device can be realized at low cost. Further, the vibration and noise of the disk are significantly reduced, and the recording and reproduction on the disk are stabilized.

The switching operation block includes a current detection section 21 for detecting a current detection signal corresponding to a current supplied from the voltage supply section 25 to the three-phase coils 12, 13, and 14.
And the output signal of the current detection unit 21 and the command signal are compared,
And a switching control unit 22 for generating a switching pulse signal in response to the comparison result. Three lower power transistors 101, 102, 1
03 and three upper power transistors 105, 106,
At least one of the power transistors 107 may be configured to perform a high-frequency switching operation in response to a switching pulse signal. With this configuration, in the current path switching operation, the three lower power transistors 101, 102, 103 or the three upper power transistors 105, 106, 10
Even if two of the power transistors are simultaneously energized, the current supplied to the three-phase coils 12, 13, and 14 can be easily and accurately controlled in response to the command signal.

The state transition unit 31 changes the first adjustment time T1 and the second adjustment time T2 in response to the arrival interval T0 of the detection pulse signal. Thus, even if the rotation speed of the disk 1 changes over a wide range,
Lower power transistors 101, 102, 103 and three upper power transistors 105, 106, 107
Can be surely made larger than 360/3 = 120 degrees. In the first embodiment, the conduction interval of the upper power transistors 105, 106, 107 and the lower power transistors 101, 102, 103 is set to about 140 degrees (130 degrees to 150 degrees). This energizing section is, for example, 125 degrees or more and 180 degrees to reduce vibration and noise.
It may be larger within degrees.

In the first embodiment, one of the three lower power transistors 101, 102, 103
One or two power transistors are turned on / off by a high-frequency switching operation to realize a first switching operation in which one terminal voltage is subjected to a high-frequency switching operation and a second switching operation in which two terminal voltages are subjected to a high-frequency switching operation. Then, the first switching operation and the second switching operation were performed alternately with the rotation of the rotor. As described above, in the first embodiment, since only the lower power transistors 101, 102, and 103 are operated at the high frequency, the coils 12, 13, and 14 are operated.
Power supply terminal does not fall below the ground potential. As a result, when the lower power transistors 101, 102, and 103, the upper power transistors 105, 106, and 107, and many other transistors and resistors are joined and separated on a single silicon chip to form an integrated circuit, The unnecessary operation of the parasitic transistor accompanying the high-frequency switching operation of the power transistors 101, 102, and 103 is eliminated, and the operation of other integrated transistors is not hindered. That is, according to the configuration of the first embodiment, the entire operation is extremely stable. However, the present invention is not limited to such a configuration, and the lower power transistors 101, 102, 103
And at least one of the upper power transistors 105, 106, and 107 performs a high-frequency switching operation.
It is possible to control the supply current to 3,14.

In the first embodiment, the power transistor performing the high-frequency switching operation is switched between the first stop time including the time point of change from off to on and the second stop time including the time point of change from on to off. Stops the detection operation of the detection pulse signal, and detects the detection pulse signal in response to the comparison result of the terminal voltages of the coils 12, 13, and 14 during the remaining time excluding the first stop time and the second stop time. Is being implemented. Thereby, the power transistor PWM
Erroneous detection and malfunction due to noise accompanying the switching operation can be easily prevented.

In general, when at least one power transistor is subjected to high-frequency switching operation by a switching pulse signal, a first stop time including a time point when the power transistor changes from off to on and a time point when the power transistor changes from on to off are determined. The detecting operation of the detection pulse signal is stopped during at least one of the second stop times including the second stop time. The above-described effect can be obtained by performing the detection operation of the detection pulse signal in response to the comparison result of the terminal voltages of the coils 12, 13, and 14 at least at the time of the ON operation of the power transistor excluding the at least one stop time. It is preferable for obtaining. In particular, since the power transistor performs the high-frequency switching operation in response to a single switching pulse signal, the number of times that the switching of the power transistor changes is reduced, and the PWM is reduced.
It is possible to easily prevent a malfunction caused by noise accompanying the switching operation.

In the first embodiment, the detection pulse signal corresponding to the comparison result of the terminal voltages of the coils 12, 13, and 14 is generated in a relatively long time excluding the first stop time and the second stop time. Therefore, for example, the zero crossing point of the terminal voltage can be accurately detected. Further, in the first embodiment, the coils 12, 13, 14
Since the terminal voltage is not smoothed by a filter (a filter using a resistor or a capacitor), a detection pulse signal that quickly follows a change in the terminal voltage can be created. Here, the zero crossing point means a point in time at which the terminal voltage becomes substantially equal to the common voltage. As a result, by performing the switching operation of the current path to the coil in response to the detection pulse signal, the rotor and the disk can be rotationally driven with high accuracy. Further, for example, when the speed of a disk or a rotor is controlled by a command signal in response to an output pulse signal such as a detection pulse signal of a voltage detection unit, the rotation speed can be accurately controlled with low jitter. That is, a disk device that drives and controls the disk with high precision can be realized.

Further, the voltage detecting section 30 includes the coils 12, 1
It comprises a voltage comparator 41 for comparing the terminal voltages of the terminals 3 and 14, and a detection pulse generator 42 including a noise removing circuit 201. The noise elimination circuit 201 logically gates the selection voltage comparison signal Bj of the voltage comparator 41 with the noise elimination signal Wx in response to the main PWM pulse signal, which is a switching pulse signal, and when the switching pulse signal changes from OFF to ON. The selected voltage comparison signal Bj of the voltage comparator 41 is invalidated during a first predetermined time including the time and a second predetermined time including a change time point from on to off. This can easily prevent erroneous detection due to noise accompanying the PWM switching operation.

In general, the noise elimination circuit 201 performs logical gate processing on the selection voltage comparison signal Bj of the voltage comparator 41 with a noise elimination signal corresponding to the main PWM pulse signal, which is a switching pulse signal, and turns the switching pulse signal from off to on. Invalidating the selected voltage comparison signal Bj of the voltage comparator 41 in at least one of a first predetermined time including a change time point to the ON state and a second predetermined time including a change time point from the ON state to the OFF state. Accordingly, erroneous detection due to noise accompanying the PWM switching operation of the power transistor in response to the switching pulse signal can be easily prevented. In particular, since the power transistor performs the high-frequency switching operation in response to a single switching pulse signal, the noise removal signal Wx can be created by a simple circuit, and malfunction due to noise due to the switching operation can be easily prevented. The time ratio at which the noise removal signal Wx becomes “L” is about 20% (less than 50%), and the time for detecting the terminal voltages of the coils 12, 13, and 14 is longer than the time for noise removal. Therefore, the coils 12, 1
A detection pulse signal corresponding to the comparison result of the terminal voltages of the terminals 3 and 14 can be obtained, and the disk 1 and the rotor 11 can be driven to rotate with high accuracy.

Further, the voltage detecting section 30 includes a pulse generating circuit 202, and changes the state of the flip-flop in response to occurrence of a rising edge or a falling edge of the output signal of the noise removing circuit 201, and changes the state of the flip-flop. The responded detection pulse signal is created. This prevents the detection pulse signal from being excessively generated and stabilizes the energization control operation. That is, the first embodiment
In the disk device described above, the disk 1 and the rotor 11 are driven to rotate stably. Note that the flip-flop is reset by the third timing adjustment signal after a third adjustment time has elapsed from the edge of the detection pulse signal corresponding to the state change of the flip-flop. Since the third adjustment time is configured to change in response to the edge interval of the detection pulse signal, even if the rotation speed of the rotor 11 changes, it is possible to reliably prevent the generation of excessive pulses.

In the first embodiment, the upper power transistors 105, 106, and 107 of the same phase are turned off and on in a complementary manner with respect to the on / off high-frequency switching operation of the lower power transistors 101, 102, and 103. High-frequency switching operation. Thereby, the power loss due to the upper power diodes 105d, 106d, and 107d is reduced. Also, the on-voltage of the upper power diodes 105d, 106d, and 107d changes depending on the current, which may adversely affect the detection of the terminal voltages of the coils 12, 13, and 14. Upper power transistor 1
Since the high-frequency switching operation of the switches 05, 106, and 107 is actively performed, the influence of the on-voltage of the upper power diodes 105d, 106d, and 107d does not occur in the detection of the terminal voltages of the coils 12, 13, and 14.
As a result, an accurate terminal voltage detection operation can be performed. Also, the lower power transistors 101, 102,
103 and upper power transistors 105, 106, 10
A gap time is provided between these operations so that 7 does not turn on at the same time. Since the ON voltage of the upper power diodes 105d, 106d, and 107d is affected within the gap time, the operation of detecting the terminal voltages of the coils 12, 13, and 14 is stopped within the gap time by the noise removal signal Wx. Also, since these operations are performed in response to a single pulse signal, it can be easily realized with a very simple circuit configuration. In the first embodiment,
Although one or two upper power transistors are configured to perform complementary off-on high-frequency switching operations at the same time, the present invention is not limited to such a configuration, and only one upper power transistor is complementary. An off-on high-frequency switching operation may be performed.

The upper auxiliary signal Wj of the first embodiment is set to "L".
When fixed to the state, the lower power transistor 10
When 1, 102 and 103 are turned off, the upper power diodes 105d, 106d and 107d are turned on. In the detection of the terminal voltages of the coils 12, 13, and 14 by the voltage detection unit 30, the upper power diode 105
Erroneous detection may occur due to the influence of the ON voltages of d, 106d, and 107d. In order to prevent erroneous detection of the terminal voltages of the coils 12, 13, and 14 in the section where the upper power diodes 105d, 106d, and 107d are turned on, the noise removal signal Wx is devised to perform a high-frequency switching operation. Side power transistors 101 and 10
In only the ON operation section of 2,103, the coils 12, 13, 1
4 may be configured to detect the terminal voltage. The PWM pulse generator 502 of the switching control unit 22 shown in FIG.
Can be changed to the configuration shown in FIG. 18 to realize the above-described operation. The change in the configuration will be described below.

The PWM pulse unit 502 of the switching control unit 22 shown in FIG. 18 includes an overall delay circuit 811 and a logic synthesis output circuit 812. The whole delay circuit 811 includes a basic PWM pulse signal Wp of the comparison pulser.
Is delayed by a predetermined time Tc or about Tc to output a whole delay pulse signal Wc. Logic synthesis output circuit 8
Reference numeral 12 logically synthesizes the basic PWM pulse signal Wp and the entire delay pulse signal Wc, and outputs a main PWM pulse signal Wm, an auxiliary PWM pulse signal Wh, and a noise removal signal Wx. 19A to 19E show the basic PWM pulse signal W.
p, total delay pulse signal Wc, main PWM pulse signal W
FIG. 7 is a waveform diagram showing a signal relationship among m, an auxiliary PWM pulse signal Wh, and a noise removal signal Wx. In FIG.
The horizontal axis is time. The entire delay pulse signal Wc is the basic PW
This is a signal obtained by delaying the M pulse signal Wp as a whole by a predetermined time Tc (see FIGS. 19A and 19B).

The main PWM pulse signal Wm output from the logic synthesis output circuit 812 is obtained by outputting the basic PWM pulse signal Wp via the buffer circuit 821. Therefore, the main PWM pulse signal Wm has the same waveform as the basic PWM pulse signal Wp (see (c) of FIG. 19). The auxiliary PWM pulse signal Wh is fixed at the “L” state (see FIG. 19D). The noise removal signal Wx is obtained by logically synthesizing the basic PWM pulse signal Wp and the entire delay pulse signal Wc by the AND circuit 822.
The waveform shown in FIG. 9E is obtained. Thus, the “L” section of the noise elimination signal Wx includes the “L” section of the main PWM pulse signal Wm, and is a predetermined period from the time when the main PWM pulse signal Wm changes from “L” to “H”. It has a time width Tc.

By configuring the PWM pulse unit 502 of the switching control unit 22 as shown in FIG.
The lower power transistor 10 responds to the pulse signal Wm.
1, 102 and 103 perform on / off high frequency switching operation. Since the auxiliary PWM pulse signal Wh is "L", the upper power transistors 105, 106, 107
Does not perform high-frequency switching operation. Noise removal signal Wx
Is "L", the voltage detection unit 30 detects the coil 12, 1
The operation of detecting the terminal voltages of the terminals 3 and 14 is stopped. Therefore, during the predetermined time Tc including the time point when the power transistor changes from off to on, the voltage detection unit 30 controls the coils 12, 13,
The detection operation of the terminal voltage of the terminal 14 is stopped, and the detection operation of the detection pulse signal directly responding to the comparison result of the terminal voltages of the coils is performed when the power transistor is turned on after the lapse of the predetermined time Tc. As a result, erroneous detection due to noise accompanying the PWM switching operation of the power transistor
Malfunction can be prevented.

In order to perform such an operation, the main PW
A noise removal signal Wx corresponding to the M pulse signal Wh is generated, and a noise removal signal Wx is generated from a first predetermined time including a time when the power transistor changes from off to on and a second predetermined time including a time when the power transistor changes from on to off. The noise elimination signal Wx is set to "L" for at least one predetermined time, and the noise elimination signal Wx is set to "L" while the power transistor is off. The noise elimination circuit 201 of the voltage detection unit 30 performs logical gate processing on the output signal of the voltage comparator 41 based on the noise elimination signal Wx, and the noise elimination signal Wx becomes “
The output signal of the voltage comparator 41 is invalidated in the section of L ". That is, the first predetermined time including the time point when the power transistor changes from OFF to ON and the second signal including the time point when the power transistor changes from ON to OFF. Except for at least one of the predetermined times, the output signal of the voltage comparator 41 is enabled when the power transistor is turned on, and the coil 1
The detection operation of the detection pulse signal directly responding to the comparison result of the terminal voltages of 2, 13, and 14 is performed. This can prevent erroneous detection and malfunction due to noise accompanying the PWM switching operation of the power transistor.

Further, the PWM pulse unit 502 of the switching control unit 22 shown in FIG. 12 can be changed to the configuration shown in FIG. The change in the configuration will be described below. PWM of the switching control unit 22 shown in FIG.
The pulser 502 includes a first overall delay circuit 851, a second overall delay circuit 852, and a logic synthesis output circuit 853. The first overall delay circuit 851 outputs a first overall delay pulse signal Wa obtained by delaying the basic PWM pulse signal Wp of the comparison pulser 501 as a whole by a first predetermined time Ta or about Ta. The second whole delay circuit 852 outputs a second whole delay pulse signal Wb obtained by delaying the first whole delay pulse signal Wa as a whole by a second predetermined time Tb or about Tb. Logic synthesis output circuit 8
53 logically synthesizes the basic PWM pulse signal Wp, the first whole delay pulse signal Wa, and the second whole delay pulse signal Wb, and outputs a main PWM pulse signal Wm, an auxiliary PWM pulse signal Wh, and a noise removal signal Wx. I do.

FIGS. 21A to 21F show the basic PWM pulse signal Wp, the first overall delay pulse signal Wa, the second overall delay pulse signal Wb, the main PWM pulse signal Wm, the auxiliary PWM pulse signal Wh, FIG. 4 is a waveform diagram showing a signal relationship between the noise removal signal Wx and the noise removal signal Wx. In FIG. 21, the horizontal axis is time. The first whole delay pulse signal Wa is a basic PWM.
The pulse signal Wp is a signal which is entirely delayed by a first predetermined time Ta, and the second whole delay pulse signal Wb is a signal obtained by totally delaying the first whole delay pulse signal Wa by a second predetermined time Tb. (A) of FIG. 21)
(C)).

The main PWM pulse signal Wm output from the logic synthesis output circuit 853 is obtained by outputting the basic PWM pulse signal Wp and the first whole delay pulse signal Wa via the AND circuit 861. The waveform shown in FIG. The auxiliary PWM pulse signal Wh is obtained by logically synthesizing the basic PWM pulse signal Wp and the first whole delay pulse signal Wa by the NOR circuit 862, and has a waveform shown in FIG. The “H” section of the auxiliary PWM pulse signal Wh is “L” of the main PWM pulse signal Wm.
In the section, both the main PWM pulse signal Wm and the auxiliary PWM pulse signal Wh do not go to “H” at the same time.
That is, a time difference of the first predetermined time Ta is provided between the “H” section of the auxiliary PWM pulse signal Wh and the “H” section of the main PWM pulse signal Wm. The noise removal signal Wx is obtained by logically synthesizing the basic PWM pulse signal Wp and the second whole delay pulse signal Wb by the exclusive NOR circuit 863, and has a waveform shown in FIG.
The “L” section of the noise elimination signal Wx includes a change time point of the main PWM pulse signal Wm and has at least a predetermined time width Tb from the change time point. The “L” section of the noise removal signal Wx includes a change time point of the auxiliary PWM pulse signal Wh and has at least a predetermined time width Tb from the change time point. The noise elimination signal Wx is input to the noise elimination circuit 201 of the detection pulse generator 42 of the voltage detection unit 30 and becomes a comparison detection signal of the terminal voltages of the coils 12, 13, and 14 with the high-frequency switching operation of the power transistor. Eliminate generated noise.

By configuring the PWM pulse unit 502 of the switching control unit 22 as shown in FIG.
The lower power transistor 10 responds to the pulse signal Wm.
1, 102 and 103 perform on / off high frequency switching operation. In response to the auxiliary PWM pulse signal Wh, the upper power transistors 105, 106, and 107 perform a high-frequency switching operation of turning off and on. Noise removal signal W
In the section where x is “L”, the voltage detection unit 30
The operation of detecting the terminal voltages of the terminals 3 and 14 is stopped. Therefore,
The voltage detection unit 30 is connected to the coil during a first stop time including a time point when the lower power transistors 101, 102, and 103 change from off to on and a second stop time including a time point when the lower power transistors change from on to off. The detection operation of the terminal voltages of the terminals 12, 13, and 14 is stopped, and the detection operation of the detection pulse signal corresponding to the result of the comparison of the terminal voltages of the coils is performed in the remaining time excluding the first stop time and the second stop time. Let me. Further, the voltage detection unit 30 operates during the period of the first stop time including the time point when the upper power transistors 105, 106, and 107 change from on to off and the second stop time including the time point when the upper power transistor 105 changes from off to on. The detection of the terminal voltages of the coils 12, 13, and 14 is stopped, and the detection is performed in response to the comparison result of the terminal voltages of the coils 12, 13, and 14 during the remaining time excluding the first stop time and the second stop time. The detection operation of the pulse signal is performed. This can prevent erroneous detection and malfunction due to noise accompanying the PWM switching operation of the lower power transistors 101, 102, 103 and / or the upper power transistors 105, 106, 107.

These noise removing operations are performed by the noise removing signal Wx. That is, the noise removal signal Wx in response to the main PWM pulse signal and the auxiliary PWM pulse signal, which are switching pulse signals, takes a first predetermined time including a time point when the switching pulse signal changes from off to on and a change from on to off. It becomes “L” for a second predetermined time including the time point, and the noise removal circuit 201 of the voltage detection unit 30 outputs the voltage comparator 41 for these predetermined times.
Output signal is disabled.

Second Embodiment Next, a motor according to a second embodiment of the present invention and a disk device including the motor will be described with reference to the accompanying drawings. FIG.
2 and 23 are configuration diagrams showing a motor and a disk device including the motor according to the second embodiment of the present invention. FIG. 22 is a block diagram showing the overall configuration of the second embodiment. In the second embodiment, the voltage detection unit 30, the state transition unit 31, and the energization control unit 32 in the first embodiment described above.
And the required functions of the switching control unit 22 are configured by the hardware and software of the microcomputer unit 701. The same components as those in the first embodiment are given the same reference numerals, and the description thereof is omitted.

As the disk 1 and the rotor 11 rotate,
The power supply unit 20 changes the state of energization of the coils 12, 13, and 14. The voltage comparator 700 includes the coil 12,
The microcomputer 70 detects the terminal voltages of the terminals 13 and 14 and outputs a comparison pulse signal Z (Z1, Z2, Z3) corresponding to the terminal voltages.
Output to 1. FIG. 23 is a circuit diagram showing a specific configuration of voltage comparator 700.

The voltage comparator shown in FIG.
716, the terminal voltages V1,
V2 and V3 are divided to obtain divided terminal voltages V11, V22 and V
Create 33. The composite voltage circuit 720 converts the divided terminal voltages V11, V22, and V33 into resistors 721, 722, and 723.
To generate a combined common voltage Vcr. The comparator circuits 731, 732, and 733 compare the divided terminal voltages V11, V22, and V33 with the combined common voltage Vcr, and compare pulse signals Z1 and Z corresponding to the comparison result.
2 and Z3 are output. Thereby, the voltage comparator 700
Creates a comparison pulse signal that substantially compares the terminal voltages of the coils 12, 13, and 14 with the common voltage at the midpoint terminal.

The microcomputer unit 701 shown in FIG. 22 receives the comparison pulse signals Z1, Z2, and Z3 of the voltage comparator 700, and removes the influence of the PWM noise from the coil unit 701.
The change of the comparison pulse signal corresponding to the energization state to 2, 13, and 14 is detected. Based on this detection operation, a timing adjustment operation is performed at the first adjustment time T1 and the second adjustment time T2, and a transition of the holding state is performed. That is, an operation of selectively detecting the edges of the comparison pulse signals Z1, Z2, and Z3 is performed, and after the first adjustment time T1 after the detection, the state is changed from the first holding state to the second holding state (substantially the second holding state). 1
(The transition operation of the holding state by the timing adjustment signal F1), the third holding state after the second adjustment time T2.
(Substantially the holding state transition operation by the second timing adjustment signal F2). A total of 12 holding states are sequentially transitioned. Based on this holding state, the lower energization control signals M1, M2, M3 and the upper energization control signal N
1, N2 and N3 are determined. Also, the microcomputer unit 701 inputs the current detection signal Ad of the current detection unit 21 as a current digital signal obtained by AD conversion, and compares the current digital signal with the command digital signal. A main PWM pulse signal (switching pulse signal) corresponding to the comparison result is substantially created in a software manner, and the above-described lower energization control signals M1, M2, M3 are converted into PWM pulses. Further, an auxiliary PWM pulse signal that changes in synchronization with the main PWM pulse signal is substantially created in software, and logically synthesized with the above-described upper energization control signals N1, N2, and N3 to complement the lower energization control signal. PWM operation. In addition, a noise removal signal that changes in synchronization with the main PWM pulse signal is substantially created in a software manner, and the PWM signal included in the comparison pulse signal is generated.
A noise removal operation is performed.

In the second embodiment, the main PWM pulse signal, the auxiliary PWM pulse signal, the noise elimination signal, and the like do not need to be created as individual signals, and various modifications are possible. For example, P of the lower energization control signal
Necessary timings, such as the WM operation, the PWM operation of the upper energization control signal, and the noise removal operation, may be created by software of the microcomputer unit 701, and the required operation may be executed. This configuration is also included in the present invention. . Further, a part of the above operation is not limited to the software of the microcomputer unit 701,
It may be executed by hardware. In the second embodiment, the same operation and effect as in the first embodiment can be obtained by performing the same operation as in the first embodiment.

Third Embodiment Next, a motor according to a third embodiment of the present invention and a disk device including the motor will be described with reference to the accompanying drawings. FIG.
5 is a block diagram showing a configuration of a motor according to Embodiment 3 of the present invention. In the third embodiment, components having the same functions and configurations as those in the above-described embodiments are denoted by the same reference numerals,
The description is omitted. The rotor 11 is provided with a field portion that generates a plurality of poles of magnetic field magnetic flux. In the third embodiment, the field portion is formed by the two-pole permanent magnet magnetic flux. However, in general, a multi-pole field portion formed by the magnet magnetic flux can be configured. The three-phase coils 12, 13, and 14 are disposed on the stator, and
They are electrically shifted by 120 degrees. Here, the electrical angle of 360 degrees corresponds to a pair of angular widths of the north pole and the south pole of the rotor 11. One end of each of the coils 12, 13, 14 is commonly connected, and the other end is connected to the output terminal side of the power supply unit 20 as a power supply terminal. The three-phase coils 12, 13, and 14 generate a three-phase magnetic flux by the three-phase drive currents I1, I2, and I3, generate a driving force by interaction with a field part of the rotor 11, and drive the rotor 11 to rotate. I do.

The power supply section 20 includes a lower energization control signal M1, M2, M3 and an upper energization control signal N
1, N2, and N3, a current path from the voltage supply unit 25 to the three-phase coils 12, 13, and 14 is formed.
2, 13, and 14 are supplied. Since the specific configuration of the power supply unit 20 has been described in the first embodiment with reference to FIG. 2, detailed description thereof will be omitted.

The voltage detector 30 includes a voltage comparator 41 and a detection pulse generator 42. The voltage comparator 41 includes three-phase terminal voltages V1, V2, and V3 generated at one end of the three-phase coils 12, 13, and 14, and the coil 1
The common voltage V at the midpoint terminals of 2, 13, and 14 which are connected in common
c is input. The three-phase terminal voltages V1, V2, and V3 are substantially selectively directly compared with the common voltage Vc, and a selection voltage comparison signal Bj corresponding to the comparison result is output. The detection pulse generator 42 outputs a detection pulse signal Dt from which the high frequency switching noise included in the selection voltage comparison signal Bj of the voltage comparator 41 has been removed. The specific configuration of the voltage comparator 41 according to the third embodiment is described in the first embodiment.
Has been described with reference to FIGS. 3 and 4, and a detailed description thereof will be omitted. Further, since the specific configuration of the detection pulse generator 42 has been described in the first embodiment with reference to FIG. 5, the detailed description thereof will be omitted.

The state transition section 31 includes a timing adjuster 43
And a state holder 44. The timing adjuster 43 delays the first timing adjustment signal F1 delayed by the first adjustment time T1 and the second adjustment time T2 each time the rising edge of the detection pulse signal Dt of the voltage detection unit 30 arrives. Second timing adjustment signal F2
And outputs a third timing adjustment signal F3 delayed by a third adjustment time T3. The state holder 44 includes a first timing adjustment signal F1 and a second timing adjustment signal F2.
And changes the holding state, and outputs first state signals P1 to P6 and second state signals Q1 to Q6 corresponding to the holding state. That is, the state holder 44 of the state transition unit 31
Changes the holding state from the first state to the second state in response to the generation of the first timing adjustment signal F1, and changes the holding state to the second state in response to the generation of the second timing adjustment signal F2. A transition is made from the state 2 to the third state. Thus, the holding state of the state transition unit 31 sequentially transitions through a total of 12 states. Further, the third timing adjustment signal F3 is input to the detection pulse generator 42 of the voltage detector 30, and resets the detection pulse signal Dt. Timing adjuster 4
3 is the same as that shown in FIG.
Therefore, the detailed description is omitted. Since the specific configuration of the state holder 44 has been described in Embodiment 1 with reference to FIG. 7, the detailed description thereof will be omitted.

The energization control unit 32 controls the first state of the state transition unit 31.
And the lower energization control signals M1, M2, M3 and the upper energization control signals N1, N2, N3 in response to the state signals P1 to P6 and the second state signals Q1 to Q6. Therefore, coil 1
2, 13 and 14 are energized by the first state signal and the second state signal.
Is determined by the status signal. Also, the energization control unit 32
Is the main PWM pulse signal Wm of the switching controller 22.
And the lower energization control signals M1, M2, M3 and the upper energization control signals N1, N2, N
3 is converted into a PWM pulse. Since the specific configuration of the energization control unit 32 has been described in the first embodiment with reference to FIG. 8, detailed description thereof will be omitted.

The switching control unit 22 includes the current detection unit 2
1 and compares the current detection signal Ad with the command signal Ac, and outputs a main PWM pulse signal Wm, an auxiliary PWM pulse signal Wh, and a noise removal signal Wx corresponding to the comparison result. The main PWM pulse signal Wm and the auxiliary PWM of the switching control unit 22
The M pulse signal Wh is input to the energization control unit 32, and the noise removal signal Wx of the switching control unit 22 is
0 is input to the detection pulse generator 42. Command signal Ac
Is a voltage signal generated by, for example, a speed detection mechanism. The speed detection mechanism includes, for example, the voltage detection unit 30
The detection pulse signal Dt detects the rotation speed of the rotor 11 and generates a command signal Ac corresponding to the difference from the target speed. The specific configuration of the switching control unit 22 is as follows.
Since the first embodiment has been described with reference to FIG. 9, a detailed description thereof will be omitted.

The operation of the third embodiment is the same as the operation of the first embodiment already described, and a detailed description thereof will be omitted. Further, the motor of the third embodiment can obtain the same operation and effects as those of the first embodiment. Note that various modifications are possible for the specific configuration of each of the above-described embodiments. For example, each phase coil may be configured by connecting a plurality of partial coils in series or in parallel. The three-phase coils are not limited to the star connection, but may be a delta connection. Further, the number of phases of the coil is not limited to three. Generally, a configuration having coils of a plurality of phases can be realized. Further, the number of magnetic poles of the field portion of the rotor is not limited to two, but may be multi-pole.

In each of the above-described embodiments, a high-frequency switching operation is easily performed by using a field effect power transistor having an N-channel MOS structure as a power transistor of the power supply unit 20. This allows
The power loss and heat generation of the power transistor have been reduced and the integration into an integrated circuit has been simplified. However, the present invention is not limited to such a case. For example, a bipolar transistor or an IGBT transistor can be used as the power transistor. In addition, the power supply unit 20 performs the on / off high-frequency switching operation of the power transistor, but the operation is not limited to the full on / off PWM operation, and may be the on / off PWM operation including half-on. good. For example, in U.S. Pat. No. 5,982,118, a drive voltage to a coil is subjected to PWM operation based on an output signal of a position detection element. This patent discloses a motor in which a high-frequency switching operation of a field-effect power transistor is performed between an on state (full on or half on) and an off state to reduce the power loss of the power transistor and smoothly switch the drive current to the coil. Is described.

Further, in each of the above-described embodiments, only the lower power transistor is operated for high-frequency switching. However, the present invention is not limited to such a case. The high-frequency switching operation of the transistor and the upper power transistor may be alternately performed. Further, one of the three lower power transistors and the three upper power transistors is configured to perform a high-frequency switching operation simultaneously in response to a single switching pulse signal, thereby simplifying the switching operation. Let it be done. However, the present invention is not limited to such a configuration, and various modifications are possible.

Further, in each of the above embodiments, the current detecting section is simply constituted by one current detecting resistor. However, the present invention is not limited to such a case, and various current detecting methods may be used. It is possible. For example, the present invention is not limited to the case where the current obtained by combining the negative current values of the three-phase drive currents is detected, and the current obtained by combining the positive current values may be detected. further,
Make the lower power transistor and upper power transistor multiple outputs, detect the current output to one end,
The resistance for current detection may be eliminated. In addition, various modifications are possible without changing the gist of the present invention, and it goes without saying that such a configuration is also included in the present invention.

[0106]

As apparent from the detailed description of the embodiments, the present invention has the following effects. In the motor and the disk device according to the present invention, by changing the energized state in response to the terminal voltage of the coil,
It is possible to rotate a disk or a rotor in a predetermined direction with low vibration and low noise without using a position detecting element. Further, by causing the lower power transistor and the upper power transistor to perform a high-frequency switching operation of turning on / off, power loss and heat generation of the power transistor can be significantly reduced. Therefore, according to the present invention, there is an effect that a high-performance motor or disk device with low power consumption, low vibration and noise, can be realized at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram of a power supply unit 20 and a current detection unit 21 according to the first embodiment.

FIG. 3 is a circuit diagram of a voltage comparator 41 of the voltage detection unit 30 according to the first embodiment.

FIG. 4 is a circuit diagram of another configuration of the voltage comparator 41 of the voltage detection unit 30 according to the first embodiment.

FIG. 5 is a circuit diagram of a detection pulse generator 42 of the voltage detector 30 according to the first embodiment.

FIG. 6 is a circuit diagram of a timing adjuster 43 of the state transition unit 31 according to the first embodiment.

FIG. 7 is a circuit diagram of a state holder 44 of the state transition unit 31 according to the first embodiment.

FIG. 8 is a circuit diagram of a communication control unit 32 according to the first embodiment.

FIG. 9 shows a switching control unit 22 according to the first embodiment.
FIG.

FIG. 10 shows a switching control unit 2 according to the first embodiment.
FIG. 4 is a circuit diagram of a second comparison pulser 501.

FIG. 11 is a switching control unit 2 according to the first embodiment.
FIG. 10 is a circuit diagram of another configuration of the second comparison pulser 501.

FIG. 12 shows a switching control unit 2 according to the first embodiment.
2 is a circuit diagram of a second PWM pulser 502. FIG.

FIG. 13 is a waveform chart for explaining an operation of the timing adjuster 43 of the state transition unit 31 according to the first embodiment.

FIG. 14 is a diagram illustrating the state holder 44 of the state transition unit 31 and the first selection circuit 401 of the energization control unit 32 according to the first embodiment.
FIG. 9 is a waveform chart for explaining the operation of the second selection circuit 402.

FIG. 15 is a waveform chart for explaining the operation of the comparison pulser shown in FIG. 10 in the first embodiment.

FIG. 16 is a waveform chart for explaining an operation of the comparison pulser shown in FIG. 11 in the first embodiment.

FIG. 17 shows the PWM shown in FIG. 12 in the first embodiment.
FIG. 6 is a waveform diagram for explaining the operation of the pulse device.

FIG. 18 shows a switching control unit 2 according to the first embodiment.
FIG. 10 is a circuit diagram of another configuration of the second PWM pulser 502.

FIG. 19 shows the PWM shown in FIG. 19 in the first embodiment.
FIG. 6 is a waveform diagram for explaining the operation of the pulse device.

FIG. 20 is a switching control unit 2 according to the first embodiment.
FIG. 13 is a circuit diagram of still another configuration of the second PWM pulser 502.

FIG. 21 shows the PWM shown in FIG. 20 in the first embodiment.
FIG. 6 is a waveform diagram for explaining the operation of the pulse device.

FIG. 22 is a block diagram showing an overall configuration according to Embodiment 2 of the present invention.

FIG. 23 is a circuit diagram of a voltage comparator 700 according to the second embodiment.

FIG. 24 is a block diagram relating to information signals of the disk device in the embodiment.

FIG. 25 is a block diagram showing an overall configuration according to Embodiment 3 of the present invention.

FIG. 26 is a block diagram showing a configuration of a motor used in a conventional disk device.

[Explanation of symbols]

 Reference Signs List 1 disc 2 head 3 information processing unit 11 rotor 12 coil 13 coil 14 coil 20 power supply unit 21 current detection unit 22 switching control unit 25 voltage supply unit 30 voltage detection unit 31 state transition unit 32 conduction control unit 35 command unit 41 voltage comparison Unit 42 detection pulse generator 43 timing adjuster 44 state holder 700 voltage comparator 701 microcomputer unit

Claims (32)

[Claims] 1. A rotor provided with a field portion for generating a field magnetic flux, a Q-phase (Q is an integer of 3 or more) coil disposed on a stator, and two output terminals for supplying a DC voltage Voltage supply means having: Q power transistors for supplying power from the first output terminal side of the voltage supply means to one end of the coil; and a second output terminal side of the voltage supply means A power supply unit configured to include Q second power transistors for supplying power to one end of the coil from a power supply unit; a voltage detection unit configured to generate a detection pulse signal in response to a terminal voltage of the coil; State transition means for changing a holding state in response to a detection pulse signal of a voltage detection means, and energization control for controlling energization of a power transistor of the power supply means in response to a holding state of the state transition means And switching operation means for causing at least one of the Q first power transistors and the Q second power transistors of the power supply means to perform a high-frequency switching operation in response to a command signal. A motor comprising: a first energization control signal of Q phase and a second energization control signal of Q phase in response to a holding state of the state transition means; Controlling the energization state of the Q first power transistors and the Q second power transistors in response to a first energization control signal and the Q-phase second energization control signal; And a means for setting the energizing section of the first power transistor and each of the second power transistors to an electrical angle greater than 360 / Q degrees, wherein the switching operation means responds to the command signal. Means for generating a switching pulse signal, and causing at least one of the Q first power transistors and the Q second power transistors to perform a high-frequency switching operation in response to the switching pulse signal. Wherein the voltage detecting means includes a first stop time including a change time point of the high frequency switching operation of the at least one power transistor from off to on and a second stop time including a change time point from on to off. The detection operation of the detection pulse signal is stopped during at least one of the stop times, and the terminal voltage of the coil is at least turned on when the at least one power transistor is turned on except for the at least one stop time. Means for performing a detection operation of the detection pulse signal in response to Configured motor. 2. The voltage detection means stops the detection operation of the detection pulse signal during the first stop time and the second stop time, and determines the first stop time and the second stop time. 2. The motor according to claim 1, further comprising means for performing a detection operation of the detection pulse signal in response to a terminal voltage of the coil in a remaining time except for the time. 3. The voltage detecting means according to claim 1, wherein said voltage detecting means comprises a voltage comparing means for substantially comparing each terminal voltage of said Q-phase coil with a common voltage of said coil, and a noise removing signal responsive to said switching pulse signal. The output signal of the voltage comparison means is subjected to logic gate processing, and at least one of a first predetermined time including a time point when the switching pulse signal changes from off to on and a second predetermined time including a time point when the switching pulse signal changes from on to off. 3. The motor according to claim 1, further comprising: a noise removing unit that invalidates an output signal of the voltage comparing unit during one predetermined time. 4. 4. The voltage detecting means further includes a flip-flop which changes a state in response to occurrence of a rising edge or a falling edge of an output signal of the noise removing means, and which responds to a state of the flip-flop. 4. The motor according to claim 3, further comprising a pulse generating unit for generating the detected pulse signal. 5. A rotor having a field portion for generating a field magnetic flux, a Q-phase (Q is an integer of 3 or more) coil disposed on a stator, and two output terminals for supplying a DC voltage. Voltage supply means having: Q power transistors for supplying power from the first output terminal side of the voltage supply means to one end of the coil; and a second output terminal side of the voltage supply means A power supply unit configured to include Q second power transistors for supplying power to one end of the coil from a power supply unit; a voltage detection unit configured to generate a detection pulse signal in response to a terminal voltage of the coil; State transition means for changing a holding state in response to a detection pulse signal of a voltage detection means, and energization control for controlling energization of a power transistor of the power supply means in response to a holding state of the state transition means And switching operation means for causing at least one of the Q first power transistors and the Q second power transistors of the power supply means to perform a high-frequency switching operation in response to a command signal. A motor comprising: a first energization control signal of Q phase and a second energization control signal of Q phase in response to a holding state of the state transition means; In response to the first energization control signal and the Q-phase second energization control signal.
Means for controlling the energization state of the power transistor and the Q number of second power transistors so that the energization section of each of the first power transistor and each of the second power transistors is larger than 360 / Q degrees in electrical angle. The switching operation means generates a switching pulse signal in response to the command signal, and at least one of the Q first power transistors and the Q second power transistors Means for performing high-frequency switching operation of the power transistor in response to the switching pulse signal, wherein the voltage detection means substantially compares each terminal voltage of the Q-phase coil with a common voltage of the coil. The voltage comparison means, and a noise removal signal responsive to the switching pulse signal. Logic gate processing the output signal of the switching pulse signal, and at least one of a first predetermined time including a time point when the switching pulse signal changes from off to on and a second predetermined time including a time point when the switching pulse signal changes from on to off. A noise removing unit that invalidates an output signal of the voltage comparing unit in time. 6. The state transition means changes the holding state from the first state to the second state after a first adjustment time from the arrival of the detection pulse signal of the voltage detection means, and the arrival of the detection pulse signal To the second adjustment time (second adjustment time>
The motor according to any one of claims 1 to 5, further comprising means for changing the holding state from the second state to the third state after (first adjustment time). 7. The state transition means includes means for changing the first adjustment time and the second adjustment time in response to an arrival interval of a detection pulse signal of the voltage detection means. Item 7. The motor according to Item 6. 8. The means for stopping detection of the detection pulse signal during a period from the arrival of the detection pulse signal to a third adjustment time (third adjustment time> second adjustment time). 8. The motor according to claim 6, wherein the third adjustment time is changed in response to an arrival interval of the detection pulse signal. 9. 9. The switching operation means includes: a current detection means for obtaining a current detection signal in response to a current supplied from the voltage supply means to the Q-phase coil; and an output signal of the current detection means and the command signal. 9. The motor according to claim 1, further comprising: a switching control unit that compares the comparison result and generates the switching pulse signal that changes in response to the comparison result. 10. The switching operation means causes the first power transistor to perform an on / off high-frequency switching operation, and complementarily turns off / on the second power transistor in the same phase as the first power transistor. The motor according to any one of claims 1 to 9, comprising means for performing the high-frequency switching operation of (1). 11. A rotor provided with a field portion for generating a field magnetic flux, a Q-phase (Q is an integer of 3 or more) coil disposed on a stator, and two output terminals for supplying a DC voltage Voltage supply means having: Q power transistors for supplying power from the first output terminal side of the voltage supply means to one end of the coil; and a second output terminal side of the voltage supply means A power supply unit configured to include Q second power transistors for supplying power to one end of the coil from a power supply unit; a voltage detection unit configured to generate a detection pulse signal in response to a terminal voltage of the coil; State transition means for changing a holding state in response to a detection pulse signal of a voltage detection means; and an energization control for controlling energization of a power transistor of the power supply means in response to a holding state of the state transition means. Switching operation means for causing at least one of the Q first power transistors and the Q second power transistors of the power supply means to perform a high-frequency switching operation in response to a command signal; Wherein the state transition means changes the holding state from the first state to the second state after a first adjustment time from the arrival of the detection pulse signal of the voltage detection means, Means for further changing the holding state from the second state to the third state after a second adjustment time (second adjustment time> first adjustment time) from the arrival of the signal; The means generates a Q-phase first energization control signal and a Q-phase second energization control signal in response to the holding state of the state transition means, and generates the Q-phase first energization control signal and the Q-phase The second Controlling the energization state of the Q first power transistors and the Q second power transistors in response to the power control signal, and energizing each of the first power transistors and each of the second power transistors. A switching section configured to generate a current detection signal corresponding to a supply current to the Q-phase coil from the voltage supply section. And comparing the output signal of the current detecting means with the command signal to generate a switching pulse signal in response to the comparison result, and in response to the switching pulse signal, the Q first signals of the power supply means. And a switch for causing at least one of the Q second power transistors to perform a high-frequency switching operation. Motor configured to include the etching control means. 12. The state transition means includes means for changing the first adjustment time and the second adjustment time in response to an arrival interval of a detection pulse signal of the voltage detection means. Item 12. The motor according to Item 11. 13. The method according to claim 1, wherein the voltage detection unit performs a third adjustment time (third adjustment time> second adjustment time) from the arrival of the detection pulse signal.
11) means for stopping detection of the detection pulse signal until the adjustment time), and the third adjustment time is changed in response to the arrival interval of the detection pulse signal. 13. The motor according to any one of 12 above. 14. The voltage detection means according to claim 1, wherein said voltage comparison means substantially compares each terminal voltage of said Q-phase coil with a common voltage of said coil, and said noise detection signal in response to said switching pulse signal. The output signal of the voltage comparison means is subjected to logic gate processing, and at least one of a first predetermined time including a time point when the switching pulse signal changes from off to on and a second predetermined time including a time point when the switching pulse signal changes from on to off. The motor according to any one of claims 11 to 13, further comprising: noise removing means for invalidating an output signal of the voltage comparing means during one predetermined time. 15. The voltage detection means includes a first stop time including a time point when the high frequency switching operation of the at least one power transistor changes from off to on and a second stop time including a time point when the at least one power transistor changes from on to off. During at least one of the stop times, the detection operation of the detection pulse signal is stopped, and the terminal voltage of the coil is at least turned on at least when the at least one power transistor is turned on except for the at least one stop time. The motor according to any one of claims 11 to 14, further comprising means for performing a detection operation of the detection pulse signal in response to a comparison result. 16. The motor according to claim 1, wherein the motor further includes command means for generating the command signal in response to an output pulse signal of the voltage detection means.
The motor according to claim 1. 17. At least a head unit for reproducing a signal from a disk or recording a signal on a disk, and at least processing an output signal of the head unit to output a reproduction information signal, or a recording information signal. Information processing means for signal processing and outputting the signal to the head means; a rotor having a field portion for directly rotating and driving the disk to generate a field magnetic flux; and a Q-phase disposed on the stator. (Q is an integer of 3 or more) coil, voltage supply means having two output terminals for supplying a DC voltage, and power supply from the first output terminal side of the voltage supply means to one end of the coil A structure including Q first power transistors and Q second power transistors for supplying power from the second output terminal side of the voltage supply means to one end of the coil Power supply means, voltage detection means for generating a detection pulse signal in response to a terminal voltage of the coil, state transition means for transitioning a holding state in response to a detection pulse signal of the voltage detection means, the state Energization control means for controlling energization of the power transistor of the power supply means in response to the holding state of the transition means; the Q first power transistors and the Q second power transistors of the power supply means Switching operation means for performing high-frequency switching operation in response to at least one of the command signals in response to a command signal. A first energization control signal and a Q-phase second energization control signal are created, and the Q-phase first energization control signal and the Q-phase second energization control signal are generated. Correspondingly, the energization state of the Q first power transistors and the Q second power transistors is controlled, and the energization section of each of the first power transistors and each of the second power transistors is set to an electrical angle. The switching operation means generates a switching pulse signal in response to the command signal, and includes the Q first power transistors and the Q second power transistors. And a means for causing at least one of the power transistors to perform a high-frequency switching operation in response to the switching pulse signal, wherein the voltage detecting means detects a high-frequency switching operation of the at least one power transistor. A first stop time including an off-to-on transition point and an on-to-off transition point The detection operation of the detection pulse signal is stopped during at least one stop time among the second stop times including the second stop time, and the coil is turned on at least when the at least one power transistor is turned on except for the at least one stop time. A disk device including means for executing a detection operation of the detection pulse signal in response to the terminal voltage. 18. The voltage detection means stops the detection operation of the detection pulse signal during the first stop time and the second stop time, and detects the first stop time and the second stop time.
18. The disk drive according to claim 17, further comprising: means for executing a detection operation of the detection pulse signal in response to a terminal voltage of the coil during a remaining time excluding the stop time. 19. The voltage detecting means, comprising: a voltage comparing means for substantially comparing each terminal voltage of the Q-phase coil with a common voltage of the coil; and a noise removing signal in response to the switching pulse signal. The output signal of the voltage comparison means is subjected to logic gate processing, and at least one of a first predetermined time including a time point when the switching pulse signal changes from off to on and a second predetermined time including a time point when the switching pulse signal changes from on to off. 19. The disk device according to claim 17, further comprising: a noise removing unit that invalidates an output signal of the voltage comparing unit during one predetermined time. 20. The voltage detecting means further includes a flip-flop which changes a state in response to occurrence of a rising edge or a falling edge of an output signal of the noise removing means, and which responds to a state of the flip-flop. 20. The disk device according to claim 19, further comprising a pulse creating unit that creates the detected pulse signal. 21. At least a head means for reproducing a signal from the disk or recording a signal on the disk, and at least processing an output signal of the head means to output a reproduction information signal or recording. An information processing means for processing an information signal and outputting the processed signal to the head means; a rotor having a field portion for directly rotating and driving the disk to generate a field magnetic flux; and a stator provided. A coil of Q phase (Q is an integer of 3 or more); voltage supply means having two output terminals for supplying a DC voltage; and power supply from a first output terminal side of the voltage supply means to one end of the coil And Q second power transistors for supplying power from the second output terminal side of the voltage supply means to one end of the coil. Power supply means, a voltage detection means for generating a detection pulse signal in response to the terminal voltage of the coil, state transition means for transitioning a holding state in response to the detection pulse signal of the voltage detection means, Energization control means for controlling energization of a power transistor of the power supply means in response to the holding state of the state transition means; and the Q first power transistors and the Q second power transistors of the power supply means. A switching operation means for causing at least one of the power transistors to perform a high-frequency switching operation in response to a command signal, wherein the energization control means responds to a holding state of the state transition means. A first energization control signal of a phase and a second energization control signal of a Q phase are generated, and the first energization control signal of the Q phase and the second energization of the Q phase are generated. It said in response to the control signal Q number of first
Means for controlling the energization state of the power transistor and the Q number of second power transistors so that the energization section of each of the first power transistor and each of the second power transistors is larger than 360 / Q degrees in electrical angle. The switching operation means generates a switching pulse signal in response to the command signal, and at least one of the Q first power transistors and the Q second power transistors Means for performing a high-frequency switching operation in response to the switching pulse signal of the power transistor, wherein the voltage detecting means substantially compares each terminal voltage of the Q-phase coil with a common voltage of the coil. The voltage comparison means, and a noise removal signal responsive to the switching pulse signal. Logic gate processing the output signal of the switching pulse signal, and at least one of a first predetermined time including a time point when the switching pulse signal changes from off to on and a second predetermined time including a time point when the switching pulse signal changes from on to off. A noise removing unit that invalidates an output signal of the voltage comparing unit in time. 22. The state transition means changes the holding state from the first state to the second state after a first adjustment time from the arrival of the detection pulse signal of the voltage detection means, and the arrival of the detection pulse signal 18. The method according to claim 17, further comprising means for further changing the holding state from the second state to the third state after the second adjustment time (second adjustment time> first adjustment time). The disk device according to claim 21. 23. The state transition means comprising means for changing the first adjustment time and the second adjustment time in response to an arrival interval of a detection pulse signal of the voltage detection means. Item 23. The disk device according to item 22. 24. The apparatus according to claim 23, wherein the voltage detection unit sets a third adjustment time (third adjustment time> second adjustment time) from the arrival of the detection pulse signal.
23. The apparatus according to claim 22, further comprising means for stopping detection of the detection pulse signal until the adjustment time), and changing the third adjustment time in response to the arrival interval of the detection pulse signal. 24. The disk device according to any one of 23. 25. A current detecting means for obtaining a current detection signal corresponding to a current supplied from the voltage supply means to the Q-phase coil, an output signal of the current detection means and the command signal. 25. The disk device according to claim 17, further comprising: a switching control unit that compares the comparison result and generates the switching pulse signal that changes in response to the comparison result. 26. The switching operation means causes the first power transistor to perform an on / off high-frequency switching operation and complementarily turns off / on the second power transistor in the same phase as the first power transistor. The disk device according to any one of claims 17 to 25, comprising means for performing the high-frequency switching operation of (1). 27. At least a head means for reproducing a signal from the disk or recording a signal on the disk, and at least processing an output signal of the head means to output a reproduction information signal or recording. An information processing means for processing an information signal and outputting the processed signal to the head means; a rotor having a field portion for directly rotating and driving the disk to generate a field magnetic flux; and a stator provided. A coil of Q phase (Q is an integer of 3 or more); voltage supply means having two output terminals for supplying a DC voltage; and power supply from a first output terminal side of the voltage supply means to one end of the coil And Q second power transistors for supplying power from the second output terminal side of the voltage supply means to one end of the coil. Power supply means, a voltage detection means for generating a detection pulse signal in response to the terminal voltage of the coil, state transition means for transitioning a holding state in response to the detection pulse signal of the voltage detection means, Energization control means for controlling energization of a power transistor of the power supply means in response to the holding state of the state transition means; and the Q first power transistors and the Q second power transistors of the power supply means. A switching operation means for causing at least one of the power transistors to perform a high-frequency switching operation in response to a command signal, wherein the state transition means receives a detection pulse signal from the voltage detection means. After the first adjustment time, the holding state is changed from the first state to the second state, and the arrival time of the detection pulse signal is changed to a second adjustment time. A second adjustment time> a first adjustment time), a unit for further changing the holding state from the second state to the third state after the first adjustment time, and the energization control unit includes a holding state of the state transition unit. And generating a Q-phase first energization control signal and a Q-phase second energization control signal corresponding to the Q-phase first energization control signal and the Q-phase second energization control signal. Controlling the energization state of the Q first power transistors and the Q second power transistors, and energizing sections of the first power transistors and the second power transistors in 360 electrical degrees. The switching operation means includes a current detection means for obtaining a current detection signal in response to a current supplied from the voltage supply means to the Q-phase coil, and the current detection means. Output signal And the command signal, and generates a switching pulse signal in response to the comparison result. In response to the switching pulse signal, the Q first power transistors and the Q number A disk device comprising switching control means for causing at least one of the two power transistors to perform a high-frequency switching operation. 28. The state transition means comprising means for changing the first adjustment time and the second adjustment time in response to an arrival interval of a detection pulse signal of the voltage detection means. Item 28. The disk device according to Item 27. 29. The method according to claim 29, wherein the voltage detection unit sets a third adjustment time (third adjustment time> second adjustment time) from the arrival of the detection pulse signal.
28. The apparatus according to claim 27, further comprising means for stopping detection of the detection pulse signal until the detection pulse signal arrives, and changing the third adjustment time in response to the arrival interval of the detection pulse signal. 29. The disk device according to any one of items 28. 30. The voltage detecting means, comprising: a voltage comparing means for substantially comparing each terminal voltage of the Q-phase coil with a common voltage of the coil; and a noise removing signal in response to the switching pulse signal. The output signal of the voltage comparison means is subjected to logic gate processing, and at least one of a first predetermined time including a time point when the switching pulse signal changes from off to on and a second predetermined time including a time point when the switching pulse signal changes from on to off. 30. The disk device according to claim 27, further comprising: a noise removing unit that invalidates an output signal of the voltage comparing unit during one predetermined time. 31. The voltage detecting means includes a first stop time including a time point when the high frequency switching operation of the at least one power transistor changes from off to on and a second stop time including a time point when the high frequency switching operation changes from on to off. During at least one of the stop times, the detection operation of the detection pulse signal is stopped, and the terminal voltage of the coil is at least turned on at least when the at least one power transistor is turned on except for the at least one stop time. 31. The disk device according to claim 27, further comprising means for executing a detection operation of the detection pulse signal in response to the comparison result. 32. The disk device according to claim 17, further comprising command means for generating the command signal in response to an output pulse signal of the voltage detection means. The disk device according to item 1.