JP2001230670A - PLL oscillation circuit - Google Patents

Abstract

[PROBLEMS] To provide a PLL oscillation circuit having a wide band and high stability. A two different control voltage - using a voltage controlled oscillator 1A having an oscillation frequency characteristic, a phase comparator 2A for generating a lock detecting signal L _OCK the state where the phase synchronization is applied, this loop filter 3 and variable frequency divider 4,
Constitute a PLL oscillation circuit combines the reference signal oscillator 5, the first and second switching circuits 7 and 8 which is switching control by the presence or absence of the lock detection signal L _OCK, when the transient state in which the frequency is changed In addition, the change of the oscillation frequency with respect to the control voltage of the voltage controlled oscillator 1A is increased, and after the phase synchronization is applied, the change of the oscillation frequency with respect to the control voltage of the oscillator 1A is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL type oscillating circuit used for a carrier frequency signal source or a local oscillation frequency source of a radio device, and more particularly to a case where a wider oscillation frequency is required. The present invention relates to a PLL oscillation circuit.

[0002]

2. Description of the Related Art A PLL oscillation circuit is also called a PLL frequency synthesizer, and includes a variable frequency divider (programmable counter), a phase comparator, and a loop filter.
By using L (phase locked loop) and synchronizing the voltage controlled oscillator (VCO) with the reference oscillator,
A circuit for generating a highly stable variable frequency signal, which has been widely used in recent years as a carrier frequency signal source or a local oscillation frequency signal source of a radio device.

FIG. 6 shows an example of a PLL oscillation circuit according to the prior art, which uses a voltage-controlled oscillator 1, a phase comparator 2, a loop filter 3, a variable frequency divider 4, and a reference signal oscillating section 5 as shown in FIG. The signal of the frequency F output from the voltage controlled oscillator 1 is input to the variable frequency divider 4 to divide the frequency by N, and this is supplied to the comparison input of the phase comparator 2, and the reference input of the signal is supplied to the reference input of the phase comparator 2. It is configured to supply a reference signal having a frequency f ₀ output from the unit 5, where:
N is one or more arbitrary integers.

As a result, the output of the phase comparator 2 includes:
A reference signal of a frequency f _0, which is supplied from the reference signal oscillator 5, a variable frequency signal of the voltage value V _D appearing corresponding to the phase difference between the divider 4 dividing the frequency f / N of the signal, which is It will be supplied as the control voltage V _C to the control voltage input of the voltage controlled oscillator 1 via the loop filter 3.

Accordingly, a phase-locked loop system is formed by the reference signal oscillating section 5, the phase comparator 2, the loop filter 3, the voltage controlled oscillator 1, and the variable frequency divider 4. At this time, the frequency division of the variable frequency divider 4 is performed. The ratio N is controlled by frequency division data supplied from the control processing unit 12, and as a result, by setting the frequency division ratio N arbitrarily, the output terminal 6
Will output a signal of the desired frequency F.

The operation of the conventional PLL oscillation circuit shown in FIG. 6 will be described in further detail. In the phase comparator 2, the phase of the reference signal having the frequency f ₀ and the frequency divided by the variable frequency divider 4 are obtained. compared the phase of the signal of the frequency F / N, the phase error signal of a voltage value V _D is outputted as the comparison result. Then, this phase error signal is output to the loop filter 3
Is applied to the control voltage input of the voltage-controlled oscillator 1 as the control voltage V _C to control the oscillation frequency of the oscillator 1.

Therefore, the voltage controlled oscillator 1 is controlled so that the phase of the signal of frequency F / N output from the variable frequency divider 4 is locked to the signal of frequency f ₀ output from the reference signal oscillating unit 5. A loop operation for controlling the oscillation frequency F works. As a result, a signal having a frequency stability equal to the frequency stability of the reference signal oscillating unit 5 is generated by the voltage controlled oscillator 1.
It will be obtained from.

[0008] Therefore, the frequency stability is higher oscillator as a reference signal oscillator 5, for example, in terms of using a crystal oscillator, so that the variable range of the oscillation frequency with respect to the control voltage V _C of the voltage controlled oscillator 1 in the range that requires If the voltage controlled oscillator 1 is designed and the frequency division ratio N of the variable frequency divider 4 is changed, a high stability signal of a frequency F determined by the relationship of F = N · f ₀ can be obtained from the output terminal 6. Will be.

Here, a control voltage-oscillation frequency characteristic of the voltage controlled oscillator 1 is called a conversion gain, which is set so as to cover a required oscillation frequency variable width. The frequency division ratio N by the variable frequency divider 4 at this time is determined by the control processing unit 1
2, it can be set arbitrarily over a predetermined range.

Therefore, the numerical value N corresponding to the required output frequency
By setting the frequency-divided data in the variable frequency divider 4, the frequency of the output signal can be arbitrarily selected according to the frequency command, and can be used as a highly stable variable frequency signal source.

[0011]

In the above prior art, no consideration is given to a decrease in stability due to noise (noise) mixed into the control voltage input of the voltage controlled oscillator, and there is a problem in widening the oscillation frequency. Was. That is, in the above-described conventional technology, if noise is mixed in the control voltage input of the voltage-controlled oscillator, the frequency or phase of the oscillator is modulated, and the oscillation frequency fluctuates, thereby lowering stability. This decrease in stability is more pronounced as the required frequency variable width is wider, that is, as the band is widened, so that a problem arises in widening the band.

This point will be described with reference to the prior art in FIG. 6. A block diagram of the phase locked loop in this case is as shown in FIG.
_Is the conversion gain of K _Φ and the transfer function of the loop filter 3 is F
(S), the conversion gain of the voltage controlled oscillator 1 is K _V , the frequency division number of the variable frequency divider 4 is N, and the output phase of the output terminal 6 is θ.
₀ (S), assuming that the phase fluctuation due to the noise is disturbance D (S), the loop transfer characteristic of the output phase θ ₀ (S) with respect to the disturbance D (S) can be expressed by the following equation (1).

Θ ₀ (S) / D (S) = K _V / {1+ ( _KΦ · K _V / N) · F (S)} (1) From this equation (1), the disturbance D (S In order to reduce the influence of (), the equation {(K _Φ ·
K _V / N) · F (S)} or the conversion gain of the molecule K _V
It can be seen that (forward transmission gain) needs to be reduced.
Especially in the case of the disturbance D (S) due to noise including the loop tracking frequency range outside of the component, by open-loop transfer gain becomes extremely small, in a state that _{1» (K Φ · K V /} N) · F (S) However, in this case, since θ ₀ (S) ≒ K _V · D (S), it is necessary to reduce the conversion gain K _V in the numerator on the right side in order to reduce the influence of disturbance.

[0014] On the other hand, the variable width of the oscillation frequency by a voltage controlled oscillator, that is, the variable range of the output frequency of the PLL oscillation circuit is determined by conversion gain K _V, for broadband, it is necessary to increase the conversion gain K _V .

This is because, in the case of the prior art, the expansion of the frequency variable width and the suppression of the decrease in stability due to disturbance are in a trade-off relationship, and when the variable width of the oscillation frequency is required to be wide. Means that it becomes difficult to suppress a decrease in stability due to frequency fluctuations due to disturbance. Therefore, in the related art, there is a problem in achieving both broadband and high stability.

It is an object of the present invention to provide a broadband and high stability PL.
An L oscillation circuit is provided.

[0017]

SUMMARY OF THE INVENTION An object of the present invention is to divide the output of a voltage controlled oscillator by N using a variable frequency divider, compare the frequency of the divided signal with a reference frequency signal, and determine the phase difference between these signals. Controlling the oscillation frequency of the voltage-controlled oscillator according to the above, so that a signal having a frequency N times higher than the reference frequency signal is output from the voltage-controlled oscillator.
In the L oscillation circuit, in an unlocked state where a phase difference remains between the signals, a change amount of the oscillation frequency with respect to a control voltage of the voltage controlled oscillator is increased, and in a locked state where there is no phase difference between the signals. , And the amount of change is reduced.

At this time, the time constant of a loop filter in a phase locked loop for controlling the oscillation frequency of the voltage controlled oscillator according to the phase difference between the signals is switched between the unlocked state and the locked state, The above object can be achieved even when the cutoff frequency of the loop and the damping factor are kept substantially constant.

At this time, the amount of change in the unlocked state is set to a magnitude that covers a change width of the oscillation frequency required for the voltage controlled oscillator, and the amount of change in the locked state is The above object can be achieved even if the magnitude is set so as to cover the variation width of the oscillation frequency due to the drift of the voltage controlled oscillator.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PLL oscillation circuit according to the present invention will be described in detail with reference to the illustrated embodiments.
FIG. 1 shows an embodiment of the present invention, in which 1A is a voltage controlled oscillator, 2A is a phase comparator, 7 is a first switch circuit, 8 is a second switch circuit, and 9 is an A / D converter. Reference numeral 10 denotes a D / A converter, and reference numeral 11 denotes a voltage source. The other components are the same as those in the conventional technique described with reference to FIG.

The voltage-controlled oscillator 1A has two control input terminals X and Y so that the oscillation frequency F can be controlled in accordance with the control voltage input thereto. For example, as shown in FIG. An oscillator 1A1 composed of an active element such as a transistor is combined with a resonance circuit 1A2 having two variable capacitance diodes D1 and D2 and an inductance element L as a resonance circuit for determining an oscillation frequency. .

Here, each variable capacitance diode D1, D2
Is connected to the inductance element L via the capacitors C1 and C2 in parallel with the anode grounded, thereby forming an LC resonance circuit and determining the oscillation frequency F of the voltage controlled oscillator 1A. Has become.

The variable capacitance diodes D1,
The cathode of D2 further includes a coil CH1 for blocking high frequency,
The terminals X and Y are connected to the terminals X and Y via CH2, and DC control voltages V _C1 and V _C2 are applied from these terminals X and Y. Therefore, the oscillation frequency F of the voltage controlled oscillator 1 Control voltage V _C1 supplied to terminals X and Y of
It will be controlled by V _C2 . Here, the inductance element L has an adjustable inductance value.
It is composed of a so-called semi-fixed inductance type coil or the like.

On the other hand, the capacitors C1 and C2 are used to prevent the control voltages V _C1 and V _C2 from being short-circuited by the inductance element L and to determine the resonance frequency and the conversion gain. The resonance frequency F of the circuit depends on the inductance value of the inductance element L, the variable capacitance diodes D1, D2 and the capacitor C.
1, it is determined by the capacitance value of C2.

The phase comparator 2A compares the phase of the reference signal of the frequency f ₀ supplied from the reference signal oscillating section 5 with the phase of the signal of the frequency F / N divided by the variable frequency divider 4. comparison point for outputting a phase error signal of the voltage value V _D as is the same as the phase comparator 2 in the prior art of FIG. 6, further this time, the phase locked loop is unlocked (phase synchronization the comparison result Is locked)
(The state where phase synchronization is applied)
It is intended to serve to the control processor 12 generates a lock detection signal L _OCK.

The first switch circuit 7 and the second switch circuit 8 control the control signal S supplied from the control processing unit 12, respectively.
1, the control voltages V _C1 and V _C2 applied to the terminals X and Y of the voltage controlled oscillator 1A are controlled by the output of the loop filter 3 and the D / A converter 10 as shown in FIG.
, And the output of the voltage source 11.

The A / D converter 9 performs a conversion process required for the control processing unit 12 to take in the output of the loop filter 3, and the D / A converter 10 converts the output of the control processing unit 12 to a control voltage V _C1. Performs conversion processing necessary for use. At this time, the control processing unit 12 sets the loop filter 3
The timing for taking in the output of is described later.

The voltage source 11 has a function of generating a voltage E having a predetermined constant value. The voltage E from the voltage source 11 is, as will be described later, unlocked by a phase locked loop. In the locked state, it is used as the control voltage V _C2 .

Next, the operation of the embodiment of FIG. 1 will be described. First, the operation of the voltage controlled oscillator 1A will be described with reference to FIG.
A represents the conversion gain of A, where the characteristic KV _C1 is the conversion gain by the first control voltage V _C1 applied to the terminal X, and the characteristic KV _C2 is the second control voltage V _C applied to the terminal Y. _This is the conversion gain due to _C2 .

First, the first control voltage V _C1 and the second control voltage V _C2 change between the lower limit voltage V _L and the upper limit voltage V _H of the output voltage dynamic range ΔV of the phase comparator 2 at this time. oscillation frequency at the lower limit voltage V _L is F _L
Therefore, the oscillation frequency at the upper limit voltage V _H is F _H , so that the oscillation frequency _FL is the lower limit frequency of the required oscillation frequency variable range, and the oscillation frequency F _H is also the upper limit frequency.

Next, the frequency F _{0 on the} vertical axis is the value of the oscillation frequency F determined by the frequency division ratio N set by the control processing unit 12 at this time, and the voltage V _{01 on the} horizontal axis is the first voltage at this time. It represents the value of the control voltage V _C1, the voltage V _02, like represents the value of the second control voltage V _C2 at this time.

The control voltages V _C1 and V _{C2 at} this time are
The conversion gains KV _C1 and KV _C2 are selected as variable capacitance diodes D1 and D2, respectively, and the capacitance values of capacitors C1 and C2 connected in series to these variable capacitance diodes are selected. Can be set to any conversion gains by selecting and adjusting.

[0033] Therefore, the first conversion gain KV _C1 to the first control voltage V _C1, is set to a size required to cover a variable range required for the oscillation frequency F. next,
Conversion gain KV _C2 to the second control voltage V _C2 is a state in which oscillates at any frequency, so as to cover the oscillation frequency variation width due to variations in the various operating conditions such as temperature changes in the voltage controlled oscillator 1A Set.

Therefore, in general, KV _C1 ≫KV _C2 . Therefore, a variable capacitance diode D1 having a large change in capacitance with respect to the reverse voltage is selected.
As the variable capacitance diode D2, a diode having a small change in capacitance with respect to the reverse voltage is selected.

As will be described later, the first control voltage V _C1 is set to the lower limit voltage V _L according to the required oscillation frequency F.
To the upper limit voltage V _H , while the second control voltage V _C2 is substantially maintained at the voltage V ₀₂ in the steady state regardless of the required oscillation frequency.

Here, the variation width ΔF of the oscillation frequency due to the first control voltage V _C1 is F _H −F _L , and the conversion gain KV _C1 = ΔF / ΔV in this case, whereas the second control The variation width Δf of the oscillation output frequency due to the voltage V _C2 is f _H −
f _L , so that the conversion gain KV _C2 = Δf / ΔV.

Therefore, for example, in a 400 MHz band broadband radio, if the required oscillation frequency variable width is 20 MHz, the phase error output voltage range of the phase comparator 2 is 5 V, and the frequency fluctuation of the voltage controlled oscillator 1A is 0.5%, Conversion gain K
V _C1 is about 4 MHz / V, and conversion gain KV _C2 is about 0.4 M
Hz / V.

Next, the operation of the entire PLL oscillation circuit shown in FIG. 1 will be described with reference to the timing chart of FIG. As shown in FIG. 1, the output of the voltage controlled oscillator 1A is connected to the output terminal 6 and the variable frequency divider 4, and the output of the variable frequency divider 4 is connected to the comparison input of the phase comparator 2A. The output of the reference signal oscillating unit 5 is connected to the reference input of the phase comparator 2A, and the phase error output of the comparator 2 is connected to the input of the loop filter 3.

Therefore, also in this embodiment, a phase locked loop is formed by the reference signal oscillating unit 5, the phase comparator 2A, the loop filter 3, the voltage controlled oscillator 1A, and the variable frequency divider 4, and the phase comparator 2A The phase of the reference signal of the reference signal oscillating unit 5 is compared with the phase of the output signal of the voltage controlled oscillator 1A divided by the variable frequency divider 4, and a phase error signal is output as a comparison result. 3 operates in such a manner that the oscillation frequency of the oscillator 1A is controlled by being applied to the control voltage input of the voltage-controlled oscillator 1A via the control circuit 3 as in the prior art.

[0040] Thus, in the embodiment of FIG. 1, when the phase-locked loop becomes from the unlocked state to the locked state, the phase comparator 2A generates a lock detection signal L _OCK,
The first switch circuit 7 and the second switch circuit 8 are input to the control processing unit 12, thereby controlling the first switch circuit 7 and the second switch circuit 8. As a result, the operation described below is executed at the start of operation or every time the frequency command is updated. Is different from the prior art.

[0041] First, in the unlocked state, the first switch circuit 7 and the second switch circuit 8 takes the switching position of each illustrated, when the lock detection signal L _OCK in the locked state is supplied, and shown Are controlled to assume opposite switching positions.

Therefore, in the unlocked state, the output voltage V _C of the loop filter 3 is supplied to the X terminal of the voltage controlled oscillator 1A as the first control voltage V _C1 , and the Y terminal is
The voltage E from the voltage source 11 is supplied as the second control voltage V _C2 , but in the locked state, the D / A converter 10
Is supplied to the X terminal of the voltage controlled oscillator 1A as the first control voltage V _C1 , and the output voltage V _C of the loop filter 3 is supplied to the Y terminal as the second control voltage V _C2. Become.

[0043] Therefore, now, the frequency command for the time t ₀ before the operation at a given time is started or the control processor 12 of FIG. 3 is updated as a result of the new frequency dividing ratio N is set, the time t ₀ In the unlocked state, the phase-locked loop is controlled by the second control voltage V
_{While C2} is fixed at the voltage E, only the first control voltage V _C1 of the voltage controlled oscillator 1A is controlled, and the oscillation frequency of the oscillator 1A is controlled so as to converge to the locked state.

At this time, the voltage E set to the voltage source 11
Is, for example, a voltage near the center of the output voltage dynamic range ΔV of the phase comparator 2A, that is, E ≒ V _L + (V _H −
_VL ) / 2. Therefore, at this time, as is apparent from FIG. 2, the control by the phase locked loop operates under a large conversion gain KV _{C1, and as} a result, the oscillation frequency F can be changed over a wide oscillation frequency variable range ΔF. It is possible to easily cope with a wider band.

Next, the operation of the phase locked loop in such a time after t _0, when the phase has become locked state at time t _1, wherein the lock detection signal L _OCK is generated from the phase comparator 2A Are supplied to the control processing unit 12.

The control processing section 12 outputs the lock detection signal L
At this time, in response to the input of _OCK , the output voltage V _C of the loop filter 3 is captured and stored via the A / D converter 9, and then output via the D / A converter 10 and the control signal S 1. , S2 to control the respective switch circuits 7, 8 to switch positions opposite to those shown in the figure.

As a result, after the time t ₁ , the phase locked loop operates in a state where the first control voltage V _C1 of the voltage controlled oscillator 1 A is fixed to the output voltage of the D / A converter 10.
This time, the second control voltage V _C2 of the voltage controlled oscillator 1A is controlled, and the oscillation frequency of the oscillator 1A is controlled so as to converge to the locked state.

[0048] Now, the oscillation frequency F newly set this time, assuming that a frequency F ₀ of FIG. 2, at time t ₁ in which the phase has become locked, A loop filter 3
The output voltage V _C taken through the / D converter 9 is
A voltage V ₀₁ as shown, which is after time t ₁ as a fixed voltage, the D / A converter 10 to the voltage controlled oscillator 1A, will be supplied as a first control voltage V _C1.

[0049] according to the result, the oscillation frequency F of the voltage controlled oscillator 1A, even prima facie after time t ₁ is held to a frequency F ₀ which is commanded, the phase locked loop under the control of the second control voltage V _C2 in this state Since the control works, at time t
_{From 1} onward, the oscillation frequency stabilizing operation by the phase locked loop works under the small conversion gain KV _C2 around the oscillation frequency F _0, and as a result, the fluctuation of the oscillation frequency due to disturbance is sufficiently suppressed. be able to.

More specifically, as described above, for example, in the 400 MHz band, the required oscillation frequency
MHz, the phase error output voltage range ΔV of the phase comparator 2 is 5
Assuming that the frequency fluctuation due to the drift of the V and voltage controlled oscillator 1A is 0.5%, the conversion gain KV _C1 ≒ 4
At MHz / V, the conversion gain KV _C2 ≒ 0.4 MHz / V.

In this case, in the steady state, that is, in the locked state, the conversion gain is set to about 1/10 of that in the transient state, that is, in the unlocked state. As a result, the influence of the disturbance is also reduced to about 1 /. It will be suppressed to 10. Therefore, according to this embodiment, even if the variation width of the oscillation frequency is widened, there is no possibility that the stability is reduced due to disturbance.
It is possible to easily achieve compatibility between a wide band and high stability.

Next, FIG. 5 shows another embodiment of the present invention.
The difference from the embodiment of FIG. 1 is that a loop filter 3A capable of switching the time constant is provided instead of the loop filter 3 in the embodiment of FIG. The point is that the transfer characteristic of the loop filter 3A can be switched between the locked state and the locked state.

In the case of the embodiment of the present invention in which the conversion gain is switched by using the voltage controlled oscillator 1A, the loop gain of the phase locked loop changes with the switching of the conversion gain.
As a result, the loop cutoff angular frequency ω that determines the loop characteristics
n and the damping factor ζ also change.

In the embodiment of FIG. 5, the time constant is switched between the transient state and the steady state by using the loop filter 3A whose transfer characteristic is switched. Thus, the influence of the change in the loop characteristics can be avoided.

[0055]

According to the present invention, since the conversion gain of the voltage controlled oscillator is switched between the transient state and the steady state, it is possible to achieve both expansion of the frequency variable width and suppression of the decrease in stability due to disturbance. Therefore, a PLL oscillation circuit having a wide band and high stability can be easily provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL oscillation circuit according to the present invention.

FIG. 2 is a control voltage-oscillation frequency characteristic diagram of a voltage controlled oscillator according to an embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the embodiment of the present invention;

FIG. 4 is a circuit diagram of a voltage controlled oscillator according to an embodiment of the present invention.

FIG. 5 is a block diagram showing another embodiment of the PLL oscillation circuit according to the present invention.

FIG. 6 is a block diagram showing an example of a conventional PLL oscillation circuit.

FIG. 7 is a block diagram for explaining the influence of disturbance on a phase locked loop.

[Explanation of symbols]

 Reference Signs List 1A voltage controlled oscillator 2A phase comparator 3 loop filter 4 variable frequency divider 5 reference signal oscillating unit 6 output terminal 7 first switch circuit 8 second switch circuit 9 A / D converter 10 D / A converter 11 voltage source 12 Control processor 1A1 Oscillator 1A2 Resonator

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H03L 7/107 H03L 7/10 EF term (Reference) 5J081 AA02 BB01 BB10 CC06 CC07 DD02 EE02 EE03 EE18 FF02 FF06 FF08 FF12 FF24 FF25 KK02 KK09 KK22 MM01 5J106 AA04 BB01 CC15 CC21 CC41 CC53 DD09 DD35 DD36 EE10 EE18 GG01 GG07 GG09 GG20 HH01 HH10 JJ01 KK03 KK08 KK12 KK25 KK27 LL01 PP03 QQ07 QQ09 RR08

Claims (4)

[Claims] An output of a voltage controlled oscillator is frequency-divided by a variable frequency divider by N, a phase of a frequency-divided signal is compared with a reference frequency signal, and an oscillation frequency of the voltage controlled oscillator is determined according to a phase difference between these signals. In the PLL oscillation circuit in which a signal having a frequency N times higher than the reference frequency signal is output from the voltage controlled oscillator, in an unlocked state in which a phase difference remains between the signals,
In the lock state where the amount of change in the oscillation frequency with respect to the control voltage of the voltage controlled oscillator is increased, and there is no phase difference between the signals,
A PLL oscillation circuit characterized in that the amount of change is reduced. 2. The invention according to claim 1, wherein a time constant of a loop filter in a phase locked loop for controlling an oscillation frequency of the voltage controlled oscillator according to a phase difference between the signals is set to the unlocked state. A PLL oscillation circuit which is switched in a locked state, and wherein a cutoff angular frequency and a damping factor of the phase locked loop are kept substantially constant. 3. The invention according to claim 1, wherein the amount of change in the unlocked state covers a change width of an oscillation frequency required for the voltage controlled oscillator. Wherein the amount of change in the locked state is set to a magnitude that covers a range of change in oscillation frequency due to drift of the voltage controlled oscillator. 4. A resonance section to which a first control input terminal, a second control voltage input terminal, the first and second control voltage input terminals are connected, and a resonance frequency corresponding to the resonance frequency of the resonance section. A voltage controlled oscillator comprising: an oscillating unit that outputs an oscillating frequency signal; and an output terminal of the oscillating unit, wherein a first conversion gain between the first control voltage input terminal and the output terminal; A voltage controlled oscillator characterized in that a second conversion gain between a control voltage input terminal and an output terminal is different.