JP2001230549A - Method for manufacturing multil ayer printed wiring board circuit board - Google Patents
Method for manufacturing multil ayer printed wiring board circuit boardInfo
- Publication number
- JP2001230549A JP2001230549A JP2000018171A JP2000018171A JP2001230549A JP 2001230549 A JP2001230549 A JP 2001230549A JP 2000018171 A JP2000018171 A JP 2000018171A JP 2000018171 A JP2000018171 A JP 2000018171A JP 2001230549 A JP2001230549 A JP 2001230549A
- Authority
- JP
- Japan
- Prior art keywords
- base material
- copper foil
- insulating base
- conductive paste
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 80
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 77
- 239000011889 copper foil Substances 0.000 claims abstract description 73
- 229920005989 resin Polymers 0.000 claims abstract description 47
- 239000011347 resin Substances 0.000 claims abstract description 47
- 239000004020 conductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000011049 filling Methods 0.000 claims abstract description 25
- 230000008569 process Effects 0.000 claims abstract description 11
- 239000012790 adhesive layer Substances 0.000 claims description 28
- 238000003825 pressing Methods 0.000 claims description 7
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 19
- 239000000853 adhesive Substances 0.000 abstract description 12
- 230000001070 adhesive effect Effects 0.000 abstract description 12
- 239000011229 interlayer Substances 0.000 abstract description 7
- 238000009413 insulation Methods 0.000 abstract 4
- 229920002799 BoPET Polymers 0.000 description 14
- 239000011162 core material Substances 0.000 description 11
- 239000003822 epoxy resin Substances 0.000 description 11
- 239000011521 glass Substances 0.000 description 11
- 229920000647 polyepoxide Polymers 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 10
- 239000004744 fabric Substances 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 9
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 8
- 238000007639 printing Methods 0.000 description 8
- 239000000243 solution Substances 0.000 description 7
- 239000007864 aqueous solution Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000002923 metal particle Substances 0.000 description 6
- 238000007731 hot pressing Methods 0.000 description 5
- 238000010030 laminating Methods 0.000 description 5
- 229910002092 carbon dioxide Inorganic materials 0.000 description 4
- 239000001569 carbon dioxide Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- -1 polyethylene terephthalate Polymers 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- AEMRFAOFKBGASW-UHFFFAOYSA-N Glycolic acid Chemical compound OCC(O)=O AEMRFAOFKBGASW-UHFFFAOYSA-N 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004734 Polyphenylene sulfide Substances 0.000 description 2
- WCUXLLCKKVVCTQ-UHFFFAOYSA-M Potassium chloride Chemical compound [Cl-].[K+] WCUXLLCKKVVCTQ-UHFFFAOYSA-M 0.000 description 2
- KAESVJOAVNADME-UHFFFAOYSA-N Pyrrole Chemical compound C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 2
- 239000004760 aramid Substances 0.000 description 2
- 229920003235 aromatic polyamide Polymers 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 238000007872 degassing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 150000007524 organic acids Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- JRKICGRDRMAZLK-UHFFFAOYSA-L peroxydisulfate Chemical compound [O-]S(=O)(=O)OOS([O-])(=O)=O JRKICGRDRMAZLK-UHFFFAOYSA-L 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920000069 polyphenylene sulfide Polymers 0.000 description 2
- 239000012286 potassium permanganate Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- JUWOETZNAMLKMG-UHFFFAOYSA-N [P].[Ni].[Cu] Chemical compound [P].[Ni].[Cu] JUWOETZNAMLKMG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000005273 aeration Methods 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 150000003851 azoles Chemical class 0.000 description 1
- 230000005587 bubbling Effects 0.000 description 1
- 239000002738 chelating agent Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- VFFQCUJVGMRYIF-UHFFFAOYSA-N copper;1h-imidazole Chemical compound [Cu+2].C1=CNC=N1 VFFQCUJVGMRYIF-UHFFFAOYSA-N 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 235000011164 potassium chloride Nutrition 0.000 description 1
- 239000001103 potassium chloride Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層プリント配線
板の製造に供される両面回路基板および片面回路基板の
製造方法についての提案である。The present invention relates to a method for manufacturing a double-sided circuit board and a single-sided circuit board for use in manufacturing a multilayer printed wiring board.
【０００２】[0002]
【従来の技術】最近の電子機器の小型・軽量・高速・高
機能化の要求に応じて、従来のスルーホール構造の多層
プリント配線板に代えて、高密度配線化に対応し易いイ
ンターステシャルビアホール構造（以下、ＩＶＨ構造と
略記する）を有する多層プリント配線板が提案されてい
る。2. Description of the Related Art In response to recent demands for smaller, lighter, faster, and more sophisticated electronic devices, an interstitial that can easily cope with high-density wiring is used instead of a conventional multilayer printed wiring board having a through-hole structure. A multilayer printed wiring board having a via hole structure (hereinafter abbreviated as an IVH structure) has been proposed.
【０００３】このＩＶＨ構造を有する多層プリント配線
板というのは、積層体を構成する各層間絶縁層に、導体
回路間を電気的に接続するビアホールが設けられている
構造のプリント配線板である。このようなプリント配線
板は、内層導体回路パターン相互間あるいは内層導体回
路パターンと外層導体回路パターン間が、配線基板を貫
通しないビアホール（べリードビアホールあるいはブラ
インドビアホール）によって電気的に接続されているこ
とが特徴である。それ故に、かかるＩＶＨ構造の多層プ
リント配線板は、スルーホールを形成するための領域を
特別に設ける必要がなく、各層間接続を微細なビアホー
ルだけで行うことができるため、電子機器の小型化、高
密度化、信号の高速伝搬を容易に実現することができる
ものと期待されている。[0003] The multilayer printed wiring board having the IVH structure is a printed wiring board having a structure in which via holes for electrically connecting conductor circuits are provided in each interlayer insulating layer constituting a laminate. In such a printed wiring board, the inner-layer conductor circuit patterns or the inner-layer conductor circuit patterns and the outer-layer conductor circuit patterns are electrically connected by via holes (solid via holes or blind via holes) that do not penetrate the wiring board. Is the feature. Therefore, in the multilayer printed wiring board having such an IVH structure, it is not necessary to provide a special region for forming a through hole, and each interlayer connection can be made only by a fine via hole. It is expected that high density and high-speed signal propagation can be easily realized.
【０００４】しかしながら、上記ＩＶＨ構造の多層プリ
ント配線板はその製造工程において、絶縁性樹脂基材と
して、ガラス布にエポキシ樹脂を含浸させたガラスエポ
キシプリプレグのような未硬化樹脂を採用していること
に起因する問題点があった。すなわち、プリプレグ上に
銅箔を熱プレスによって接着し、それをエッチングして
導体回路を形成した回路基板の複数枚を接着剤を介して
積層し、その後、積層された回路基板を一括して熱プレ
スすることによって多層化する際、硬化した樹脂が収縮
するために、ビアホールの位置がＸＹ方向にずれるとい
う現象が見られた。このような位置ずれに対処するに
は、ビアランド径を予め大きくしておく必要があるた
め、精密配線が困難であった。However, in the manufacturing process of the multilayer printed wiring board having the IVH structure, an uncured resin such as a glass epoxy prepreg obtained by impregnating a glass cloth with an epoxy resin is used as an insulating resin base material. There was a problem caused by. That is, a copper foil is bonded on a prepreg by a hot press, and a plurality of circuit boards on which a conductive circuit is formed by etching the copper foil are laminated via an adhesive, and then the laminated circuit boards are collectively heated. When a multilayer is formed by pressing, a phenomenon in which the position of the via hole shifts in the XY directions due to shrinkage of the cured resin was observed. In order to cope with such a displacement, it is necessary to increase the diameter of the via land in advance, so that precise wiring is difficult.
【０００５】なお、このような問題点については、本願
の発明者らは先に、特願平第１０-１７９１９２号とし
てその改善方法を提案した。このような改善提案は、従
来のような未硬化樹脂からなる絶縁性基材ではなく、硬
化した樹脂からなる樹脂基材をコア材とし、このコア材
の片面または両面に導体回路を形成して、その導体回路
間を充填ビアホールで接続した片面回路基板または両面
回路基板についての提案であり、これらの複数枚を適宜
組み合わせて積層し、一括加熱プレスすることによって
多層プリント配線板を製造する技術である。Regarding such problems, the inventors of the present application have previously proposed a method for improving such a problem as Japanese Patent Application No. 10-179192. Such an improvement proposal is to use a resin base material made of a cured resin as a core material, instead of an insulating base material made of an uncured resin as in the past, and to form a conductor circuit on one or both surfaces of the core material. This is a proposal for a single-sided circuit board or a double-sided circuit board in which the conductor circuits are connected by filling via holes, and a technique for manufacturing a multilayer printed wiring board by appropriately combining and laminating a plurality of these boards and performing batch heating press. is there.
【０００６】[0006]
【発明が解決しようとする課題】ところが、上記の改善
提案については、なお次のような解決すべき課題が残さ
れていた。すなわち、先行提案技術においては、絶縁性
基材の両面に導体回路を有する回路基板の製造は、絶縁
性基材に貫通孔を設け、その貫通孔内へ導電性ペースト
を印刷等の方法で充填して充填ビアホールを形成した
後、両面に銅箔を貼付け、その銅箔をエッチングするこ
とによって両面に導体回路を形成していた。However, with respect to the above-mentioned improvement proposals, the following problems to be solved still remain. That is, in the prior art, in manufacturing a circuit board having conductor circuits on both sides of an insulating base material, a through hole is provided in the insulating base material, and a conductive paste is filled into the through hole by printing or the like. After the filling via holes were formed, copper foils were adhered on both sides, and the copper foils were etched to form conductor circuits on both sides.
【０００７】しかしながら、このような両面回路基板と
片面回路基板とを積層して多層プリント配線板を製造す
る際に、両面回路基板と片面回路基板とを別個の製造ラ
インにおいて製造しなければならず、多層プリント配線
板の製造コストを押し上げているという現実的な問題が
ある。However, when manufacturing a multilayer printed wiring board by laminating such a double-sided circuit board and a single-sided circuit board, the double-sided circuit board and the single-sided circuit board must be manufactured on separate manufacturing lines. However, there is a practical problem that the manufacturing cost of the multilayer printed wiring board is increased.
【０００８】さらに、両面／片面回路基板の製造工程に
おいては、導電性ペーストの充填前の攪拌時あるいは印
刷時において、導電性ペースト内に気泡が巻き込まれ
る、すなわち、気泡混入の問題がある。この導電性ペー
ストへの気泡混入の程度は、一般的には、貫通孔内に充
填するよりも非貫通孔内に充填する場合の方が大きい
が、いずれの場合でも気泡混入を極力減少させることが
層間接続抵抗を安定化させるためには必要である。Further, in the manufacturing process of the double-sided / single-sided circuit board, there is a problem that bubbles are trapped in the conductive paste during stirring or printing before filling the conductive paste, that is, bubbles are mixed. In general, the degree of air bubbles mixed into the conductive paste is larger in the case of filling non-through holes than in the case of through holes. Is necessary to stabilize the interlayer connection resistance.
【０００９】気泡混入を減少させる技術として、導電性
ペーストを充填しながらあるいは充填した後、充填され
たペーストを減圧下において加圧することによって、導
電性ペースト内に巻き込まれた気泡を除去する、いわゆ
る真空加圧脱泡という方法が提案されているが、このよ
うな技術を貫通孔内への充填に効率的に適用することは
難しく、導電性ペースト内に混入した気泡の残留を完全
に回避することは困難である。[0009] As a technique for reducing the inclusion of air bubbles, while filling or after filling the conductive paste, the filled paste is pressurized under reduced pressure to remove air bubbles entrained in the conductive paste. Although a method called vacuum pressure defoaming has been proposed, it is difficult to efficiently apply such a technique to filling in the through-hole, and completely avoids residual air bubbles mixed in the conductive paste. It is difficult.
【００１０】そこで、発明者らは絶縁性基材に設けた貫
通孔内に導電性ペーストを充填する工程を採用しない
で、両面回路基板と片面回路基板とを、それらの一部の
工程を共通する製造工程、すなわち、一面に銅箔を貼付
けた絶縁性基材に非貫通孔を設け、その非貫通孔に導電
性ペーストを充填する工程、を含んだ製造方法を提案す
るものである。本発明は、改善提案技術が抱える上記問
題点に鑑みてなされたものであり、その主たる目的は、
製造コストを低減させ、かつ層間接続抵抗を安定化させ
ることができる多層プリント配線板用の回路基板の製造
方法を提案することにある。Therefore, the inventors of the present invention do not employ a process of filling a conductive paste into a through-hole provided in an insulating substrate, but share a part of the process between the double-sided circuit board and the single-sided circuit board. In other words, the present invention proposes a manufacturing method that includes a manufacturing step of forming a non-through hole in an insulating base material having a copper foil adhered to one surface thereof and filling the non-through hole with a conductive paste. The present invention has been made in view of the above problems of the improvement proposal technology, the main purpose is,
An object of the present invention is to propose a method of manufacturing a circuit board for a multilayer printed wiring board, which can reduce the manufacturing cost and stabilize the interlayer connection resistance.
【００１１】[0011]
【課題を解決するための手段】発明者らは、上掲の目的
を実現するために鋭意研究した結果、以下の内容を要旨
構成とする本発明に想到した。すなわち、 （Ａ） 本発明の多層プリント配線板用回路基板の製造
方法は、硬質の絶縁性基材の両面に導体回路を有し、こ
の絶縁性基材中に前記導体回路間を電気的に接続するビ
アホールが形成された多層プリント配線板用回路基板を
製造するに当たって、その製造工程中に、少なくとも以
下の（１）〜（４）の工程、すなわち、（１）一面に銅
箔が貼付けられた絶縁性基材の他の面に、樹脂フィルム
を粘着させたのち、その樹脂フィルム上からレーザ照射
を行って前記銅箔に達する非貫通孔を形成する工程、
（２）前記非貫通孔内に導電性ペースト充填しながら、
あるいは充填した後、前記絶縁性基材を減圧条件下にお
いて、前記導電性ペーストを加圧する工程、（３）前記
樹脂フィルムを絶縁性基材の表面から剥離させたのち、
前記絶縁性基材の他の面から露出した導電性ペーストを
半硬化させ、そのペーストを含んだ絶縁性基材の表面
に、半硬化状態の樹脂接着剤層を形成し、その樹脂接着
剤層を介して銅箔を加熱圧着して、前記導電性ペースト
と銅箔とを電気的に接続させる工程、（４）前記絶縁性
樹脂に貼付けられた銅箔をエッチングして、導体回路を
形成する工程、とを含むことを特徴とする。Means for Solving the Problems The inventors of the present invention have made intensive studies to achieve the above-mentioned objects, and as a result, have arrived at the present invention having the following content as a gist. That is, (A) The method for producing a circuit board for a multilayer printed wiring board of the present invention has a conductor circuit on both surfaces of a hard insulating substrate, and electrically connects the conductor circuits in the insulating substrate. In manufacturing a circuit board for a multilayer printed wiring board in which via holes to be connected are formed, during the manufacturing process, at least the following steps (1) to (4), that is, (1) copper foil is adhered on one surface. The other surface of the insulating substrate, after adhering a resin film, a step of forming a non-through hole reaching the copper foil by performing laser irradiation from the resin film,
(2) While filling the non-through hole with a conductive paste,
Or after filling, a step of pressing the conductive paste under a reduced pressure condition of the insulating base, (3) after the resin film is peeled off from the surface of the insulating base,
The conductive paste exposed from the other surface of the insulating substrate is semi-cured, and a semi-cured resin adhesive layer is formed on the surface of the insulating substrate containing the paste, and the resin adhesive layer is formed. Heat-compressing the copper foil through the step to electrically connect the conductive paste and the copper foil; (4) etching the copper foil attached to the insulating resin to form a conductive circuit And a step.
【００１２】（Ｂ）また、本発明の多層プリント配線板
用回路基板の製造方法は、硬質の絶縁性基材の片面に導
体回路を有し、この絶縁性基材中に前記導体回路に達す
る充填ビアホールが形成された多層プリント配線板用回
路基板を製造するに当たって、その製造工程中に、少な
くとも以下の（１）〜（３）の工程、すなわち、（１）
一面に銅箔が貼付けられた絶縁性基材にエッチング処
理を施して導体回路を形成する工程、（２） 前記記絶
縁性基材の他の面に、樹脂フィルムを貼付け、その樹脂
フィルム上からレーザ照射を行って前記導体回路に達す
る非貫通孔を形成する工程、（３） 前記非貫通孔内に
導電性ペースト充填しながら、あるいは充填した後、前
記絶縁性基材を減圧条件下において前記導電性ペースト
を加圧して前記銅箔との電気的接続を行なう充填ビアホ
ールを形成する工程、とを含むことを特徴とする。(B) In the method of manufacturing a circuit board for a multilayer printed wiring board according to the present invention, a conductive circuit is provided on one side of a hard insulating base material, and reaches the conductive circuit in the insulating base material. In manufacturing a circuit board for a multilayer printed wiring board in which a filled via hole is formed, at least the following steps (1) to (3), that is, (1)
A step of forming a conductive circuit by performing an etching treatment on an insulating substrate having copper foil adhered to one surface thereof, (2) attaching a resin film to the other surface of the insulating substrate, Forming a non-through hole reaching the conductor circuit by irradiating a laser; (3) filling the non-through hole with or after filling a conductive paste in the non-through hole; Forming a filled via hole for electrically connecting the conductive paste to the copper foil by pressing the conductive paste.
【００１３】[0013]
【発明の実施の形態】本発明にかかる回路基板の製造方
法の特徴は、全層がＩＶＨ構造を有する多層プリント配
線板のコアとなる両面回路基板だけでなく、そのコア回
路基板に積層される積層用回路基板として用いられるの
に好適な片面回路基板を、硬質の絶縁性基材に貫通孔を
設けることなく、両面回路基板と一部共通の工程にて製
造することに特徴がある。DESCRIPTION OF THE PREFERRED EMBODIMENTS A feature of the method of manufacturing a circuit board according to the present invention is that not only a double-sided circuit board as a core of a multilayer printed wiring board in which all layers have an IVH structure, but also a laminate on the core circuit board. It is characterized in that a single-sided circuit board suitable for use as a circuit board for lamination is manufactured in a partly common process with a double-sided circuit board without providing a through hole in a hard insulating base material.
【００１４】すなわち、硬質の絶縁性基材の一方の面に
銅箔を貼付け、その絶縁性基材の他方の面から銅箔に達
する非貫通孔を形成した後に、その非貫通孔内に導電性
ペーストを充填しながら、あるいは充填した後、絶縁性
基材を減圧条件下において、導電性ペーストを加圧して
充填ビアホールを形成し、さらに絶縁性基材の他方の面
から露出する導電性ペーストを半硬化させ、そのペース
トを覆って樹脂接着剤層を形成し、その樹脂接着剤を介
して銅箔を絶縁性基材に貼付けた後に、絶縁性基材の両
面に貼付けられた銅箔をエッチングすることによって、
両面に導体回路を有する回路基板を製造することを特徴
とする。That is, a copper foil is attached to one surface of a hard insulating base material, and a non-through hole reaching the copper foil from the other surface of the insulating base material is formed. While filling or after filling the conductive paste, the conductive paste is pressed under a reduced pressure condition to form a filled via hole, and the conductive paste is exposed from the other surface of the insulating base material. After semi-curing, cover the paste to form a resin adhesive layer, paste the copper foil on the insulating base material via the resin adhesive, then paste the copper foil on both sides of the insulating base material By etching
A circuit board having conductor circuits on both sides is manufactured.
【００１５】また、硬質の絶縁性基材の一方の面に銅箔
を貼付け、その絶縁性基材にエッチング処理を施して導
体回路を形成し、絶縁性基材の他方の面から銅箔に達す
る非貫通孔を形成した後に、その非貫通孔内に導電性ペ
ーストを充填しながら、あるいは充填した後、絶縁性基
材を減圧条件下において、導電性ペーストを加圧して充
填ビアホールを形成し、さらに絶縁性基材の他方の面か
ら露出する導電性ペーストを半硬化させ、そのペースト
を覆って樹脂接着剤層を形成することによって、片面に
導体回路を有する回路基板を製造することを特徴とす
る。このような構成によれば、両面回路基板だけでな
く、それと一部共通な製造工程を経て片面回路基板も製
造できるので、製造コストの低減を図ることができ、ま
た、一面に銅箔（導体回路）が貼付けられた絶縁性基材
に設けた非貫通孔内に、真空加圧脱泡によって導電性ペ
ーストを充填するので、導電性ペーストへの気泡の残留
を極力抑えることができるので、安定した層間接続抵抗
を得ることができる。Further, a copper foil is adhered to one surface of a hard insulating base material, and the insulating base material is subjected to an etching treatment to form a conductor circuit, and the other surface of the insulating base material is applied to the copper foil. After forming the reaching non-through hole, filling the non-through hole with or after filling the conductive paste, the insulating base material under reduced pressure condition, pressurizing the conductive paste to form a filled via hole. Further, a circuit board having a conductive circuit on one side is manufactured by semi-curing a conductive paste exposed from the other surface of the insulating base material and forming a resin adhesive layer over the paste. And According to such a configuration, not only the double-sided circuit board but also a single-sided circuit board can be manufactured through a manufacturing process partially common thereto, so that the manufacturing cost can be reduced, and the copper foil (conductor) Since the conductive paste is filled by vacuum pressure degassing into the non-through holes provided in the insulating base material to which the circuit is attached, the residual air bubbles in the conductive paste can be suppressed as much as possible. The obtained interlayer connection resistance can be obtained.
【００１６】本発明の製造方法において用いられる絶縁
性基材は、従来のような半硬化状態のプリプレグではな
く、完全に硬化した樹脂材料から形成される硬質の絶縁
性基材であり、このような材料を用いることによって、
絶縁性基材上へ銅箔を加熱プレスによって圧着させる際
に、プレス圧による絶縁性基材の最終的な厚みの変動が
なくなるので、ビアホールの位置ずれを最小限度に抑え
て、ビアランド径を小さくできる。したがって配線ピッ
チを小さくして配線密度を向上させることができる。ま
た、基材の厚みを実質的に一定に保つことができるの
で、充填ビアホール形成用の非貫通孔をレーザ加工によ
って形成する場合には、そのレーザ照射条件の設定が容
易となる。The insulating substrate used in the manufacturing method of the present invention is not a conventional semi-cured prepreg but a hard insulating substrate formed from a completely cured resin material. By using various materials,
When the copper foil is pressed on the insulating base material by hot pressing, the final thickness of the insulating base material does not fluctuate due to the pressing pressure, so the positional deviation of the via hole is minimized and the via land diameter is reduced. it can. Therefore, the wiring pitch can be reduced and the wiring density can be improved. In addition, since the thickness of the base material can be kept substantially constant, when a non-through hole for forming a filled via hole is formed by laser processing, setting of the laser irradiation condition becomes easy.
【００１７】上記絶縁性基材としては、厚さが２０〜６
００μmのガラス布エポキシ基材が用いられるのが好ま
しい。その理由は、２０μｍ未満の厚さでは、強度が低
下して取扱が難しくなるとともに、電気的絶縁性に対す
る信頼性が低くなり、６００μｍを超える厚さでは微細
なビアホールの形成および導電性ペーストの充填が難し
くなるとともに、基板そのものが厚くなるためである。The insulating substrate has a thickness of 20 to 6
Preferably, a 00 μm glass cloth epoxy substrate is used. The reason for this is that if the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to electrical insulation is reduced. If the thickness exceeds 600 μm, fine via holes are formed and the conductive paste is filled. And the thickness of the substrate itself is increased.
【００１８】上記絶縁性基材の一方の表面には、適切な
樹脂接着剤を介して銅箔が貼り付けられ、エッチング処
理によって導体回路が形成される。このような絶縁性基
材上への銅箔の貼付に代えて、絶縁性基材上に予め銅箔
が貼付られた片面銅張積層板を用いることもできる。A copper foil is adhered to one surface of the insulating base material via an appropriate resin adhesive, and a conductive circuit is formed by an etching process. Instead of sticking the copper foil on the insulating base material, a single-sided copper-clad laminate in which the copper foil is stuck on the insulating base material in advance can be used.
【００１９】本発明にかかる両面回路基板を製造する際
には、まず上記銅箔が貼付けられた絶縁性基材の表面と
反対側の表面に、保護フィルムを貼付け、その保護フィ
ルム上からレーザ照射を行って非貫通孔を形成するが、
片面回路基板を製造する際には、まず上記銅箔をエッチ
ングして導体回路を形成した後、この導体回路が形成さ
れた絶縁性基材の表面と反対側の表面に、保護フィルム
を貼付け、その保護フィルム上からレーザ照射を行って
非貫通孔を形成する。上記保護フィルムは、絶縁性基材
の表面から銅箔に達する非貫通孔内に導電性ペーストを
充填する際の印刷用マスクとして機能し、絶縁性基材に
非貫通孔を形成した後は、絶縁性基材から剥離されるよ
うな粘着剤層を有する。この保護フィルムは、たとえ
ば、粘着剤層の厚みが１〜２０μｍであり、フィルム自
体の厚みが１０〜50μｍであるＰＥＴフィルムから形成
されるのが好ましい。In manufacturing the double-sided circuit board according to the present invention, first, a protective film is attached to the surface of the insulating substrate on which the copper foil is attached, opposite to the surface thereof, and laser irradiation is performed from above the protective film. To form a non-through hole,
When manufacturing a single-sided circuit board, first, after etching the copper foil to form a conductor circuit, a protective film is attached to the surface opposite to the surface of the insulating substrate on which the conductor circuit is formed, Laser irradiation is performed from above the protective film to form a non-through hole. The protective film functions as a printing mask when filling the conductive paste into the non-through holes reaching the copper foil from the surface of the insulating base material, and after forming the non-through holes in the insulating base material, It has an adhesive layer that can be peeled off from the insulating substrate. This protective film is preferably formed of, for example, a PET film in which the thickness of the pressure-sensitive adhesive layer is 1 to 20 μm and the thickness of the film itself is 10 to 50 μm.
【００２０】その理由は、ＰＥＴフィルムの厚さに依存
して、導電性ペーストの絶縁性基材表面からの突出量が
決まるので、１０μｍ未満の厚さでは突出量が小さすぎ
て接続不良になりやすく、逆に５０μｍを超えた厚さで
は、溶融した導電性ペーストが接続界面において拡がり
すぎるので、ファインパターンの形成ができないからで
ある。The reason is that the amount of protrusion of the conductive paste from the surface of the insulating base material is determined depending on the thickness of the PET film. If the thickness is less than 10 μm, the amount of protrusion is too small, resulting in poor connection. If the thickness exceeds 50 μm, the melted conductive paste spreads too much at the connection interface, so that a fine pattern cannot be formed.
【００２１】上記範囲の厚さを有するガラスエポキシ基
板上に、レーザ照射によって形成される非貫通孔は、パ
ルスエネルギーが０．５〜１００ｍＪ、パルス幅が１〜
１００μｓ、パルス間隔が０．５ｍｓ以上、ショット数
が３〜５０の条件で照射される炭酸ガスレーザによって
形成されることが好ましく、その口径は、５０〜２５０
μｍの範囲であることが望ましい。その理由は、５０μ
ｍ未満では非貫通孔内に導電性ペーストを充填し難くな
ると共に、接続信頼性が低くなるからであり、２５０μ
ｍを超えると、高密度化が困難になるからである。A non-through hole formed on a glass epoxy substrate having a thickness in the above range by laser irradiation has a pulse energy of 0.5 to 100 mJ and a pulse width of 1 to 100 mJ.
It is preferably formed by a carbon dioxide laser irradiated under the conditions of 100 μs, pulse interval of 0.5 ms or more, and the number of shots is 3 to 50, and the diameter is 50 to 250.
It is desirable to be in the range of μm. The reason is 50μ
When the diameter is less than 250 m, it is difficult to fill the non-through hole with the conductive paste and the connection reliability is lowered.
If the number exceeds m, it is difficult to increase the density.
【００２２】非貫通孔に導電性ペーストを充填する前
に、非貫通孔の内壁面に残留する樹脂残滓を取り除くた
めのデスミア処理を行うことが接続信頼性確保の点から
望ましく、たとえば、プラズマ放電やコロナ放電等を用
いたドライデスミア処理や、過マンガン酸カリウム溶液
等を用いたウエットデスミア処理のいずれでも可能であ
る。Before filling the non-through hole with the conductive paste, desmear treatment for removing resin residue remaining on the inner wall surface of the non-through hole is desirable from the viewpoint of ensuring connection reliability. Or a dry desmear treatment using a corona discharge or a wet desmear treatment using a potassium permanganate solution or the like.
【００２３】上記絶縁性基材の非貫通孔に対するデスミ
ア処理の後、真空加圧脱泡法によって、非貫通孔内に充
填される導電性ペーストは、製造コストを低減させ、歩
留まりを向上させるのに好適である。上記導電性ペース
トとしては、銀、銅、金、ニッケル、半田から選ばれる
少なくとも1 種以上の金属粒子を含む導電性ペーストを
使用できる。After the desmear treatment for the non-through holes of the insulating base material, the conductive paste filled in the non-through holes by vacuum pressure defoaming can reduce the manufacturing cost and improve the yield. It is suitable for. As the conductive paste, a conductive paste containing at least one or more metal particles selected from silver, copper, gold, nickel, and solder can be used.
【００２４】また、前記金属粒子としては、金属粒子の
表面に異種金属をコーティングしたものも使用できる。
具体的には銅粒子の表面に金、銀から選ばれる貴金属を
被覆した金属粒子を使用することができる。上記導電性
ペーストとしては、金属粒子に、エポキシ樹脂、フェノ
ール樹脂などの熱硬化性樹脂、ポリフェニレンスルフイ
ド（ＰＰＳ）などの熱可塑性樹脂を加えた有機系導電性
ペーストを用いることもできる。このような導電性ペー
ストの非貫通孔内への充填は、メタルマスクを用いた印
刷による方法や、スクイージやディスペンサーを用いた
方法等のいずれの方法でも可能である。Further, as the metal particles, those obtained by coating the surface of metal particles with a dissimilar metal can also be used.
Specifically, metal particles in which the surface of copper particles is coated with a noble metal selected from gold and silver can be used. As the conductive paste, an organic conductive paste obtained by adding a thermosetting resin such as an epoxy resin or a phenol resin or a thermoplastic resin such as polyphenylene sulfide (PPS) to metal particles can also be used. The filling of the conductive paste into the non-through holes can be performed by any method such as a printing method using a metal mask or a method using a squeegee or a dispenser.
【００２５】また、減圧条件および印加する圧力は、導
電性ペーストの粘度、溶剤の種類や量、スルーホールや
ビアホールの開口径および深さに応じて決定され、この
ような適切な条件下での導電性ペーストへの圧力印加
は、例えば、公知のプレス装置やドライフィルム形成用
の真空ラミネータを用いて行うことができる。さらに、
必要に応じて、開口内に充填された導電性ペーストを加
熱して、その流動性を高めることによって、気泡排除の
時間を短縮することができる。The pressure reduction conditions and the applied pressure are determined according to the viscosity of the conductive paste, the type and amount of the solvent, the opening diameter and the depth of the through-holes and via holes, and under such appropriate conditions. Pressure application to the conductive paste can be performed using, for example, a known press device or a vacuum laminator for forming a dry film. further,
If necessary, the conductive paste filled in the openings is heated to increase the fluidity thereof, so that the time for eliminating bubbles can be reduced.
【００２６】片面回路基板を製造する際には、上記絶縁
性基材の非貫通孔内に導電性ペーストを充填した後、絶
縁性基材から保護フィルムを剥離させることによって、
充填ビアホールを形成するが、絶縁性基材表面に露出し
た導電性ペーストを覆った半硬化の樹脂接着剤を形成す
ることが望ましい。When manufacturing a single-sided circuit board, a conductive paste is filled into the non-through holes of the insulating base material, and then the protective film is peeled off from the insulating base material.
Although a filled via hole is formed, it is desirable to form a semi-cured resin adhesive covering the conductive paste exposed on the surface of the insulating base material.
【００２７】また、両面回路基板を製造する際には、上
記絶縁性基材の非貫通孔内に導電性ペーストを充填した
後、保護フィルムを剥離して、絶縁性基材表面に露出し
た導電性ペーストを覆った半硬化状態の樹脂接着剤を形
成し、この樹脂接着剤を介して絶縁性基材表面に銅箔を
加熱プレスすることによって、導電性ペーストと銅箔と
が電気的に接続される。When a double-sided circuit board is manufactured, a conductive paste is filled in the non-through holes of the insulating base material, and then the protective film is peeled off to expose the conductive base material exposed on the surface of the insulating base material. The conductive paste and the copper foil are electrically connected by forming a semi-cured resin adhesive covering the conductive paste and hot-pressing the copper foil on the surface of the insulating base material through the resin adhesive. Is done.
【００２８】上記樹脂接着剤は、たとえば、ビスフェノ
ールＡ型エポキシ樹脂から形成され、その厚みは１０〜
５０μｍの範囲が好ましい。また、上記銅箔の厚さは、
５〜１８μｍが望ましく、また加熱プレスは、適切な温
度および加圧力のもとで行なわれる。より好ましくは、
減圧下において加熱プレスが行なわれ、半硬化状態の樹
脂接着剤層のみを硬化することによって、銅箔を絶縁性
基材に対してしっかりと接着され得るので、従来のプリ
プレグを用いた回路基板に比べて製造時間が短縮され
る。The resin adhesive is formed of, for example, a bisphenol A type epoxy resin and has a thickness of 10 to 10.
A range of 50 μm is preferred. The thickness of the copper foil is
The thickness is preferably 5 to 18 μm, and the hot pressing is performed at an appropriate temperature and pressure. More preferably,
Heat pressing is performed under reduced pressure, and by curing only the resin adhesive layer in a semi-cured state, the copper foil can be firmly adhered to the insulating base material, so it can be applied to a circuit board using a conventional prepreg. The manufacturing time is shortened in comparison.
【００２９】上記絶縁性基材の一面に貼付けられた銅箔
は、前述したように絶縁性基材の他の面に予め貼付けて
ある銅箔とともに、適切なエッチング処理が施されて、
絶縁性基材の両面に導体回路が形成される。The copper foil adhered to one surface of the insulating substrate is subjected to an appropriate etching treatment together with the copper foil previously adhered to the other surface of the insulating substrate as described above.
Conductive circuits are formed on both surfaces of the insulating base material.
【００３０】このように導体回路が絶縁性基材の両面に
形成されるような回路基板は、多層プリント配線板を形
成する際のコア基板として適切であるが、各ビアホール
に対応した基板表面には、導体回路の一部としてのビア
ランド(パッド)が、その口径が５０〜２５０μｍの範囲
に形成されるのが好ましい実施の形態である。また、導
体回路が絶縁性基材の片面に形成されるような回路基板
は、積層用回路基板として適切であり、ビアホールに充
填された導電性ペーストを基板表面から所定量だけ露出
させて突起状導体を形成することが好ましい。A circuit board in which conductive circuits are formed on both sides of an insulating base material as described above is suitable as a core board when forming a multilayer printed wiring board. Is a preferred embodiment in which a via land (pad) as a part of a conductor circuit is formed in a diameter of 50 to 250 μm. Further, a circuit board in which a conductive circuit is formed on one side of an insulating base material is suitable as a circuit board for lamination, and the conductive paste filled in the via hole is exposed from the board surface by a predetermined amount to form a projection. Preferably, a conductor is formed.
【００３１】以下、本発明にかかる多層プリント配線板
用の両面回路基板の製造方法の一例について、図１を参
照にして具体的に説明する。 本発明にかかる両面回路板を製造するに当たって、絶
縁性基材１０の片面に銅箔が１２が貼付けられたものを
出発材料として用いる（図１(a)参照）。この絶縁性基
材１０は、たとえば、ガラス布エポキシ樹脂基材、ガラ
ス布ビスマレイミドトリアジン樹脂基材、ガラス布ポリ
フェニレンエーテル樹脂基材、アラミド不織布−エポキ
シ樹脂基材、アラミド不織布−ポリイミド樹脂基材から
選ばれるリジッド（硬質）な積層基材が使用され得る
が、ガラス布エポキシ樹脂基材が最も好ましい。Hereinafter, an example of a method for manufacturing a double-sided circuit board for a multilayer printed wiring board according to the present invention will be specifically described with reference to FIG. In manufacturing the double-sided circuit board according to the present invention, a material in which a copper foil 12 is adhered to one surface of an insulating base material 10 is used as a starting material (see FIG. 1A). The insulating base material 10 is, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid nonwoven fabric-epoxy resin base material, an aramid nonwoven fabric-polyimide resin base material. A rigid (hard) laminated substrate of choice may be used, but glass cloth epoxy resin substrates are most preferred.
【００３２】上記絶縁性基材１０の厚さは、２０〜６０
０μｍが望ましい。その理由は、２０μｍ未満の厚さで
は、強度が低下して取扱が難しくなるとともに、電気的
絶縁性に対する信頼性が低くなり、６００μｍを超える
厚さでは微細なビアホールの形成および導電性ペースト
の充填が難しくなるとともに、基板そのものが厚くなる
ためである。The thickness of the insulating substrate 10 is 20 to 60.
0 μm is desirable. The reason for this is that if the thickness is less than 20 μm, the strength is reduced and handling becomes difficult, and the reliability with respect to electrical insulation is reduced. If the thickness exceeds 600 μm, fine via holes are formed and the conductive paste is filled. And the thickness of the substrate itself is increased.
【００３３】また銅箔１２の厚さは、５〜１８μｍが望
ましい。その理由は、後述するようなレーザ加工を用い
て、絶縁性基材にビアホール形成用の非貫通孔を形成す
る際に、薄すぎると貫通してしまうからであり、逆に厚
すぎるとエッチングにより、ファインパターンを形成し
難いからである。上記絶縁性基材１０および銅箔１２と
しては、特に、エポキシ樹脂をガラスクロスに含潰させ
てＢステージとしたプリプレグと、銅箔とを積層して加
熱プレスすることにより得られる片面銅張積層板を用い
ることが好ましい。その理由は、銅箔１２が後述するよ
うにエッチングされた後の取扱中に、配線パターンやビ
アホールの位置がずれることがなく、位置精度に優れる
からである。The thickness of the copper foil 12 is preferably 5 to 18 μm. The reason is that, when forming a non-through hole for forming a via hole in an insulating base material by using a laser processing as described later, if it is too thin, it penetrates. This is because it is difficult to form a fine pattern. As the insulating base material 10 and the copper foil 12, in particular, a single-sided copper-clad laminate obtained by laminating a prepreg obtained by impregnating an epoxy resin in a glass cloth into a B-stage, and laminating and hot-pressing the copper foil. It is preferable to use a plate. The reason is that the positions of the wiring patterns and the via holes do not shift during handling after the copper foil 12 is etched as described later, and the positional accuracy is excellent.
【００３４】このような絶縁性基材１０の銅箔１２が
貼付けられた表面と反対側の表面に、保護フィルム１６
を貼付ける（図１(b)参照）。この保護フィルム１６
は、後述する導電性ペーストの印刷用マスクとして使用
され、たとえば、表面に粘着層を設けたポリエチレンテ
レフタレート（ＰＥＴ）フィルムが使用され得る。前記
ＰＥＴフィルム１６は、粘着剤層の厚みが1〜２０μ
ｍ、フィルム自体の厚みが１０〜５０μｍであるような
ものが使用される。On the surface of the insulating base material 10 opposite to the surface to which the copper foil 12 is attached, a protective film 16 is provided.
(See FIG. 1 (b)). This protective film 16
Is used as a mask for printing a conductive paste described later, and for example, a polyethylene terephthalate (PET) film provided with an adhesive layer on the surface can be used. The PET film 16 has a pressure-sensitive adhesive layer thickness of 1 to 20 μm.
m, a film having a thickness of 10 to 50 μm is used.
【００３５】ついで、絶縁性基材１０上に貼付けられ
たＰＥＴフィルム１６上からレーザ照射を行って、ＰＥ
Ｔフィルム１６を貫通して、絶縁性基材１０の表面から
銅箔１２に達する非貫通孔１８を形成する（図１(ｃ)参
照）。このレーザ加工は、パルス発振型炭酸ガスレーザ
加工装置によって行われる。加工条件は、パルスエネル
ギーが０．５〜１００ｍＪ、パルス幅が１〜１００μ
ｓ、パルス間隔が０．５ｍｓ以上、ショット数が３〜５
０の範囲内であることが望ましい。このような加工条件
のもとで形成され得る非貫通孔１８の口径は、５０〜２
５０μｍであることが望ましい。Then, laser irradiation is performed from above the PET film 16 stuck on the insulating base material 10 to obtain a PE film.
Non-through holes 18 are formed through the T film 16 and reach the copper foil 12 from the surface of the insulating substrate 10 (see FIG. 1C). This laser processing is performed by a pulse oscillation type carbon dioxide laser processing apparatus. The processing conditions were as follows: pulse energy 0.5 to 100 mJ, pulse width 1 to 100 μJ
s, pulse interval 0.5 ms or more, number of shots 3-5
It is desirable to be within the range of 0. The diameter of the non-through hole 18 that can be formed under such processing conditions is 50 to 2
Desirably, it is 50 μm.
【００３６】前記の工程で形成された非貫通孔１８
の内壁面に残留する樹脂残滓を取り除くために、デスミ
ア処理を行う。このデスミア処理としては、プラズマ放
電、コロナ放電等を用いたドライデスミア処理や過マン
ガン酸カリウム溶液等を用いたウエットデスミア処理が
可能である。The non-through hole 18 formed in the above process
Desmear treatment is performed to remove the resin residue remaining on the inner wall surface of the substrate. As the desmear treatment, a dry desmear treatment using a plasma discharge, a corona discharge, or the like, or a wet desmear treatment using a potassium permanganate solution or the like is possible.
【００３７】次に、デスミア処理された非貫通孔１８
内に印刷によって導電性ペースト２０を充填する（図1
(ｄ)参照）。その後、基板全体を真空チェンバー（図示
を省略）内のステージ上に固定し、1×１０３〜5×１０
３Ｐａの減圧下において、絶縁性基材１０の導電性ペー
スト２０の露出側の表面を適切なプレス装置（図示を省
略）によって、数分間だけ加圧して、半硬化状態にす
る。Next, the desmeared non-through hole 18
The inside is filled with a conductive paste 20 by printing (see FIG. 1).
(d)). Thereafter, the entire substrate is fixed on a stage in a vacuum chamber (not shown), and 1 × 10 3 to 5 × 10
Under a reduced pressure of 3 Pa, the surface of the insulating substrate 10 on the exposed side of the conductive paste 20 is pressed for a few minutes by a suitable press device (not shown) to be in a semi-cured state.
【００３８】その後、ＰＥＴフィルム１６を絶縁性基
材１０の表面から剥離させたのち、半硬化状態の接着剤
層、すなわちＢステージの接着剤層１４を配置し（図１
(ｅ)参照）、この接着剤層１４を介して銅箔２４を絶縁
性基材１０の表面に加熱プレスによって圧着して、接着
剤層１４を硬化させる（図１(f)参照）。この接着剤１
４は、たとえば、エポキシ樹脂ワニスが使用され、その
層厚は１０〜５０μｍの範囲が望ましく、銅箔２４の厚
さは、５〜１８μｍが望ましい。上記加熱プレスによっ
て、銅箔２４は硬化した接着剤層１４を介して絶縁性基
材１０に接着され、導電性ペースト２０と銅箔２４とが
電気的に接続される。Then, after the PET film 16 is peeled off from the surface of the insulating substrate 10, the adhesive layer in a semi-cured state, that is, the B-stage adhesive layer 14 is disposed (FIG. 1).
(See (e)), the copper foil 24 is pressed against the surface of the insulating substrate 10 via the adhesive layer 14 by a hot press, and the adhesive layer 14 is cured (see FIG. 1 (f)). This adhesive 1
For example, epoxy resin varnish 4 is used, and its layer thickness is desirably in the range of 10 to 50 μm, and the thickness of copper foil 24 is desirably 5 to 18 μm. By the heating press, the copper foil 24 is adhered to the insulating base material 10 via the cured adhesive layer 14, and the conductive paste 20 and the copper foil 24 are electrically connected.
【００３９】ついで、絶縁性基材１０の両面に貼付け
られた銅箔１２および２４上に、それぞれエッチング保
護フィルムを貼付けて、所定の回路パターンのマスクで
披覆した後、エッチング処理を行って、導体回路２６お
よび２８（ビアランドを含む）を形成する（図１(g)参
照）。この処理工程においては、先ず、銅箔１２および
２４の表面に感光性ドライフィルムレジストを貼付した
後、所定の回路パターンに沿って露光、現像処理してエ
ッチングレジストを形成し、エッチングレジスト非形成
部分の金属層をエッチングして、ビアランドを含んだ導
体回路パターン２６および２８を形成する。エッチング
液としては、硫酸一過酸化水素、過硫酸塩、塩化第二
銅、塩化第二鉄の水溶液から選ばれる少なくとも1種の
水溶液が望ましい。上記銅箔１２および２４をエッチン
グして導体回路２６および２８を形成する前処理とし
て、ファインパターンを形成しやすくするため、あらか
じめ、銅箔の表面全面をエッチングして厚さを１〜１０
μｍ、より好ましくは２〜８μｍ程度まで薄くすること
ができる。導体回路の一部としてのビアランドは、その
内径がビアホール径とほぼ同様であるが、その外径は、
５０〜２５０μｍの範囲に形成されることが好ましい。Next, an etching protection film is stuck on each of the copper foils 12 and 24 stuck on both sides of the insulating base material 10, and is covered with a mask having a predetermined circuit pattern. Conductive circuits 26 and 28 (including via lands) are formed (see FIG. 1 (g)). In this processing step, first, a photosensitive dry film resist is attached to the surfaces of the copper foils 12 and 24, and then exposed and developed along a predetermined circuit pattern to form an etching resist. Is etched to form conductive circuit patterns 26 and 28 including via lands. As the etching solution, at least one aqueous solution selected from aqueous solutions of sulfuric acid hydrogen peroxide, persulfate, cupric chloride, and ferric chloride is desirable. As a pretreatment for forming the conductor circuits 26 and 28 by etching the copper foils 12 and 24, in order to easily form a fine pattern, the entire surface of the copper foil is previously etched to a thickness of 1 to 10 to facilitate formation of a fine pattern.
μm, more preferably about 2 to 8 μm. The via land as a part of the conductor circuit has an inner diameter almost the same as the via hole diameter, but the outer diameter is
Preferably, it is formed in the range of 50 to 250 μm.
【００４０】次に、前記の工程で形成した導体回路
２６および２８の表面を粗化処理して（粗化層の表示は
省略する）、コア用の両面回路基板３０を形成する。こ
の粗化処理は、多層化する際に、接着剤層との密着性を
改善し、剥離（デラミネーション）を防止するためであ
る。粗化処理方法としては、例えば、ソフトエッチング
処理や、黒化（酸化）一還元処理、銅−ニッケルーリン
からなる針状合金めっき（荏原ユージライト製：商品名
インタープレート）の形成、メック社製の商品名「メッ
クエッチボンド」なるエッチング液による表面粗化があ
る。Next, the surfaces of the conductor circuits 26 and 28 formed in the above steps are roughened (roughened layers are not shown) to form a double-sided circuit board 30 for a core. This roughening treatment is for improving adhesion to the adhesive layer and preventing peeling (delamination) when forming a multilayer. Roughening methods include, for example, soft etching, blackening (oxidation) and one-reduction treatment, formation of a copper-nickel-phosphorus needle-like alloy plating (manufactured by Ebara Uzilite; trade name: Interplate), manufactured by MEC Corporation. Surface roughening by an etching solution called "Mech etch bond".
【００４１】この実施形態においては、上記粗化層の形
成は、エッチング液を用いて形成されるのが好ましく、
たとえば、導体回路の表面を第二銅錯体と有機酸の混合
水溶液からエッチング液を用いてエッチング処理するこ
とによって形成することができる。かかるエッチング液
は、スプレーやバブリングなどの酸素共存条件下で、銅
導体回路を溶解させることができ、反応は、次のように
進行するものと推定される。 Ｃｕ＋Ｃｕ（II）Ａｎ →２Ｃｕ（Ｉ）Ａｎ／２ ２Ｃｕ（Ｉ）Ａｎ／２ ＋ｎ／４Ｏ２ ＋ｎＡＨ （エアレーション） →２Ｃｕ（II）Ａｎ ＋ｎ／２Ｈ２Ｏ 式中、Ａは錯化剤（キレート剤として作用）、ｎは配位
数を示す。In this embodiment, the roughened layer is preferably formed by using an etching solution.
For example, it can be formed by etching the surface of a conductor circuit from a mixed aqueous solution of a cupric complex and an organic acid using an etchant. Such an etchant can dissolve the copper conductor circuit under the condition of coexistence of oxygen such as spraying or bubbling, and the reaction is presumed to proceed as follows. Cu + Cu (II) A n → 2Cu (I) An / 2 2Cu (I) A n / 2 + n / 4O 2 + nAH (aeration) → 2Cu (II) A n + n / 2H 2 O In the formula, A is a complex. Agent (acting as a chelating agent), n represents the coordination number.
【００４２】この式に示されるように、発生した第一銅
錯体は、酸の作用で溶解し、酸素と結合して第二銅錯体
となって、再び銅の酸化に寄与する。本発明で用いられ
る第二銅錯体は、アゾール類の第二銅錯体がよい。この
有機酸−第二銅錯体からなるエッチング液は、アゾール
類の第二銅錯体および有機酸（必要に応じてハロゲンイ
オン）を、水に溶解して調製することができる。このよ
うなエッチング液は、たとえば、イミダゾール銅(ＩＩ)
錯体 １０重量部、グリコール酸 ７重量部、塩化カリ
ウム ５重量部を混合した水溶液から形成される。上記
〜の工程にしたがって製造された、本発明にかかる
多層プリント配線板用両面回路基板は、多層プリント配
線板のコア用回路基板として好適である。As shown in this formula, the generated cuprous complex dissolves under the action of an acid and combines with oxygen to form a cupric complex, which again contributes to copper oxidation. The cupric complex used in the present invention is preferably a cupric complex of azoles. The etching solution comprising the organic acid-cupric complex can be prepared by dissolving a cupric complex of an azole and an organic acid (halogen ion as required) in water. Such an etchant is, for example, imidazole copper (II)
It is formed from an aqueous solution in which 10 parts by weight of a complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride are mixed. The double-sided circuit board for a multilayer printed wiring board according to the present invention manufactured according to the above-mentioned steps is suitable as a core circuit board of the multilayer printed wiring board.
【００４３】次に、上記両面回路基板の表面および裏面
にそれぞれ積層される片面回路基板の製造方法につい
て、図２を参照にして説明する。 （１）まず、絶縁性基材１０の片面に貼付けられた銅箔
１２上に、エッチング保護フィルムを貼付けて、所定の
回路パターンのマスクで披覆した後、エッチング処理を
行って、導体回路３４（ビアランドを含む）を形成する
（図２(ｂ)参照）。この処理工程においては、先ず、銅
箔１２の表面に感光性ドライフィルムレジストを貼付し
た後、所定の回路パターンに沿って露光、現像処理して
エッチングレジストを形成し、エッチングレジスト非形
成部分の金属層をエッチングして、ビアランドを含んだ
導体回路パターン３４を形成する。エッチング液として
は、硫酸一過酸化水素、過硫酸塩、塩化第二銅、塩化第
二鉄の水溶液から選ばれる少なくとも1種の水溶液が望
ましい。上記銅箔１２をエッチングして導体回路３４を
形成する前処理として、ファインパターンを形成しやす
くするため、あらかじめ、銅箔の表面全面をエッチング
して厚さを1〜１０μｍ、より好ましくは２〜８μｍ程
度まで薄くすることができる。Next, a method of manufacturing a single-sided circuit board to be laminated on the front and back surfaces of the double-sided circuit board will be described with reference to FIG. (1) First, an etching protection film is stuck on the copper foil 12 stuck on one side of the insulating base material 10 and covered with a mask of a predetermined circuit pattern. (Including via lands) are formed (see FIG. 2B). In this processing step, first, after a photosensitive dry film resist is attached to the surface of the copper foil 12, exposure and development are performed along a predetermined circuit pattern to form an etching resist, and the metal in a portion where the etching resist is not formed is formed. The layer is etched to form a conductor circuit pattern 34 including via lands. As the etching solution, at least one aqueous solution selected from aqueous solutions of sulfuric acid hydrogen peroxide, persulfate, cupric chloride, and ferric chloride is desirable. As a pretreatment for etching the copper foil 12 to form the conductive circuit 34, in order to easily form a fine pattern, the entire surface of the copper foil is previously etched to a thickness of 1 to 10 μm, more preferably 2 to 10 μm. The thickness can be reduced to about 8 μm.
【００４４】（２）導体回路３４を絶縁性基材１０の片
面に形成した後、上記両面回路基板の〜の工程にし
たがった処理を行ない（図２（ｃ）〜図２（ｄ）参
照）、その後、ＰＥＴフィルム16を絶縁性基材１０の表
面から剥離させた後、絶縁性基材１０の樹脂面および突
起状導体３６を覆って接着剤層３８を形成することによ
って、絶縁性基材１０の片面に導体回路３４が形成さ
れ、かつその導体回路３４に電気的に接続された充填ビ
アホール２２を備えた片面回路基板４０が製造される
（図２（ｅ）参照）。上記接着剤層３８は、両面回路基
板に片面回路基板を積層して多層プリント配線板を製造
する際に、隣接する回路基板同士を接続するために設け
られ、絶縁性基材１０の樹脂面全体に塗布され、乾燥化
された状態の未硬化樹脂からなる接着剤層３８として形
成され、取扱が容易になるため、プレキュアしておくこ
とが好ましく、その厚さは、２０〜３０μｍの範囲が望
ましい。(2) After the conductor circuit 34 is formed on one surface of the insulating base material 10, a process according to the steps (1) to (3) of the double-sided circuit board is performed (see FIGS. 2 (c) to 2 (d)). Then, after the PET film 16 is peeled off from the surface of the insulating base material 10, the adhesive layer 38 is formed by covering the resin surface of the insulating base material 10 and the protruding conductor 36. The single-sided circuit board 40 having the conductive circuit 34 formed on one side of the substrate 10 and the filled via hole 22 electrically connected to the conductive circuit 34 is manufactured (see FIG. 2E). The adhesive layer 38 is provided for connecting adjacent circuit boards when a single-sided circuit board is laminated on a double-sided circuit board and a multilayer printed wiring board is manufactured, and the entire resin surface of the insulating base material 10 is provided. Is formed as an adhesive layer 38 made of an uncured resin in a dried state, and is preferably precured for easy handling, and its thickness is preferably in a range of 20 to 30 μm. .
【００４５】このように、上記（１）〜（２）の工程に
したがって製造される片面回路基板は、絶縁性基材１０
の一方の表面に導体回路３４を有し、他方の表面には導
電性ペーストの一部が露出して形成される突起状導体３
６を有するとともに、突起状導体を含んだ絶縁性基材表
面を覆った樹脂接着剤層を有し、これらの複数枚の片面
回路基板は、予め上記工程〜にしたがって製造され
たコア用回路基板３０に積層されて多層化される。As described above, the single-sided circuit board manufactured according to the steps (1) and (2) is a
Has a conductor circuit 34 on one surface and a protruding conductor 3 formed on the other surface by exposing a part of the conductive paste.
6 and a resin adhesive layer covering the surface of the insulating base material including the protruding conductors. The layers 30 are laminated to form a multilayer.
【００４６】図３は、コア用両面回路基板３０の両面
に、３枚の片面回路基板４０、４２および４４が積層さ
れてなる４層基板が、加熱温度１５０〜２００℃、加圧
力１Ｍ〜４ＭＰａの条件下で、1度のプレス成形により
一体化された多層プリント配線板を示している。このよ
うに、加圧と同時に加熱することで、各片面回路基板が
製造されて後、多層化する段階において設けた接着剤層
３８が硬化し、隣接する片面回路基板との間で強固な接
着が行われる。なお、熱プレスとしては、真空熱プレス
を用いることが好適である。FIG. 3 shows a four-layer board in which three single-sided circuit boards 40, 42 and 44 are laminated on both sides of a core double-sided circuit board 30 at a heating temperature of 150 to 200 ° C. and a pressure of 1 to 4 MPa. 1 shows a multilayer printed wiring board integrated by a single press molding under the conditions described above. As described above, by heating simultaneously with pressurization, after each single-sided circuit board is manufactured, the adhesive layer 38 provided in the stage of multilayering is hardened, and strong adhesion between adjacent single-sided circuit boards is achieved. Is performed. It is preferable to use a vacuum hot press as the hot press.
【００４７】上述した実施形態では、コア用両面回路基
板と３層の片面回路基板とを用いて４層に多層化した
が、５層あるいは６層を超える多層プリント配線板の製
造にも適用できる。In the embodiment described above, the double-sided circuit board for the core and the three-sided single-sided circuit board are used to make the multilayer into four layers. However, the present invention can also be applied to the manufacture of a multilayer printed wiring board having more than five or six layers. .
【００４８】[0048]
【実施例】（実施例１） （１）エポキシ樹脂をガラスクロスに含潰させてＢステ
ージとしたプリプレグと、銅箔とを積層して加熱プレス
することにより得られる片面銅張積層板を基板として用
いる。絶縁性基材１０の厚さは７５μｍ、銅箔１２の厚
さは、１２μｍとした。EXAMPLES (Example 1) (1) A single-sided copper-clad laminate obtained by laminating a prepreg in which epoxy resin is impregnated in a glass cloth into a B stage and a copper foil and pressing the laminate with heat is used as a substrate. Used as The thickness of the insulating base material 10 was 75 μm, and the thickness of the copper foil 12 was 12 μm.
【００４９】（２）このような絶縁性基材１０の銅箔１
２が貼付けられた表面と反対側の表面に、厚さ２２μｍ
のＰＥＴフィルム１６を貼付ける。上記ＰＥＴフィルム
１６は、厚みが１０μｍの粘着剤層と、厚みが１２μｍ
のフィルムベースとからなる。(2) Copper foil 1 of such insulating base material 10
2 on the surface opposite to the surface on which
Is attached. The PET film 16 has an adhesive layer having a thickness of 10 μm and a thickness of 12 μm.
And a film base.
【００５０】（３）次いで、ＰＥＴフィルム１６上か
ら、以下のようなレーザ加工条件でパルス発振型炭酸ガ
スレーザを照射して、ビアホール形成用の非貫通孔１８
を形成する。 〔レーザ加工条件〕 パルスエネルギー ４．０ｍＪ パルス幅 １５μｓ パルス間隔 ２ｍｓ以上 ショット数 ５(3) Next, a pulse oscillation type carbon dioxide laser is irradiated from above the PET film 16 under the following laser processing conditions to form a non-through hole 18 for forming a via hole.
To form [Laser processing conditions] Pulse energy 4.0 mJ Pulse width 15 μs Pulse interval 2 ms or more Number of shots 5
【００５１】（４）さらに、非貫通孔１８の開口内壁に
残留する樹脂を取り除くために、以下のような条件に
て、プラズマ装置を用いたプラズマクリーニング処理を
施す。 〔プラズマクリーンニング条件〕 電極冷却方式： 水冷 熱伝導性シート： 金属粒子入シリコーン樹脂 反応ガス： Ｏ２とＣＦ４との混合ガス（Ｏ２：ＣＦ４＝７０：３０） チャンバー内真空度： ７．３×１０４Ｐａ 出力： ５００Ｗ 通電時間： ３分 回路基板温度： ６０℃(4) Further, in order to remove the resin remaining on the inner wall of the opening of the non-through hole 18, a plasma cleaning process using a plasma apparatus is performed under the following conditions. [Plasma cleaning conditions] Electrode cooling method: Water cooling Thermal conductive sheet: Silicone resin containing metal particles Reactive gas: Mixed gas of O 2 and CF 4 (O 2 : CF 4 = 70: 30) Degree of vacuum in chamber: 7 3 × 10 4 Pa output: 500 W energization time: 3 minutes Circuit board temperature: 60 ° C.
【００５２】（５）次いで、導電性ペースト２０を、Ｐ
ＥＴフィルム１６を印刷マスクとして、貫通孔１８の内
部に充填して、１５０μｍφの充填ビアホール２２を形
成する。その際、以下のような条件で真空加圧脱泡を行
う。 〔真空加圧脱泡条件〕 真空度： ２．５×１０３Ｐａ 加圧力： ２ＭＰａ(5) Next, the conductive paste 20 is
Using the ET film 16 as a print mask, the inside of the through hole 18 is filled to form a filled via hole 22 having a diameter of 150 μm. At this time, vacuum pressure degassing is performed under the following conditions. [Vacuum pressure defoaming conditions] Degree of vacuum: 2.5 × 10 3 Pa Pressure: 2 MPa
【００５３】（６）ＰＥＴフィルム１６を剥離した後、
ペースト２０を１００℃で３０分間加熱して半硬化さ
せ、さらにＢステージのエポキシ樹脂からなる接着剤層
１４を設け、この接着剤層１４を介して、厚さ１２μｍ
の銅箔２４を、以下のような条件のもとで接着剤層１４
上に加熱プレスする。 〔加熱プレス条件〕 加熱温度： １８０℃ 加熱時間： ７０分 圧力： ２ＭＰａ 真空度： ２．５×１０３Ｐａ その後、銅箔１２および２４に適切なエッチング処理を
施して、導体回路２６および２８（ビアランドを含む）
を形成して、両面回路基板３０を作製した。(6) After peeling off the PET film 16,
The paste 20 is heated at 100 ° C. for 30 minutes to be semi-cured. Further, an adhesive layer 14 made of a B-stage epoxy resin is provided.
Of the adhesive layer 14 under the following conditions.
Heat press on top. [Heating Press Conditions] Heating temperature: 180 ° C. Heating time: 70 minutes Pressure: 2 MPa Vacuum degree: 2.5 × 10 3 Pa Thereafter, the copper foils 12 and 24 are subjected to an appropriate etching treatment, and the conductor circuits 26 and 28 ( Including via land)
Was formed to produce a double-sided circuit board 30.
【００５４】（実施例２） （１）上記実施例１の（１）の工程の後に、絶縁性基材
１０の一面に貼付けられた銅箔１２に適切なエッチング
処理を施して、導体回路３４（ビアランドを含む）を形
成する。 （２）次に、上記実施例１の（２）〜（５）の工程とほ
ぼ同様の処理を行って、導電性ペースト２０を非貫通孔
１８の内部に充填し、かつ硬化させて、１５０μｍφの
充填ビアホール２２を形成し、さらに、ＰＥＴフィルム
１６を剥離させた後に、突起状導体３６を含んだ絶縁性
基材１０の表面に樹脂接着剤層３８を形成して、片面回
路基板４０を作製した。(Embodiment 2) (1) After the step (1) of Embodiment 1 described above, the copper foil 12 adhered to one surface of the insulating base material 10 is subjected to an appropriate etching treatment so that the conductor circuit 34 (Including via lands). (2) Next, the conductive paste 20 is filled into the non-through holes 18 and cured by performing substantially the same processing as the steps (2) to (5) of the first embodiment, and After forming the filled via hole 22 and peeling off the PET film 16, a resin adhesive layer 38 is formed on the surface of the insulating base material 10 including the protruding conductor 36, thereby manufacturing the single-sided circuit board 40. did.
【００５５】(比較例１) 硬化されたガラス布エポキシ樹脂基材（厚さ７５μ
ｍ）からなる絶縁性基材の両面に接着剤を塗布し、１０
０℃で３０分間の乾燥を行って厚さ２０μｍの接着剤層
を形成し、さらにその接着剤層の上に、厚みが１０μｍ
の粘着剤層を有し、フィルム自体の厚みが１２μｍのＰ
ＥＴフィルムをラミネートする。Comparative Example 1 A cured glass cloth epoxy resin base material (thickness: 75 μm)
m), an adhesive is applied to both sides of the insulating substrate,
Drying was performed at 0 ° C. for 30 minutes to form an adhesive layer having a thickness of 20 μm, and further, a thickness of 10 μm was formed on the adhesive layer.
P having a pressure-sensitive adhesive layer of 12 μm
Laminate the ET film.
【００５６】次いで、ＰＥＴフィルム上からパルス発
振型炭酸ガスレーザを照射してビアホール形成用の貫通
孔を形成し、さらにＰＥＴフィルムを印刷マスクとし
て、印刷によって貫通孔内部に導電性ペーストを充填し
て、１５０μｍφの充填ビアホールを形成する。Next, a through-hole for forming a via hole is formed by irradiating a pulse oscillation type carbon dioxide laser from above the PET film, and a conductive paste is filled in the through-hole by printing using the PET film as a printing mask. A filled via hole of 150 μmφ is formed.
【００５７】ＰＥＴフィルムを接着剤層から剥離した
後、厚さ１２μｍの銅箔を、加熱温度１８０℃、加熱時
間７０分、圧力２ＭＰａ、真空度２．５×１０３Ｐａの
条件のもとで、接着剤層上に加熱プレスする。 その後、基板両面の銅箔に適切なエッチング処理を施
して、導体回路およびビアランドを形成して、コア用両
面回路基板を作製した。After the PET film was peeled off from the adhesive layer, a copper foil having a thickness of 12 μm was subjected to a heating temperature of 180 ° C., a heating time of 70 minutes, a pressure of 2 MPa and a degree of vacuum of 2.5 × 10 3 Pa. And hot pressing on the adhesive layer. Thereafter, the copper foil on both sides of the substrate was subjected to an appropriate etching treatment to form a conductor circuit and a via land, thereby producing a double-sided circuit board for a core.
【００５８】上記実施例１、実施例２および比較例１に
よって製造された両面回路基板について、非貫通孔内に
残留する樹脂残滓の程度とボイドレスの程度をＸ線顕微
鏡（ＥＶ−１１００ＰＣ２：ユニハイト製）によって調
べた。その結果、実施例１および実施例２においては、
樹脂残滓はほとんど見当たらず、また５００，０００個
のビアホール中のボイド数は０であったが、比較例１に
おいては、若干の樹脂残滓が見受けられ、１０，０００
個のビアホール中のボイド数は５であった。With respect to the double-sided circuit boards manufactured in Example 1, Example 2 and Comparative Example 1, the degree of resin residue and the degree of voidless remaining in the non-through hole were measured with an X-ray microscope (EV-1100PC2: manufactured by Uniheight). ). As a result, in Example 1 and Example 2,
Almost no resin residue was found, and the number of voids in the 500,000 via holes was 0. In Comparative Example 1, however, some resin residue was found and 10,000.
The number of voids in each of the via holes was 5.
【００５９】[0059]
【発明の効果】以上説明したように、本発明によれば、
両面回路基板と片面回路基板とを一部共通な製造工程を
経て製造できるので、製造コストの低減を図ることがで
き、また、一面に銅箔が貼付けられた絶縁性基材に設け
た非貫通孔内に、真空加圧脱泡によって導電性ペースト
を充填するので、導電性ペーストへの気泡の残留を極力
抑えることができ、層間接続抵抗の安定化を図ることが
できる。As described above, according to the present invention,
Since the double-sided circuit board and the single-sided circuit board can be manufactured through a common manufacturing process, the manufacturing cost can be reduced, and a non-penetrating board provided on an insulating substrate having copper foil adhered to one side Since the conductive paste is filled in the holes by vacuum pressure defoaming, bubbles can be suppressed from remaining in the conductive paste as much as possible, and the interlayer connection resistance can be stabilized.
【図1】本発明の多層プリント配線板用両面回路基板の
製造工程の一部を示す図。FIG. 1 is a diagram showing a part of a manufacturing process of a double-sided circuit board for a multilayer printed wiring board of the present invention.
【図２】本発明の両面回路基板に積層される回路基板の
製造工程の一部を示す図。FIG. 2 is a view showing a part of a manufacturing process of a circuit board to be laminated on the double-sided circuit board of the present invention.
【図３】本発明による両面回路基板と片面回路基板とを
積層した４層配線板を示す図。FIG. 3 is a diagram showing a four-layer wiring board in which a double-sided circuit board and a single-sided circuit board according to the present invention are stacked.
１０ 絶縁性基材 １２ 銅箔 １４ 樹脂接着剤 １６ ＰＥＴフィルム １８ 非貫通孔 ２０ 導電性ペースト ２２ 充填ビアホール ２４ 銅箔 ２６、２８ 導体回路 ３０ コア用両面回路基板 ３４ 導体回路 ３６ 突起状導体 ３８ 樹脂接着剤 ４０、４２、４４ 積層用片面回路基板 DESCRIPTION OF SYMBOLS 10 Insulating base material 12 Copper foil 14 Resin adhesive 16 PET film 18 Non-through hole 20 Conductive paste 22 Filled via hole 24 Copper foil 26, 28 Conductor circuit 30 Double-sided circuit board for core 34 Conductor circuit 36 Projecting conductor 38 Resin adhesion Agents 40, 42, 44 Single-sided circuit board for lamination
Claims (2)
し、この絶縁性基材中に前記導体回路間を電気的に接続
するビアホールが形成された多層プリント配線板用回路
基板を製造するに当たって、その製造工程中に、少なく
とも以下の（１）〜（４）の工程、すなわち、（１）一
面に銅箔が貼付けられた絶縁性基材の他の面に、樹脂フ
ィルムを貼付け、その樹脂フィルム上からレーザ照射を
行って前記銅箔に達する非貫通孔を形成する工程、
（２）前記非貫通孔内に導電性ペースト充填しながら、
あるいは充填した後、前記絶縁性基材を減圧条件下にお
いて、前記導電性ペーストを加圧する工程、（３）前記
樹脂フィルムを絶縁性基材の表面から剥離させたのち、
前記絶縁性基材の他の面から露出した導電性ペーストを
半硬化させ、そのペーストを含んだ絶縁性基材の表面
に、半硬化状態の樹脂接着剤層を形成し、その樹脂接着
剤層を介して銅箔を加熱圧着して、前記導電性ペースト
と銅箔とを電気的に接続させる工程、（４）前記絶縁性
基材に貼付けられた銅箔をエッチングして、絶縁性基材
の両面に導体回路を形成する工程、とを含むことを特徴
とする多層プリント配線板用回路基板の製造方法。1. A circuit board for a multilayer printed wiring board having a conductor circuit on both surfaces of a hard insulating base material and having via holes formed in the insulating base material to electrically connect the conductive circuits. In the manufacturing process, at least the following steps (1) to (4) are performed during the manufacturing process, that is, (1) a resin film is attached to the other surface of the insulating substrate having copper foil attached to one surface. Forming a non-through hole reaching the copper foil by irradiating laser from above the resin film,
(2) While filling the non-through hole with a conductive paste,
Or after filling, a step of pressing the conductive paste under a reduced pressure condition of the insulating base, (3) after the resin film is peeled off from the surface of the insulating base,
The conductive paste exposed from the other surface of the insulating substrate is semi-cured, and a semi-cured resin adhesive layer is formed on the surface of the insulating substrate containing the paste, and the resin adhesive layer is formed. Heat-compressing the copper foil through the above to electrically connect the conductive paste and the copper foil, (4) etching the copper foil attached to the insulating base material, Forming a conductive circuit on both sides of the circuit board.
し、この絶縁性基材中に前記導体回路に達する充填ビア
ホールが形成された多層プリント配線板用回路基板を製
造するに当たって、その製造工程中に、少なくとも以下
の（１）〜（３）の工程、すなわち、（１） 一面に銅
箔が貼付けられた絶縁性基材にエッチング処理を施して
導体回路を形成する工程、（２） 前記記絶縁性基材の
他の面に、樹脂フィルムを貼付け、その樹脂フィルム上
からレーザ照射を行って前記導体回路に達する非貫通孔
を形成する工程、（３） 前記非貫通孔内に導電性ペー
スト充填しながら、あるいは充填した後、前記絶縁性基
材を減圧条件下において前記導電性ペーストを加圧し
て、前記銅箔との電気的接続を行なう充填ビアホールを
形成する工程、とを含むことを特徴とする多層プリント
配線板用回路基板の製造方法。In manufacturing a circuit board for a multilayer printed wiring board having a conductive circuit on one surface of a hard insulating base material and having a filled via hole reaching the conductive circuit in the insulating base material, During the manufacturing process, at least the following processes (1) to (3), namely, (1) a process of forming a conductor circuit by performing an etching process on an insulating base material having a copper foil adhered to one surface thereof, 2) a step of attaching a resin film to the other surface of the insulating base material and irradiating the resin film with a laser to form a non-through hole reaching the conductor circuit; (3) inside the non-through hole While filling the conductive paste, or after filling, pressurizing the conductive paste under a reduced pressure condition of the insulating substrate, forming a filled via hole for making an electrical connection with the copper foil, Including Method of manufacturing a circuit board for a multilayer printed wiring board according to claim.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000018171A JP4545865B2 (en) | 1999-12-08 | 2000-01-27 | Method for manufacturing circuit board for multilayer printed wiring board |
| PCT/JP2000/004612 WO2001005204A1 (en) | 1999-07-12 | 2000-07-10 | Method of manufacturing printed-circuit board |
| US10/030,428 US6889433B1 (en) | 1999-07-12 | 2000-07-10 | Method of manufacturing printed-circuit board |
| DE60030743T DE60030743T2 (en) | 1999-07-12 | 2000-07-10 | Method for producing a printed circuit board |
| EP00944386A EP1220588B1 (en) | 1999-07-12 | 2000-07-10 | Method of manufacturing printed-circuit board |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11-348410 | 1999-12-08 | ||
| JP34841099 | 1999-12-08 | ||
| JP2000018171A JP4545865B2 (en) | 1999-12-08 | 2000-01-27 | Method for manufacturing circuit board for multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001230549A true JP2001230549A (en) | 2001-08-24 |
| JP4545865B2 JP4545865B2 (en) | 2010-09-15 |
Family
ID=26578742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000018171A Expired - Fee Related JP4545865B2 (en) | 1999-07-12 | 2000-01-27 | Method for manufacturing circuit board for multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4545865B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109429420A (en) * | 2017-08-22 | 2019-03-05 | 宏启胜精密电子(秦皇岛)有限公司 | Circuit board and preparation method thereof with electro-magnetic screen function |
| CN113498633A (en) * | 2020-01-21 | 2021-10-12 | 鹏鼎控股(深圳)股份有限公司 | Circuit board with embedded electronic element and manufacturing method |
| CN119730056A (en) * | 2024-12-04 | 2025-03-28 | 北京梦之墨科技有限公司 | Double-sided circuit board and manufacturing method thereof |
| CN119730079A (en) * | 2024-12-04 | 2025-03-28 | 北京梦之墨科技有限公司 | Multilayer circuit board and manufacturing method thereof |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0559288U (en) * | 1992-01-20 | 1993-08-06 | 株式会社東洋精機製作所 | Vacuum defoaming device |
| JPH07170046A (en) * | 1993-09-22 | 1995-07-04 | Matsushita Electric Ind Co Ltd | Printed wiring board and manufacturing method thereof |
| JPH08337920A (en) * | 1995-06-09 | 1996-12-24 | Sumitomo Chem Co Ltd | Para-aramid pulp and method for producing the same |
| JPH0936551A (en) * | 1995-05-15 | 1997-02-07 | Ibiden Co Ltd | Single-sided circuit board for multilayer printed wiring board use, multilayer printed wiring board and manufacture thereof |
| JPH09162517A (en) * | 1995-12-12 | 1997-06-20 | Yamaichi Electron Co Ltd | Circuit board |
| JPH10117068A (en) * | 1996-10-14 | 1998-05-06 | Cmk Corp | Conductive sheet and method for manufacturing multilayer printed wiring board using the conductive sheet |
| JPH118471A (en) * | 1997-06-18 | 1999-01-12 | Hitachi Ltd | Method for manufacturing multilayer wiring board, and method for mounting electronic component using multilayer wiring board |
| JPH1117300A (en) * | 1996-12-26 | 1999-01-22 | Matsushita Electric Ind Co Ltd | Wiring board, circuit component package, electronic component package, method of manufacturing wiring board, and method of manufacturing electronic component package |
| JPH11204942A (en) * | 1998-01-12 | 1999-07-30 | Hitachi Chem Co Ltd | Manufacture of multilayer wiring board |
| JPH11298106A (en) * | 1998-04-07 | 1999-10-29 | Asahi Chem Ind Co Ltd | Via hole filling type of both-sided printed wiring board and its manufacture |
-
2000
- 2000-01-27 JP JP2000018171A patent/JP4545865B2/en not_active Expired - Fee Related
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0559288U (en) * | 1992-01-20 | 1993-08-06 | 株式会社東洋精機製作所 | Vacuum defoaming device |
| JPH07170046A (en) * | 1993-09-22 | 1995-07-04 | Matsushita Electric Ind Co Ltd | Printed wiring board and manufacturing method thereof |
| JPH0936551A (en) * | 1995-05-15 | 1997-02-07 | Ibiden Co Ltd | Single-sided circuit board for multilayer printed wiring board use, multilayer printed wiring board and manufacture thereof |
| JPH08337920A (en) * | 1995-06-09 | 1996-12-24 | Sumitomo Chem Co Ltd | Para-aramid pulp and method for producing the same |
| JPH09162517A (en) * | 1995-12-12 | 1997-06-20 | Yamaichi Electron Co Ltd | Circuit board |
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