JP2001224045A - Video signal conversion device and video signal conversion method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To suppress a signal line for transmitting a video signal to a display unit. SOLUTION: A pixel counter 104 has a horizontal synchronization signal H.
The pixel number is counted using the DN and the clock signal VCK multiplied by the multiplier 109. Buffer 10
6 represents two components C from the luminance signal Y and the color difference signal C.
b, Cr are separated. The calculation unit 107 converts the two components Cb and Cr separated from the luminance signal Y and the color difference signal C into R, G, and B signals. The multiplexer 108
The pixel division count value from the pixel division counter 110 and the clock signal VC multiplied by the multiplier 109
Using K, the R, G, and B signals from the operation unit 107 are time-division multiplexed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for converting a video signal including a luminance signal Y and color difference signals Cb and Cr into R (red) and G (green) signals.
And a video signal converter for converting the image signals into three primary color signal formats of B (blue).

[0002]

2. Description of the Related Art A conventional video display device will be described with reference to FIG. FIG. 15 is a block diagram showing a configuration of a video display device provided with a conventional video signal converter. Generally, ITU-TH. In moving image compression methods such as H.261 and MPEG, CIF (Common Intermediate Format)
And QCIF (Quarter CIF). Here, the image format is CIF 4: 2: 2.
(Effective display area 352 pixels × 288 scanning lines) will be described as an example.

[0003] The video decoder 1 outputs a video signal in YCbCr format. The video signals in the YCbCr format include a luminance signal Y, a color difference signal C obtained by time-division multiplexing two color difference signals Cb and Cr, a vertical synchronization signal VDN,
This is a video signal including a horizontal synchronization signal HDN and a clock signal VCK for transferring video data.

On the other hand, a display unit 8 for displaying an image is
Drive signal converter 9 for performing signal level conversion processing and LC
D and the like. This display unit 8
Generally, video signals in RGB format are received via the interface 11. An RGB format video signal is a light 3
This is a video signal including primary color signals, that is, R (red), G (green), and B (blue) signals.

As described above, since the video signal format of the signal output by the video decoder 1 and the video signal format of the signal input by the display unit 1 are different, YCbCr
It is necessary to convert a video signal of a format into a video signal of an RGB format. Therefore, in a conventional moving image display device, a video signal converter 2 that converts a YCbCr format video signal into an RGB format video signal is provided between the video composite device 1 and the display unit 1. Hereinafter, the video signal converter 2
Will be described.

[0006] The video signal converter 2 is provided with a horizontal synchronizing signal HDN.
And a pixel counter 4 that counts a pixel number using the clock signal VCK, and counts the number of scanning lines using the vertical synchronization signal VDN, the clock signal VCK, and the pixel number (pixel count value) counted by the pixel counter 4. A scanning line counter 3; a driving signal generator 5 for generating a driving signal for the driving signal converter 9 using the pixel count value and the number of scanning lines (scanning line count value) counted by the scanning line counter 3; Using the signal Y and the color difference signal C, two components Cb,
A buffer 6 for separating Cr, and two components Cb and Cr and a luminance signal Y separated from the color difference signal C are converted to R, G, and B.
And an operation unit 7 for converting the signal into a signal.

The operation of the video signal converter 2 having the above configuration will be described with reference to FIG. 16 in addition to FIG.
FIG. 16 is a timing chart showing the operation of the video signal converter 2 in the conventional video display device.

First, the moving picture decoder 1 supplies a vertical synchronizing signal VDN, a horizontal synchronizing signal HDN, and a luminance signal Y (8 bits) to the video signal converter 2 in synchronization with the falling edge of the clock signal VCK. , And two color difference signals Cb,
It outputs a color difference signal C (8 bits) in which Cr is time-division multiplexed.

When the pixel counter 4 detects the falling edge of the horizontal synchronizing signal HDN, the pixel count value (PXL_NO) from 0 to 499 is supplied to the scanning line counter 3 and the driving signal at each falling edge of the clock signal VCK. Output to the generator 5 and the buffer 6.

The scanning line counter 3 outputs a vertical synchronizing signal VDN.
Using the logical state of the pixel count value (PXL_NO) and the pixel count value (PXL_NO), every time the pixel count value (PXL_NO) reaches 499, it advances in synchronization with the falling edge of the clock signal VCK, and the scan line count value (0 to 299) LINE_N
O) is output to the drive signal generator 5.

The drive signal generator 5 outputs a scan line count value (LINE_NO) and a pixel count value (PXL_N).
O), a vertical start pulse signal STV, a horizontal start pulse signal STH, and R, G, B
A drive signal such as a clock signal DOTCLK indicating a signal break is output.

On the other hand, a luminance signal Y and a color difference signal C from the video decoder 1 are input to the buffer 6. The buffer 6 performs a delay process on the luminance signal Y to output a luminance signal Y ′ (8 bits) to the arithmetic unit 7, and performs a separation process on the color difference signal C to generate two components. Cb and Cr (each 8 bits) are output to the arithmetic unit 7.

The arithmetic unit 7 converts the luminance signal Y 'output from the buffer 6 and the two color difference signals Cb and Cr into R,
The signals are converted into G and B signals and output. Assume that the R, G, and B signals are, for example, 6-bit signals.

The RGB format video signal output from the video signal converter 2 described above is sent to the display unit 8 via the interface 11. The display unit 8 receives the RGB received via the interface 11.
An image can be projected using a video signal of a format. That is, in the display unit 8, the drive signal converter 9 performs a predetermined process such as a signal level conversion process on the RGB video signal, and the display unit 10 such as an LCD
An image is projected using the RGB signals after the above-described predetermined processing. Note that the signal level conversion process in the drive signal converter 9 corresponds to a process for expanding a video signal in the RGB format or the like so that a signal level appropriate for the display unit 10 is obtained.

A manufacturer such as an LCD generally provides the display unit 8 as a module or a unit. In addition, a communication terminal device such as a portable TV phone or a portable information terminal is often equipped with a cable, a flexible board, or the like as the interface 11.

[0016]

However, the conventional video display apparatus has the following problems. That is, the RG output by the video signal converter 2
Since the R, G, and B signals in the B format video signal have an information amount of a plurality of bits (6 bits in the above example) per unit time, a signal line for transmitting the R, G, and B signals is used. The total number increases. More specifically, in the above example, six signal lines are required to transmit the R, G, and B signals. As described above, since the RGB format video signals include various drive signals in addition to the R, G, and B signals, the total number of signal lines for transmitting all the RGB format video signals is further increased. Become.

For this reason, as the interface unit 11,
In order to handle the RGB format video signal output from the video signal converter 2, it is necessary to use a connection cable or a flexible board having a large shape.

As a result, in the communication terminal device equipped with the interface unit 11, the size and shape of the connection cable, the flexible substrate, and the like become obstacles in downsizing the device body.

As a countermeasure against such a problem, a method in which the video signal converter 2 is equipped with a D / A converter, and converts each of the R, G, and B signals into an analog signal and outputs the analog signal. According to this method, the number of signal lines for transmitting each of the R, G, and B signals can be reduced to one, but noise is easily mixed into the R, G, and B signals.
A new problem such as deterioration of video quality occurs.

The present invention has been made in view of the above points, and provides a video signal converter that suppresses a signal line for transmitting a video signal to a display unit without deteriorating video quality. The purpose is to:

[0021]

A video signal conversion apparatus according to the present invention comprises: a conversion means for converting a YCbCr format video signal into an RGB format video signal; and a time division device for converting at least two of the RGB format video signals. Multiplexing means for generating one video signal by multiplexing, and displaying a video as a new RGB video signal using the RGB video signal other than the time-division multiplexed signal and the one video signal. Output means capable of outputting to the display means.

The video signal converter of the present invention employs a configuration in which the multiplexing means time-division multiplexes at least two video signals in the above configuration.

According to these configurations, a plurality of video signals are time-division multiplexed and converted into one video signal,
The number of signal lines required to transmit RGB format video signals can be reduced without converting the plurality of video signals into analog signals. Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

In the video signal conversion device of the present invention, in the above configuration, the conversion means generates a control signal, and the multiplexing means includes
A configuration is employed in which the generated control signal and the video signal are time-division multiplexed.

According to this configuration, a plurality of video signals are time-division multiplexed and converted into one video signal, so that the plurality of video signals are not converted into analog signals, but are converted into analog signals.
The number of signal lines required for transmitting a video signal in the GB format can be reduced. In addition, by time-division multiplexing not only a plurality of video signals but also a control signal together with the video signals, the number of signal lines required for transmitting RGB format video signals can be further reduced.

In the video signal conversion device of the present invention, in the above-mentioned configuration, the multiplexing means performs a bit inversion process on the signal to be time-division multiplexed based on the information of the control signal, and the output means converts the control signal. A configuration is adopted in which the video signal is excluded from a new RGB format video signal.

According to this configuration, the plurality of video signals are time-division multiplexed and converted into one video signal, so that the plurality of video signals are not converted into analog signals, and are converted into R signals.
The number of signal lines required for transmitting a video signal in the GB format can be reduced. In addition, by performing bit inversion processing on at least one of a plurality of video signals, it is not necessary to transmit a control signal alone. Signal lines necessary for the operation can be further reduced.

The video signal conversion device of the present invention employs a configuration in the above configuration, which includes a control unit for controlling the conversion unit, the multiplexing unit, and the output unit based on a request from the display unit.

According to this configuration, it is possible to reliably output the RGB format video signal corresponding to the request from the display unit to the display unit.

The video signal conversion device according to the present invention has a YCbCr
Converting means for converting a video signal of a video format into a video signal of an RGB format including a video signal having a predetermined transmission rate;
Changing means for changing the transmission speed of at least one video signal in the video signal of the GB format, and converting the video signal of the RGB format other than the video signal whose transmission speed has been changed and the video signal whose transmission speed has been changed into a new Output means capable of outputting the image signal as an RGB image signal to a display means for displaying an image.

According to this configuration, since the transmission speed of at least one of the plurality of video signals is changed, the plurality of video signals are not converted into analog signals without being converted.
It is possible to reduce the number of signal lines required for transmitting the RGB format video signal. Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

[0032] In the video signal conversion apparatus of the present invention, in the above configuration, the conversion means generates a control signal having the same transmission speed as the transmission rate of the video signal after the change by the changing means, Is configured to time-division multiplex the changed video signal and the generated control signal.

According to this configuration, since the transmission speed is changed for at least one of the plurality of video signals, the RGB format video signal can be transmitted without converting the plurality of video signals into analog signals. The required number of signal lines can be reduced. Further, by inserting a signal indicating a pixel break into a video signal whose transmission speed has been changed, the number of necessary signal lines can be further reduced. Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

[0034] In the video signal conversion device of the present invention, in the above configuration, the conversion means performs bit inversion processing on the video signal whose transmission speed has been changed based on the information of the control signal, and the output means includes A configuration is adopted in which the control signal is excluded from the new RGB format video signal.

According to this configuration, since the transmission speed of at least one of the plurality of video signals is changed, the RGB format video signal can be transmitted without converting the plurality of video signals into analog signals. The required number of signal lines can be reduced. In addition, by performing bit inversion processing on the video signal whose transmission speed has been changed, the control signal can be transmitted with the video signal whose transmission speed has been changed, so that the required number of signal lines can be further reduced. .

The video signal conversion device of the present invention has a configuration in which the above-mentioned configuration is provided with control means for controlling the conversion means, the change means and the output means based on the request of the display means.

According to this configuration, it is possible to reliably output the RGB format video signal corresponding to the request from the display unit to the display unit.

A communication terminal device according to the present invention employs a configuration provided with any one of the video signal conversion devices described above.

According to this configuration, the apparatus main body is provided with the video signal conversion device capable of suppressing the signal line for transmitting the video signal to the display unit without deteriorating the quality of the video. It is possible to provide a communication terminal device capable of reducing the size of the communication terminal.

The video signal conversion method of the present invention uses the YCbCr
Converting a video signal of the RGB format into a video signal of the RGB format, time-multiplexing at least two signals in the video signal of the RGB format to generate one video signal, and time-division multiplexing. And outputting the RGB video signal other than the output signal and the one video signal as a new RGB video signal to a display unit that displays a video. I made it.

According to this method, a plurality of video signals are time-division multiplexed and converted into a single video signal.
The number of signal lines required for transmitting a video signal in the GB format can be reduced. Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

The video signal conversion method according to the present invention uses the YCbCr
Converting a video signal of a video format into a video signal of an RGB format including a video signal having a predetermined transmission rate;
A changing step of changing the transmission speed of at least one video signal in the video signal of the GB format, and a video signal of the RGB format other than the video signal whose transmission speed has been changed and the video signal having the changed transmission speed, An output step of outputting an RGB format video signal to display means for displaying a video.

According to this method, since the transmission speed of at least one of the plurality of video signals is changed, the plurality of video signals are not converted into analog signals without being converted.
It is possible to reduce the number of signal lines required for transmitting the RGB format video signal. Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present inventors first focused on time-division multiplexing of a plurality of video signals, and time-division-multiplexed a plurality of video signals having the same transmission rate to form one video. The present invention has been found that the number of signal lines required for transmitting a plurality of video signals can be reduced by converting the signal lines into signals. Second, the present inventors focused on the fact that the number of signal lines required to transmit a video signal changes according to the transmission speed of the video signal, and by reducing the transmission speed of the video signal, The present inventors have found that the number of signal lines required for transmitting a video signal can be reduced, and have arrived at the present invention.

The first gist of the present invention is to time-division multiplex a plurality of video signals having the same transmission rate. A second gist of the present invention is to change the transmission speed of a video signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiment, an example will be described in which the image format is CIF 4: 2: 2 (effective display area 352 pixels × 288 scanning lines).

The first to fourth embodiments convert a plurality of video signals into one video signal by time division multiplexing, and the fifth to eighth embodiments use a plurality of video signals. Is to change the amount of information per unit time (that is, transmission speed).

(Embodiment 1) In this embodiment, a case will be described in which a plurality of video signals are time-division multiplexed and converted into one video signal. FIG. 1 shows Embodiment 1 of the present invention.
1 is a block diagram illustrating a configuration of a video display device including the video signal converter according to the first embodiment.

Referring to FIG. 1, a moving picture decoder 101
Outputs a video signal in YCbCr format to the video signal converter 102 according to the present embodiment. The video signal converter 102 converts the video signal in YCbCr format from the video decoder 101 into a video signal in RGB format. The display unit 112 receives an RGB format video signal from the video signal converter 102 via the interface 111 and displays a video.

The video signal converter 10 according to the present embodiment
2, the pixel counter 104 outputs the horizontal synchronization signal HD
The pixel number is counted using N and the clock signal VCK. The scanning line counter 103 counts the number of scanning lines using the vertical synchronization signal VDN, the clock signal VCK, and the pixel number (pixel count value) counted by the pixel counter 104.

The drive signal generator 105 uses the pixel count value and the number of scanning lines counted by the scanning line counter 103 (scanning line count value) to display the display unit 11.
2 for generating a drive signal. The buffer 106 performs a delay process on the luminance signal Y and separates two components Cb and Cr from the color difference signal C. The calculation unit 107 converts the two components Cb and Cr separated from the luminance signal Y and the color difference signal C into R, G, and B signals.

The multiplier 109 multiplies the frequency of the clock signal VCK by three times. The pixel division counter 110 uses the pixel count value and the multiplied clock signal VCK to generate a pixel division count value and a determination signal MKR indicating a pixel division. The multiplexer 108 uses the pixel division count value and the multiplied clock signal VCK to time-division multiplex the R, G, and B signals from the operation unit 107.

On the other hand, in the display unit 112, the drive signal converter 113 performs predetermined processing such as separation processing and signal level conversion processing on the RGB format video signal received via the interface 111. . The display unit 114 displays an image using the image signal on which the above-described predetermined processing has been performed.

Next, the operation of the video signal converter 102 having the above configuration will be described with reference to FIG. FIG. 2 is a timing chart showing an operation of the video signal converter 102 according to the first embodiment of the present invention.

First, the video decoder 101 instructs the video signal converter 102 to synchronize the vertical synchronizing signal VDN and the horizontal synchronizing signal H in synchronization with the falling edge of the clock signal VCK.
It outputs a color difference signal C (8 bits) in which the DN, the luminance signal Y (8 bits), and the two color difference signals Cb and Cr are time-division multiplexed. In FIG. 2, the vertical synchronization signal V
When the DN and the horizontal synchronizing signal HDN are at “0” level, the vertical blanking period (for 12 scanning lines) respectively
And a horizontal blanking period (for 148 pixels). In each blanking period, the luminance signal Y
The color difference signal C has a black level value.

The pixel counter 104 outputs the horizontal synchronizing signal HD
When the falling edge of N is detected, the clock signal VCK
The pixel count value (PXL_NO) from 0 to 499 is output to the scanning line counter 103, the drive signal generator 105, the buffer 106, and the pixel division counter 110 at each falling edge of.

The scanning line counter 103 outputs the vertical synchronizing signal V
Using the logical state of DN and the pixel count value (PXL_NO), every time the pixel count value (PXL_NO) reaches 499, it advances in synchronization with the falling edge of the clock signal VCK, and the scan line count value of 0 to 299 (LINE_N
O) to the drive signal generator 105.

The drive signal generator 105 outputs a scan line count value (LINE_NO) and a pixel count value (PXL_
NO), drive signals such as a vertical start pulse signal STV and a horizontal start pulse signal STH are output.

On the other hand, the luminance signal Y and the color difference signal C from the video decoder 101 are input to the buffer 106. The buffer 106 outputs a luminance signal Y ′ (8 bits) to the arithmetic unit 7 by performing a delay process on the luminance signal Y, and performs a separation process on the chrominance signal C to perform two processes. Cb and Cr (each 8 bits) are output to the operation unit 107. In FIG. 2, as an example, the color difference signals Cb and Cr of the odd-numbered pixels are shown.
Is obtained by diverting Cb and Cr of the even-numbered pixel one pixel before.

The arithmetic unit 107 converts the luminance signal Y ′ and the two color difference signals Cb and Cr output from the buffer 106 into R, G and B signals using the following equation, and outputs the signals. Assume that the R, G, and B signals are, for example, 6-bit signals. R = Y + 1.402 × Cr G = Y−0.344 × Cb−0.714 × Cr B = Y + 1.722 × Cb In the above calculation, input / output dynamic range adjustment / normalization, offset, and calculation result It is also possible to perform a clip process or the like for overflow / underflow.

The multiplier 109 multiplies the clock signal VCK so that the frequency is tripled by adjusting the phase to the falling edge of the clock signal VCK. The clock signal VCK multiplied by three (hereinafter referred to as “triple clock signal (VC
K × 3) ”. ) Is output to the pixel division counter 110 and the multiplexer 108.

The pixel division counter 110 outputs the pixel count value (PXL_NO) and the triple clock signal (VCK ×
By using 3), 0 to 2 are counted within one pixel interval to generate a pixel division count value and a determination signal MKR indicating a pixel segment. The pixel division count value is output to the multiplexer 108.

The multiplexer 108 sequentially takes out one of the R, G, and B signals from the arithmetic unit 107 at each falling edge of the triple clock signal (VCK × 3) based on the pixel division count value, and By performing time division multiplexing within a considerable time interval, a 6-bit RGB signal is generated. As a result, a 6-bit R signal (“R5-0” in FIG. 2), a G signal (“G5-0” in FIG. 2), and a B signal (“B5-0” in FIG. ") Indicates that the R signal, the G signal and the B signal are 1
It is converted into a 6-bit RGB signal (“RGB5-0” in FIG. 2) sequentially multiplexed in the pixel.

As described above, the video signal in the RGB format is sent to the display unit 112 via the interface 111 by the video signal converter 102. The RGB format video signal is a signal including an RGB signal and a control signal. Here, the control signal is a drive signal such as a vertical direction start pulse signal STV, a horizontal direction start pulse signal STH, a triple clock signal (VCK × 3), and a discrimination signal M.
KR is included.

On the other hand, the display unit 112 can display an image using an RGB format image signal received via the interface 111. Specifically, in the display unit 112, the drive signal converter 113
Triple clock signal (VCK × 3) and discrimination signal MKR
Is used to separate the R, G, and B signals from the RGB signals. Further, the drive signal converter 113 outputs the separated R signal, G signal and B signal, and other R signals.
The video signal in the GB format is expanded so as to have a signal level appropriate for the display unit 114. The display unit 114 displays an image using an extended RGB format image signal.

According to the video signal converter 102 as described above, the R signal and the G signal having the information amount of 6 bits per unit time are provided.
A signal and a B signal (that is, an R signal, a G signal, and a B signal having a transmission rate of 6 bits) are time-division multiplexed to provide an RG having an information amount of 6 bits per unit time.
Converted to B signal. Thus, in the conventional method, R
The number of signal lines required for transmitting the signal, the G signal, and the B signal is 18, but in the present embodiment, the R signal,
Since the number of signal lines necessary for transmitting the G signal and the B signal is six, twelve signal lines can be reduced as compared with the conventional system.

Further, in the conventional system, the number of signal lines for transmitting the RGB format video signal is as follows: a vertical start pulse signal STV (one), a horizontal start pulse signal STH (one), and a clock signal DOTCLK. (1
, R signal (six), G signal (six), and B signal (six), for a total of 21 lines. In the present embodiment, the vertical direction start pulse signal STV (one line), the horizontal direction The start pulse signal STH (one signal) and the discrimination signal MKR (1
Book), triple clock signal (1), RGB signal (6)
Is 10 in total. That is, in the present embodiment, eleven signal lines can be reduced as compared with the conventional method.

As described above, according to the video signal converter according to the present embodiment, a plurality of video signals are
By converting the video signals into one video signal, the number of signal lines required to transmit the RGB format video signal can be suppressed without converting the plurality of video signals into analog signals. Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

In the present embodiment, the R signal,
The case where these video signals are time-division multiplexed regularly in the order of the G signal and the B signal has been described as an example.
The present invention is not limited to this, and can be applied to a case where the order of video signals to be time-division multiplexed is appropriately changed as long as the drive signal converter 113 of the display unit 112 can accurately separate each video signal. is there.

Also, in the present embodiment, an example has been described in which the video signals of all the R, G, and B signals are time-division multiplexed one by one within a time interval corresponding to one pixel. The case where the number of video signals to be time-division multiplexed is appropriately changed within a time interval corresponding to one pixel within a range where the drive signal converter 113 of the display unit 112 can accurately separate each video signal is not limited to this. Is also applicable.

Further, in the present embodiment, a case has been described where a total of three video signals of R, G and B signals are time-division multiplexed and converted into one video signal. However, the present invention is not limited to this, and can be applied to a case where only any two of the three video signals are time-division multiplexed and converted into one video signal. In this case, the multiplier 109 may multiply the clock signal VCK by twice.

(Embodiment 2) In this embodiment, a case will be described in Embodiment 1 where a control signal in addition to a plurality of video signals is time-division multiplexed and converted into one video signal. Hereinafter, the video signal converter according to the present embodiment will be described with reference to FIG. FIG. 3 is a block diagram illustrating a configuration of a video display device including the video signal converter according to the second embodiment of the present invention. In addition, about the structure similar to Embodiment 1 (FIG. 1) in FIG. 3, FIG.
Are given the same reference numerals as in, and detailed description is omitted. In the present embodiment, a case where a signal indicating a pixel break is used as a control signal will be described as an example.

Referring to FIG. 3, a video signal converter 301 according to the present embodiment includes a multiplier 302 for multiplying the frequency of the clock signal VCK by four times, and a pixel count value and the multiplied clock signal VCK. Using the pixel division counter 303 for generating the pixel division count value, and the pixel division count value and the multiplied clock signal VCK, the time division multiplexing of the R, G, B signals and the discrimination signal MKR from the arithmetic unit 107. A multiplexer 304,
It has.

The operation of the video signal converter 301 having the above configuration will be further described with reference to FIG. FIG.
FIG. 9 is a timing chart showing an operation of the video signal converter according to the second embodiment of the present invention.

The multiplier 302 multiplies the clock signal VCK so that the frequency is quadrupled by adjusting the phase to the falling edge of the clock signal VCK. A clock signal multiplied by four (hereinafter referred to as a “quadruple clock signal (VCK ×
4). Are output to the pixel division counter 303 and the multiplexer 304.

The pixel division counter 303 outputs the pixel count value (PXL_NO) and the quadrupled clock signal (VCK ×
By using 4), 0 to 3 are counted within one pixel interval to generate a pixel division count value. The pixel division count value is output to the multiplexer 304.

The multiplexer 304 outputs any one of the R, G, B signals and the discrimination code MKR from the arithmetic unit 107 at each falling edge of the quadrupled clock signal (VCK × 4) based on the pixel division count value. A 6-bit RGB 'signal is generated by sequentially taking out and time-division multiplexing within a time interval corresponding to one pixel.

The discrimination code MKR has the same information amount (here, 6 bits) per unit time as the R signal, G signal and B signal. That is, the transmission speed of the discrimination code MKR is the same as the transmission speed of the R signal, the G signal, and the B signal. For example, the discrimination code MKR is “11010”
In the vertical blanking period and the horizontal blanking period, since the R, G, and B signals are at the black level, that is, "000000", the MSB becomes "1". Is desirably set to the discrimination code MKR.

As a result, a 6-bit R signal (“R5-0” in FIG. 4), a G signal (“G5-0” in FIG. 4), and a B signal (“G5-0” in FIG. B5-
0 ") is an R signal, a G signal, a B signal
A 6-bit RGB ′ signal in which the signal and the discrimination code MKR are sequentially time-multiplexed within one pixel (“RGB′5-
0 ").

As described above, the video signal in the RGB format is sent to the display unit 305 via the interface 307 by the video signal converter 301. The RGB format video signal is a signal including an RGB ″ signal and a control signal. Here, the control signal includes a drive signal such as a vertical direction start pulse signal STV, a horizontal direction start pulse signal STH, and a quadruple clock signal (VCK × 4).

On the other hand, the display unit 305 can display an image using the RGB format image signal received via the interface 307. Specifically, in the display unit 305, the drive signal converter 306
During the vertical blanking period and the horizontal blanking period, the quadrupled clock signal (VCK × 4) and the discrimination code M
The KR is used to separate the R, G, and B signals from the RGB ′ signal. The drive signal converter 113 is the same as that of the first embodiment.
As described above, the separated R signal, G signal and B signal
Signal, and other RGB format video signals,
The display unit 114 is expanded so as to have an appropriate signal level. The display unit 114 displays an image using an extended RGB format image signal.

According to the video signal converter 301 as described above, the R signal and the G signal having the information amount of 6 bits per unit time are provided.
Discrimination code MKR indicating signal, B signal, and pixel break
Is converted into an RGB ′ signal having an information amount of 6 bits per unit time by time division multiplexing. Thus, in the first embodiment described above, the number of signal lines required to transmit the R signal, the G signal, the B signal, and the determination signal MKR indicating the pixel break is seven, but in the present embodiment, , R signal, G signal, B signal, and the number of signal lines required to transmit the discrimination code MKR indicating the pixel segment, the number of signal lines is six, so that one signal line is reduced compared to the first embodiment. be able to.

Further, the number of signal lines for transmitting the RGB format video signal is 21 in total in the conventional system as described above, but in the present embodiment, the vertical start pulse signal STV (1 line) is used in the present embodiment. ), Horizontal direction start pulse signal STH (1 line), 4 times clock signal (1 line), RG
A total of nine B 'signals (six) are provided. That is, in the present embodiment, the number of twelve signal lines can be reduced as compared with the conventional method.

As described above, according to the video signal converter according to the present embodiment, a plurality of video signals are
By converting the video signals into one video signal, the number of signal lines required for transmitting the RGB format video signal can be suppressed without converting the plurality of video signals into analog signals. In addition, by time-division multiplexing not only a plurality of video signals but also a signal indicating a pixel break together with the video signals, it is possible to further reduce the number of signal lines required for transmitting RGB format video signals.

In this embodiment, the R signal,
Although the case where these signals are time-division multiplexed in the order of the G signal, the B signal, and the discrimination code MKR has been described as an example, the present invention is not limited to this, and the drive signal converter 306 of the display unit 112 The present invention can be applied to a case where the order of signals to be time-division multiplexed is appropriately changed within a range in which the signals can be accurately separated.

In this embodiment, the R signal,
The case where a total of four signals of the G signal, the B signal and the discrimination code MKR are time-division multiplexed and converted into one signal has been described, but the present invention is not limited to this. This is also applicable to the case where only two or three of these signals are time-division multiplexed and converted into one signal. In this case, the multiplier 109 may multiply the clock signal VCK by two to three times in accordance with the number of signals to be multiplexed.

Further, in the present embodiment, a case where a signal indicating a pixel break is time-division multiplexed as one of the control signals has been described as an example. However, the present invention is not limited to this, and a signal indicating a pixel break is shown. The present invention is also applicable to a case where a control signal other than a signal is time-division multiplexed. In this case, the information amount of the other control signals per unit time may be made equal to the information amounts of the R, G, and B signals per unit time.

(Embodiment 3) In this embodiment, a case will be described in Embodiments 1 and 2 where the control signal is omitted from the RGB format video signal output to the display unit. Hereinafter, the video signal converter according to the present embodiment will be described with reference to FIG. FIG.
FIG. 9 is a block diagram illustrating a configuration of a video display device including a video signal converter according to a third embodiment of the present invention. In addition, about the structure similar to Embodiment 1 (FIG. 1) in FIG. 5, the same code | symbol as the thing in FIG. 1 is attached | subjected, and detailed description is abbreviate | omitted. Further, in the present embodiment, a case will be described as an example in which a signal indicating a pixel break is used as a control signal to be omitted from an RGB format video signal.

Referring to FIG. 5, the video signal converter 501 according to the present embodiment uses a triple clock signal (VCK ×
The R, G, and B signals from the arithmetic unit 107 are time-divided by using the pixel division counter 502 that generates the pixel division count value using (3), and the pixel division count value and the triple clock signal (VCK × 3). Multiplexer 503 to be multiplexed
And

The operation of the video signal converter 501 having the above configuration will be described with reference to FIG. FIG.
FIG. 9 is a timing chart showing an operation of the video signal converter according to the third embodiment of the present invention.

The pixel division counter 502 calculates the pixel count value (PXL_NO) and the triple clock signal (VCK ×
By using 3), 0 to 2 are counted within one pixel interval to generate a pixel division count value. The pixel division count value is output to the multiplexer 503.

The multiplexer 503 sequentially extracts the R, G, and B signals from the arithmetic unit 107 at each falling edge of the triple clock signal (VCK × 4) based on the pixel division count value, and obtains a time equivalent to one pixel. By performing time division multiplexing within the interval, a 6-bit RGB '' signal is generated. At this time, the multiplexer 503 performs bit inversion processing on, for example, the B signal of the R, G, and B signals to indicate a pixel break. That is, the B signal (for example, “110101”) from the arithmetic unit 107 is subjected to B ビ ッ ト (“0” by the bit inversion process in the multiplexer 503.
01010 ") and time-division multiplexed.

Thus, in the vertical blanking period and the horizontal blanking period, since the R, G, and B signals are all at the black level, that is, “000000”, the inverted B signal of the B signal is “111111”. Therefore, in the display unit 504 described later, in the vertical blanking period and the horizontal blanking period, based on whether the B signal in the RGB ″ signal is “111111” or not.
Pixel breaks can be recognized.

As a result, a 6-bit R signal (“R5-0” in FIG. 6), a G signal (“G5-0” in FIG. 6) and a B signal (“G5-0” in FIG. B5-
0 ") is an R signal, a G signal, a B signal
6-bit RG in which signals are sequentially time-multiplexed within one pixel
B '' signal ("RGB" 5-0 "in FIG. 6).

As described above, the video signal in RGB format is sent to the display unit 504 via the interface 506 by the video signal converter 501. The RGB video signal is a signal including an RGB ″ signal and a control signal. Here, the control signal includes a drive signal such as a vertical direction start pulse signal STV, a horizontal direction start pulse signal STH, and a triple clock signal (VCK × 3).

On the other hand, the display unit 504 can display an image using the RGB image signal received via the interface 506. Specifically, in the display unit 504, the drive signal converter 505
During the vertical blanking period and the horizontal blanking period, the RGB signal is converted to the R signal, the G signal, and the triple clock signal (VCK × 3) and the code “111111” indicating the pixel break in the RGB ″ signal. Separate the B signal. The drive signal converter 113 expands the RGB video signal including the separated R signal, G signal, and B signal so as to have an appropriate signal level for the display unit 114, as described in the first embodiment. I do. Display 114
Displays an image using an extended RGB format image signal.

According to the video signal converter 501 as described above, the R signal and the G signal having the information amount of 6 bits per unit time are provided.
The signal and the B signal are time-division multiplexed to be converted into an RGB ″ signal having an information amount of 6 bits per unit time. Further, by performing bit inversion processing on any of the R signal, the G signal, and the B signal, it is not necessary to transmit a signal indicating a pixel break alone. Thus, in the above-described first embodiment, the number of signal lines required to transmit the R signal, the G signal, the B signal, and the determination signal MKR indicating the pixel break is seven, but in the present embodiment, , R signals, G signals, B signals, and signals indicating pixel breaks, the number of signal lines required is six, so that one signal line can be reduced as compared with the first embodiment. it can.

Further, the number of signal lines for transmitting the RGB format video signal is 21 in total in the conventional system as described above. However, in the present embodiment, the vertical start pulse signal STV (1 line) is used. ), Horizontal direction start pulse signal STH (1 line), triple clock signal (1 line), RG
A total of nine B '' signals (six) are provided. That is, in the present embodiment, the number of twelve signal lines can be reduced as compared with the conventional method.

Further, by setting the number of video signals to be multiplexed by the multiplexer 503 to 3, the multiplexing transmission speed of the R, G, and B signals can be increased as in the first embodiment.
It can be three times as large as one pixel.

As described above, according to the video signal converter according to the present embodiment, a plurality of video signals are
By converting the video signals into one video signal, the number of signal lines required for transmitting the RGB format video signal can be suppressed without converting the plurality of video signals into analog signals. In addition, by performing bit inversion processing on any of a plurality of video signals, it is not necessary to transmit a signal indicating a pixel break alone, so that RG
The number of signal lines required for transmitting the B-format video signal can be further reduced.

In the present embodiment, an example has been described in which bit inversion processing is performed on B signals in a plurality of video signals to be time-division multiplexed. However, the present invention is not limited to this. , Drive signal converter 5 of display unit 504
The present invention is also applicable to the case where bit inversion processing is performed on at least one of the R signal, the G signal, and the B signal within a range where the pixel 05 can accurately recognize a pixel segment.

Further, in the present embodiment, a case where a signal indicating a pixel break is used as a control signal to be omitted from the RGB format video signal has been described as an example. However, the present invention is not limited to this. Is applicable even when a control signal other than the pixel separation is used. In this case, the method of inverting the R signal, the G signal, or the B signal may be changed based on the content of the control signal used.

(Embodiment 4) In the present embodiment, a case where different multiplexing formats are required by display units will be described. Hereinafter, the video signal converter according to the present embodiment will be described with reference to FIG. FIG.
FIG. 9 is a block diagram showing a configuration of a video display device including a video signal converter according to Embodiment 4 of the present invention. In addition, about the structure similar to Embodiment 1 (FIG. 1) in FIG. 7, the same code | symbol as the thing in FIG. 1 is attached | subjected, and detailed description is abbreviate | omitted.

Referring to FIG. 7, a video signal converter 701 according to the present embodiment includes a multiplier 702 for multiplying the frequency of a clock signal VCK in accordance with a multiplex format selection signal 700, a pixel count value and A pixel division counter 703 that generates a pixel division count value and a discrimination signal MKR indicating a pixel division using the multiplied clock signal VCK, and a multiplexer 704 that performs time division multiplexing processing according to the multiplexing format selection signal 700.
It has.

Next, the operation of the video signal converter 701 having the above configuration will be described. When the display unit 705 requires the multiplexing format described in the first, second, and third embodiments, the multiplexing format selection signal 700 is set to “00” by a control unit (not shown). "," 01 "and"
10 ". Embodiments 1 to
The details of the multiplex format described in the third embodiment will be omitted.

The multiplier 702 multiplies the clock signal VCK by n times in accordance with the multiplex format selection signal 700 by adjusting the phase to the falling edge of the clock signal VCK. Specifically, the multiplex format selection signal 7
When 00 is “00” and “10”, n = 3, and when the multiplex format selection signal 700 is “01”, n = 4.

The pixel division counter 703 calculates the pixel count value (PXL_NO) and the multiplied clock signal (V
CK × n), and counts 0 to n−1 within one pixel interval to generate a pixel division count value. The pixel division counter 703 outputs the multiplex format selection signal 7
A determination signal MKR is generated in response to 00. That is, when the multiplexing format selection signal 700 is “00”, the pixel division counter 703 outputs the determination signal MKR to the display unit 705, and outputs the multiplexing format selection signal 7
If 00 is other than “00”, the determination signal MKR
Is fixed to '0' or 'Z' (high impedance).

The multiplexer 704 performs time division multiplexing processing according to the multiplexing format selection signal 700 based on the pixel division count value. Specifically, when the multiplexing format selection signal 700 is “00”, the multiplexer 704 sequentially extracts any of the R, G, and B signals from the arithmetic unit 107 and outputs the signals within a time interval corresponding to one pixel. By performing division multiplexing, a 6-bit RGB signal is generated. When the multiplexing format selection signal 700 is “01”, the multiplexer 704 sequentially takes out one of the R, G, B signals and the discrimination code MKR from the operation unit 107 and performs time division within a time interval corresponding to one pixel. By multiplexing, a 6-bit RGB ′ signal is generated. When the multiplexing format selection signal 700 is “10”, the multiplexer 704 outputs the R, G, B
The signals are sequentially extracted (the B signal is subjected to bit inversion processing) and time-division multiplexed within a time interval corresponding to one pixel, thereby generating a 6-bit RGB ″ signal.

On the other hand, the display unit 705 can display an image by using an RGB format image signal received via the interface 707. Specifically, in the display unit 705, the drive signal converter 706
A discrimination signal MKR indicating a pixel separation, a discrimination code MKR multiplexed on the RGB signals, or a code indicating a pixel separation within the vertical blanking period and the horizontal blanking period.
The drive signal converter 706 separates each of the R signal, the G signal, and the B signal from the RGB signal by using the 111111 ″. The video signal of the RGB format including the separated R signal, G signal, and B signal. Is expanded to have an appropriate signal level for the display unit 114. The display unit 11
4 projects an image using an extended RGB format image signal.

As described above, according to the video signal converter according to the present embodiment, even when a different multiplexing format is required by the display unit, the multiplexing format selection signal is switched, whereby the first embodiment is achieved.
Since the time-division multiplexing process described in the third embodiment can be performed, the RGB corresponding to the request from the display unit
The video signal of the format can be reliably output to the display unit. At this time, the plurality of video signals are time-division multiplexed and converted into one video signal, so that the plurality of video signals can be converted into RGB signals without being converted into analog signals.
The number of signal lines required for transmitting a video signal of a format can be reduced.

(Embodiment 5) In this embodiment, a case will be described in which the information amount per unit time of a plurality of video signals is changed. Hereinafter, the video signal converter according to the present embodiment will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration of a video display device including the video signal converter according to the fifth embodiment of the present invention. FIG.
The same reference numerals as in FIG. 1 denote the same components as in Embodiment 1 (FIG. 1), and a detailed description thereof will be omitted.

In the present embodiment, as an example, the operation unit 1
The information amount per unit time of each of the R, G, and B signals from 07 is set to 6 bits, and the information amount per unit time of the plurality of video signals is changed to 1 bit.

Referring to FIG. 8, a video signal converter 801 according to the present embodiment includes a multiplier 802 for multiplying the frequency of the clock signal VCK by six times, and a pixel count value and the multiplied clock signal VCK. The pixel division counter 803 that generates a pixel division count value and a discrimination signal MKR indicating the pixel division, and the R, G, and B signals from the arithmetic unit 107 using the pixel division count value and the multiplied clock signal VCK. And a parallel / serial converter 804 that performs a parallel / serial conversion process on each of them.

The operation of the video signal converter 801 having the above configuration will be further described with reference to FIG. FIG.
FIG. 14 is a timing chart showing an operation of the video signal converter according to the fifth embodiment of the present invention.

The frequency multiplier 802 multiplies the clock signal VCK so that the frequency becomes six times by adjusting the phase to the falling edge of the clock signal VCK. The clock signal multiplied by six (hereinafter referred to as “six-times clock signal (VCK ×
6). Is output to the pixel division counter 803 and the parallel / serial converter 804.

The pixel division counter 803 calculates the pixel count value (PXL_NO) and the six-times clock signal (VCK ×
Using 6), 0 to 5 are counted within one pixel interval to generate a pixel division count value and a discrimination signal MKR indicating a pixel segment. The pixel division count value and the determination signal MKR are output to the parallel / serial converter 804.

The parallel / serial converter 804 outputs a six-fold clock signal (VCK) based on the pixel division count value.
× 6) for each falling edge of R,
By performing a parallel / serial conversion process on each of the G and B signals, the R, G, and B signals can be converted at a rate of 6 times per unit time within one pixel equivalent time interval.
A signal having a bit information amount is converted into a signal having a 1-bit information amount per unit time. By this parallel / serial conversion processing, the 6-bit R signal (“R5-0” in FIG. 9) and the G signal (“G
5-0)) and the B signal (“B5-0” in FIG. 9) are displayed one bit at a time starting from the LSB.
5 are output as R ', G' and B 'signals.

As described above, the video signal in the RGB format is sent to the display unit 805 via the interface 807 by the video signal converter 801. The RGB video signal is a signal including an R ′ signal, a G ′ signal, a B ′ signal, and a control signal. Here, the control signal includes a drive signal such as a vertical direction start pulse signal STV, a horizontal direction start pulse signal STH, a 6-times clock signal (VCK × 6), and a determination signal MKR.

On the other hand, the display unit 805 can display an image by using an RGB format image signal received via the interface 807. Specifically, in the display unit 805, the drive signal converter 806
6 times clock signal (VCK × 6) and discrimination signal MKR
By performing serial / parallel conversion processing on the R ′ signal, the G ′ signal, and the B ′ signal, thereby obtaining an R signal, a G signal, and a B signal having an information amount of 6 bits per unit time.
Generate a signal. Further, the drive signal converter 806 expands the generated R signal, G signal, and B signal, and other RGB format video signals so that the signal level is appropriate for the display unit 114. Display 114
Displays an image using an extended RGB format image signal.

According to the video signal converter 801 as described above, the R signal and the G signal having an information amount of 6 bits per unit time are provided.
The signal and the B signal are converted into a signal having an information amount of 1 bit per unit time using a parallel / serial conversion process. Thus, in the conventional method, the number of signal lines required for transmitting the R signal, the G signal, and the B signal is 18
In this embodiment, the number of signal lines required for transmitting the R signal, the G signal, and the B signal is three in this embodiment, so that the number of signal lines is reduced by 15 as compared with the conventional method. be able to.

Further, in the conventional system, the number of signal lines for transmitting the RGB format video signal is as follows: the vertical start pulse signal STV (one), the horizontal start pulse signal STH (one), and the clock signal DOTCLK. (1
, R signal (six), G signal (six), and B signal (six), for a total of 21 lines. In the present embodiment, the vertical direction start pulse signal STV (one line), the horizontal direction The start pulse signal STH (one signal) and the discrimination signal MKR (1
), 6 times clock signal (1), R'G'B 'signal (3
Total of 7). That is, in the present embodiment,
14 signal lines can be reduced as compared with the conventional method.

As described above, according to the video signal converter according to the present embodiment, at least one of a plurality of video signals is provided.
Since the transmission speeds of the two signals are changed, the number of signal lines required to transmit the RGB format video signal can be suppressed without converting the plurality of video signals into analog signals. Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

In the present embodiment, the case where the transmission rate is changed for all of the plurality of video signals has been described. However, the present invention is not limited to this, and at least one of the plurality of video signals may be changed. The present invention is also applicable to the case where the transmission speed is changed for one of them. In other words, it is possible to reduce the number of signal lines required for transmitting the RGB format video signal only by changing at least one transmission speed of the plurality of video signals.

Further, in the present embodiment, a case where a video signal having an information amount of 6 bits per unit time is converted into a signal having an information amount of 1 bit per unit time has been described as an example. However, the present invention is not limited to this, and can be applied to a case where the amount of information per unit time of a video signal is appropriately changed. For example, in the above example, it is possible to change the R, G, and B signals having an information amount of 6 bits per unit time into a signal having an information amount of 3 (or 2) bits per unit time. In other words, referring to FIG. 9, for example, the R signal is represented by R0_0,1,2 and R0_0.
3, 4, and 5 (R_0, 1 and R_2, 3 and R_4, 5) can be converted into a multiplexed signal.
In this case, the clock signal VC of 2 (3) times is supplied to the multiplier.
K is output and the pixel division counter is set to 0 to 1
What is necessary is just to count the pixel division count value of (0-2).

(Embodiment 6) In this embodiment, a case where a control signal is inserted into a video signal whose information amount per unit time is changed in Embodiment 5 will be described. Hereinafter, the video signal converter according to the present embodiment will be described with reference to FIG. FIG. 10 is a block diagram illustrating a configuration of a video display device including the video signal converter according to the sixth embodiment of the present invention. In addition, about the structure similar to Embodiment 5 (FIG. 8) in FIG. 10, the same code | symbol as the thing in FIG. 8 is attached | subjected, and detailed description is abbreviate | omitted.
In the present embodiment, a case where a signal indicating a pixel break is used as a control signal will be described as an example.

Referring to FIG. 10, a video signal converter 1001 according to the present embodiment uses a multiplier 1002 for multiplying the frequency of a clock signal by seven times, and a pixel count value and a multiplied clock signal VCK. A pixel division counter 1003 for generating a pixel division count value, and a pixel division count value and a multiplied clock signal VCK.
And a parallel / serial converter 1004 that performs a parallel / serial conversion process on each of the R, G, and B signals from the arithmetic unit 107 using

Video signal converter 1001 having the above configuration
Will be further described with reference to FIG. FIG. 11 is a timing chart showing the operation of the video signal converter according to the sixth embodiment of the present invention.

The frequency multiplier 1002 multiplies the clock signal VCK by adjusting the phase to the falling edge of the clock signal VCK so that the frequency becomes 7 times. A clock signal multiplied by 7 (hereinafter referred to as a “7-times clock signal (VCK ×
7). Is output to the pixel division counter 1003 and the parallel / serial converter 1004.

The pixel division counter 1003 calculates the pixel count value (PXL_NO) and the seven-times clock signal (VCK).
× 7), 0 to 6 are counted within one pixel interval to generate a pixel division count value. The pixel division count value is output to the parallel / serial converter 1004.

[0130] The parallel / serial converter 1004 provides a 7-fold clock signal (VC) based on the pixel division count value.
By performing a parallel / serial conversion process on each of the R, G, and B signals from the arithmetic unit 107 for each falling edge of (K × 7), within a time interval corresponding to one pixel,
Each of the R, G and B signals is converted from a signal having an information amount of 6 bits per unit time to a signal having an information amount of 1 bit per unit time. At this time, the serial / parallel converter 1004 inserts the discrimination code MKR into each of the R signal, the G signal, and the B signal converted into a signal having an information amount of 1 bit per unit time, at a time interval corresponding to one pixel. I do. That is, the serial / parallel converter 1004 time-divisions each of the R signal, the G signal, and the B signal having a 1-bit transmission rate and the discrimination code MKR having a 1-bit transmission rate for each time interval corresponding to one pixel. Multiplex.

Here, a discrimination code MKR indicating a pixel break
Is set to '1'. That is, the transmission speed of the discrimination code MKR is determined by the R signal after the serial / parallel conversion processing,
The transmission speed is set to be the same as the transmission speed of the G signal and the B signal (here, 1 bit). In the vertical blanking period and the horizontal blanking period, the R signal, the G signal, and the B signal are all at the black level, that is, “000000”.
The R ″ signal, G ″ signal and B ″ signal output from 004 become “1” only at the position of the discrimination code MKR. From this property, it is possible to identify a pixel segment.

By this parallel / serial conversion processing,
Each of the 6-bit R signal (“R5-0” in FIG. 11), the G signal (“G5-0” in FIG. 11), and the B signal (“B5-0” in FIG. 11) obtained by the arithmetic unit 107 Is LS
From B to the display unit 805 one bit at a time,
It is output as an R ″ signal, a G ″ signal and a B ″ signal.

As described above, the video signal converter 1001 converts the video signal in the vertical RGB format into the interface 10.
07 to the display unit 1005. This R
The video signal in the GB format is a signal including an R ″ signal, a G ″ signal, a B ″ signal, and a control signal. Here, the control signal includes a direct start pulse signal STV, a horizontal start pulse signal STH, and a seven-fold clock signal (VCK × 7).
And the like.

On the other hand, the display unit 1005 can display an image using the RGB image signal received via the interface 1007. Specifically, in the display unit 1005, the drive signal converter 1
006 uses the 7 × clock signal (VCK × 7) and the discrimination code MKR during the vertical blanking period and the horizontal blanking period, and uses the R ″ signal, the G ″ signal, and the B ″ signal.
By performing serial / parallel conversion processing on the signal, an R signal having an information amount of 6 bits per unit time,
Generate a G signal and a B signal. Further, the drive signal converter 1006 generates the generated R signal, G signal and B signal,
In addition, the video signal of the RGB format other than these is extended so that the signal level becomes appropriate for the display unit 114. The display unit 114 displays an image using an extended RGB format image signal.

According to the video signal converter 1001 as described above, an R signal having an information amount of 6 bits per unit time,
The G signal and the B signal are converted into a signal having an information amount of 1 bit per unit time using a parallel / serial conversion process. Further, a code indicating a pixel break is inserted into each of the R signal, the G signal, and the B signal converted into a signal having an information amount of 1 bit per unit time. Thus, in the fifth embodiment, the number of signal lines required to transmit the R signal, the G signal, the B signal, and the determination signal MKR is four, but in the present embodiment, the R signal, the G signal ,
Since the number of signal lines required to transmit the B signal and the discrimination code MKR is three, one signal line can be reduced as compared with the fifth embodiment.

In the conventional system, the number of signal lines for transmitting the RGB format video signal is as follows: the vertical start pulse signal STV (one), the horizontal start pulse signal STH (one), and the clock signal DOTCLK. (1
, R signal (six), G signal (six), and B signal (six), for a total of 21 lines. In the present embodiment, the vertical direction start pulse signal STV (one line), the horizontal direction There are a total of six start pulse signals STH (one), seven-fold clock signals (one), and R "G" B "signals (three). That is, in the present embodiment, compared to the conventional method,
Fifteen signal lines can be reduced.

As described above, according to the video signal converter according to the present embodiment, since the transmission speed is changed for at least one of the plurality of video signals, it is possible to convert the plurality of video signals into analog signals. No, RG
It is possible to reduce the number of signal lines required for transmitting the video signal of the B format. Further, by inserting a signal indicating a pixel break into a video signal whose transmission speed has been changed, the number of necessary signal lines can be further reduced. Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

Although the present embodiment has been described by taking as an example a case where a video signal having an information amount of 6 bits per unit time is converted into a signal having an information amount of 1 bit per unit time, the present invention However, the present invention is not limited to this, and can be applied to a case where the amount of information per unit time of a video signal is appropriately changed. For example, in the above example, it is possible to change the R, G, and B signals having an information amount of 6 bits per unit time into a signal having an information amount of 3 (or 2) bits per unit time. In this case, the multiplier may output the clock signal VCK three times (4) times, and the pixel division counter may count the pixel division count value of 0 to 2 (0 to 3).

Further, in the present embodiment, the case where a signal indicating a pixel segment is time-division multiplexed as one of the control signals has been described as an example. However, the present invention is not limited to this, and the present invention is not limited to this. The present invention is also applicable to a case where a control signal other than a signal is time-division multiplexed.

(Embodiment 7) In this embodiment, a case will be described in which the control signal is omitted from the RGB format video signal output to the display unit in Embodiments 5 and 6. Hereinafter, the video signal converter according to the present embodiment will be described with reference to FIG. FIG.
FIG. 14 is a block diagram illustrating a configuration of a video display device including a video signal converter according to a seventh embodiment of the present invention. In addition, about the structure similar to Embodiment 5 (FIG. 8) in FIG. 12, the same code | symbol as the thing in FIG.
Detailed description is omitted. In the present embodiment, a case where a signal indicating a pixel break is used as a control signal will be described as an example.

Referring to FIG. 12, video signal converter 1201 according to the present embodiment has a pixel count value of 6
A pixel division counter 1202 that generates a pixel division count value using the double clock signal (VCK × 6), and a parallel / serial converter that performs parallel / serial conversion processing on each of the R, G, and B signals from the arithmetic unit 107 And a serial converter 1203.

A video signal converter 1201 having the above configuration
Will be further described with reference to FIG. FIG. 13 is a timing chart showing an operation of the video signal converter according to the seventh embodiment of the present invention.

The pixel division counter 1202 calculates the pixel count value (PXL_NO) and the six-fold clock signal (VCK).
X6), 0 to 5 are counted within one pixel interval to generate a pixel division count value. The pixel division count value is output to the parallel / serial converter 1203.

The parallel / serial converter 1203 outputs a six-time clock signal (VC) based on the pixel division count value.
By performing a parallel / serial conversion process on each of the R, G, and B signals from the arithmetic unit 107 for each falling edge of (K × 6), within one pixel equivalent time interval,
Each of the R, G and B signals is converted from a signal having an information amount of 6 bits per unit time to a signal having an information amount of 1 bit per unit time. At this time, the parallel / serial converter 1203 performs a bit inversion process on each MSB of the R signal, the G signal, and the B signal.

For example, if the R signal from the arithmetic unit 107 is “1”
10101 ", the parallel / serial converter 1
203 sets “010101”. In the vertical blanking period and the horizontal blanking period, R, G, B
Since all the signals are at the black level, that is, “000000”, the value obtained by inverting the MSB of the R, G, B signals is “1”.
Becomes Thereby, it is possible to identify the pixel break in the above period. By this parallel / serial conversion processing, the 6-bit R signal (“R5-0” in FIG. 13) and the G signal (“G5-
0 ”) and the B signal (“ B5-0 ”in FIG. 13) are displayed one bit at a time starting from the LSB.
Are output as an R ′ ″ signal, a G ″ ″ signal and a B ′ ″ signal.

As described above, the video signal converter 1201 converts the RGB format video signal into the interface 120
6 to the display unit 1204. This RG
The B format video signal is a signal including an R ′ ″ signal, a G ′ ″ signal, a B ′ ″ signal, and a control signal. Here, the control signals include a vertical direction start pulse signal STV, a horizontal direction start pulse signal STH, and a 6-fold clock signal (VCK ×
6) and the like.

On the other hand, the display unit 1204 can display an image using the RGB format image signal received via the interface 1206. Specifically, in the display unit 1204, the drive signal converter 1
Reference numeral 205 denotes an R ′ ″ signal and a G ′ ″ signal using a 6-times clock signal (VCK × 6) and a code “1” indicating a pixel break during the vertical blanking period and the horizontal blanking period.
By performing a serial / parallel conversion process on the signal and the B ′ ″ signal, an R signal, a G signal, and a B signal having an information amount of 6 bits per unit time are generated. Further, the drive signal converter 1205 extends the generated R signal, G signal, and B signal, and other RGB format video signals so that the signal level is appropriate for the display unit 114. The display unit 114 displays the extended RGB
The video is projected using the video signal of the format.

According to the video signal converter 1201 as described above, an R signal having an information amount of 6 bits per unit time,
The G signal and the B signal are converted into a signal having an information amount of 1 bit per unit time using a parallel / serial conversion process. Further, each MSB of the R signal, the G signal and the B signal having an information amount of 6 bits per unit time
By performing a bit inversion process on the image data, it is not necessary to transmit a signal indicating a pixel segment independently. Thus, in the fifth embodiment, the number of signal lines required to transmit the R signal, the G signal, the B signal, and the determination signal MKR is four.
In this embodiment, the number of signal lines required for transmitting the R signal, the G signal, the B signal, and the signal indicating the pixel break is three in this embodiment. 1
The number of signal lines can be reduced.

Further, in the conventional system, the number of signal lines for transmitting the RGB format video signal is as follows: the vertical start pulse signal STV (one), the horizontal start pulse signal STH (one), and the clock signal DOTCLK. (1
, R signal (six), G signal (six), and B signal (six), for a total of 21 lines. In the present embodiment, the vertical direction start pulse signal STV (one line), the horizontal direction There are a total of six start pulse signals STH (one), six times clock signal (one), and R '"G'" B '"signals (three). That is, in the present embodiment, 15 signal lines can be reduced as compared with the conventional method.

As described above, according to the video signal converter according to the present embodiment, since the transmission speed of at least one of the plurality of video signals is changed, it is possible to convert the plurality of video signals into analog signals. No, RG
It is possible to reduce the number of signal lines required for transmitting the video signal of the B format. In addition, by performing bit inversion processing on the video signal whose transmission speed has been changed, the control signal can be transmitted with the video signal whose transmission speed has been changed, so that the required number of signal lines can be further reduced. . Thus, the number of signal lines for transmitting the video signal to the display unit can be suppressed without deteriorating the quality of the video.

In this embodiment, the R signal,
Although the case where the bit subjected to the bit inversion processing in the G signal and the B signal is MSB has been described as an example, the present invention is not limited to this. signal,
The present invention is also applicable to a case where the bits to be subjected to the bit inversion processing are appropriately changed in each of the G signal and the B signal.

Further, in the present embodiment, a case where a video signal having an information amount of 6 bits per unit time is converted into a signal having an information amount of 1 bit per unit time has been described as an example. However, the present invention is not limited to this, and can be applied to a case where the amount of information per unit time of a video signal is appropriately changed. For example, in the above example, it is possible to change the R, G, and B signals having an information amount of 6 bits per unit time into a signal having an information amount of 3 (or 2) bits per unit time. In this case, the multiplier 802 may output the clock signal VCK multiplied by 2 (3), and the pixel division counter may count the pixel division count value of 0 to 1 (0 to 2).

Further, in the present embodiment, the case where a signal indicating a pixel segment is used as a control signal has been described as an example. However, the present invention is not limited to this, and control signals other than a signal indicating a pixel segment are used. This is applicable even when using. In this case, the method of inverting the R signal, the G signal, or the B signal may be changed based on the content of the control signal to be used.

(Embodiment 8) In this embodiment, a case where a different serial format (serial format) is required by the display unit will be described. Hereinafter, the video signal converter according to the present embodiment will be described with reference to FIG. FIG. 14 is a block diagram illustrating a configuration of a video display device including the video signal conversion device according to the eighth embodiment of the present invention. In addition, about the structure similar to Embodiment 5 (FIG. 8) in FIG. 14, the same code | symbol as the thing in FIG. 8 is attached | subjected, and detailed description is abbreviate | omitted.

Referring to FIG. 14, a video signal converter 1401 according to the present embodiment includes a multiplier 1402 for multiplying the frequency of clock signal VCK in response to a serial format selection signal 1400, a pixel count value and a multiplier. A pixel division counter 1403 that generates a pixel division count value and a determination signal MKR indicating a pixel division using the clock signal VCK thus obtained, and a multiplexer 1404 that performs a parallel / serial conversion process according to the serial format selection signal 1400. Have.

Next, the operation of the video signal converter 1401 having the above configuration will be described. Display unit 140
5, when the serial format described in the fifth, sixth and seventh embodiments is required, the serial format selection signal 1400 is set to “00” and “00” by control means (not shown), respectively. 0
1 "and" 10 ". Details of the serial format described in the fifth to seventh embodiments will be omitted.

The multiplier 1402 adjusts the phase of the clock signal VCK to n in accordance with the serial format selection signal 1400 to adjust the phase to the falling edge of the clock signal VCK.
Multiply by a factor of two. Specifically, when the serial format selection signal 1400 is “00” and “10”, n
= 6, and the serial format selection signal 1400
Is "01", n = 7.

Using the pixel count value (PXL_NO) and the multiplied clock signal (VCK × n), the pixel division counter 1403 sets 0 to n−1 within one pixel interval.
Is counted to generate a pixel division count value. Also,
The pixel division counter 1403 generates a determination signal MKR according to the serial format selection signal 1400. That is, the pixel division counter 1403 outputs the determination signal MKR to the display unit 1405 when the serial format selection signal 1400 is “00”, and determines when the serial format selection signal 1400 is other than “00”. The signal MKR is fixed to '0' or 'Z' (high impedance).

A parallel / serial converter 1404 performs a parallel / serial conversion process according to a serial format selection signal 1400 based on the pixel division count value. Specifically, the serial format selection signal 14
When 00 is “00”, the parallel / serial converter 1404 performs a parallel / serial conversion process on each of the R, G, and B signals from the arithmetic unit 107 to thereby execute the processing within the time interval corresponding to one pixel. Then, each of the R, G and B signals is converted from a signal having an information amount of 6 bits per unit time to a signal having an information amount of 1 bit per unit time.

Serial format selection signal 1400
Is “01”, the R, G, B
By performing a parallel / serial conversion process on each of the signals, the R signal, the G signal, and the
Each of the signal and the B signal is converted from a signal having an information amount of 6 bits per unit time to a signal having an information amount of 1 bit per unit time. At this time, the serial / parallel converter 1404 outputs a discrimination code MKR to each of the R signal, G signal, and B signal converted to a signal having an information amount of 1 bit per unit time at every one pixel equivalent time interval.
Insert

Serial format selection signal 1400
Is "10", the parallel / serial converter 14
04 performs a parallel / serial conversion process on each of the R, G, and B signals from the arithmetic unit 107, and thereby, within a time interval corresponding to one pixel, the R signal, the G signal, and the B signal.
Each of the signals is converted from a signal having an information amount of 6 bits per unit time to a signal having an information amount of 1 bit per unit time. At this time, the parallel / serial converter 1
203 is the M of each of the R signal, G signal and B signal.
A bit inversion process is performed on the SB.

On the other hand, the display unit 1405 can display an image using the RGB format image signal received via the interface 1407. Specifically, in the display unit 1405, the drive signal converter 1
Reference numeral 406 denotes a serial video using a discrimination signal MKR indicating a pixel break, a discrimination code MKR inserted in the RGB signal, or a code “1” indicating a pixel break in the vertical blanking period and the horizontal blanking period. By subjecting the signal to serial / parallel conversion processing, each of the R signal, the G signal, and the B signal is extracted from the video signal.

The driving signal converter 1406 extends the RGB video signal including the extracted R signal, G signal, and B signal so that the signal level becomes appropriate for the display unit 114. The display unit 114 displays the expanded RG
A video is projected using a B-format video signal.

As described above, according to the video signal converter of the present embodiment, even when a different serial format is required by the display unit, the serial format selection signal is switched so that the fifth to fifth embodiments can be implemented. Since the parallel / serial conversion processing described in the seventh embodiment can be performed, an RGB format video signal corresponding to a request from the display unit can be reliably output to the display unit. At this time, by performing a parallel / serial conversion process on each of the plurality of video signals, each of the plurality of video signals is converted into a signal having an information amount of 1 bit per unit time.
Signal lines required for transmitting RGB format video signals can be suppressed without converting the plurality of video signals into analog signals.

In this embodiment, an example has been described in which a video signal having an information amount of 6 bits per unit time is converted into a signal having an information amount of 1 bit per unit time. However, the present invention is not limited to this, and can be applied to a case where the amount of information per unit time of a video signal is appropriately changed. For example, in the above example, it is possible to change the R, G, and B signals having an information amount of 6 bits per unit time into a signal having an information amount of 3 (or 2) bits per unit time. In this case, the serial format selection signal may have information indicating the number of bits.

The video signal converter described in the above embodiment can be mounted on a communication terminal device such as a mobile station device or a portable information terminal.

[0167]

As described above, according to the present invention,
A signal for transmitting a video signal to a display unit without deteriorating video quality because a plurality of video signals having the same transmission speed are time-division multiplexed or the transmission speed of the video signal is changed. A video signal converter that suppresses lines can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video display device including a video signal converter according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the video signal converter according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a video display device including a video signal converter according to a second embodiment of the present invention;

FIG. 4 is a timing chart showing an operation of the video signal converter according to the second embodiment of the present invention;

FIG. 5 is a block diagram illustrating a configuration of a video display device including a video signal converter according to a third embodiment of the present invention;

FIG. 6 is a timing chart showing an operation of the video signal converter according to the third embodiment of the present invention;

FIG. 7 is a block diagram illustrating a configuration of a video display device including a video signal converter according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a video display device including a video signal converter according to a fifth embodiment of the present invention.

FIG. 9 is a timing chart showing an operation of the video signal converter according to the fifth embodiment of the present invention;

FIG. 10 is a block diagram showing a configuration of a video display device including a video signal converter according to a sixth embodiment of the present invention.

FIG. 11 is a timing chart showing an operation of the video signal converter according to the sixth embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a video display device including a video signal converter according to a seventh embodiment of the present invention.

FIG. 13 is a timing chart showing the operation of the video signal converter according to the seventh embodiment of the present invention;

FIG. 14 is a block diagram illustrating a configuration of a video display device including a video signal conversion device according to an eighth embodiment of the present invention.

FIG. 15 is a block diagram illustrating a configuration of a video display device including a conventional video signal converter.

FIG. 16 is a timing chart showing the operation of the video signal converter 2 in the conventional video display device.

[Explanation of symbols]

103 scanning line counter 104 pixel counter 105 drive signal generator 106 buffer 107 arithmetic unit 108, 304, 503, 704 multiplexer 109, 302, 702, 802, 1002, 1402
Multiplier 110, 303, 502, 703, 803, 1003
1202, 1403 Pixel division counter 112, 305, 504, 705, 805, 1005
1204, 1405 Display unit 804, 1004, 1203, 1404 Parallel / serial converter

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H04N 7/08 H04N 9/30 7/081 7/08 Z 9/30 F term (reference) 5C006 AA22 AC02 AC21 AF26 AF72 AF85 BF22 BF49 EC13 FA42 5C057 AA06 BA05 EA05 EB02 EB11 EL01 GF05 GF08 GM07 5C060 AA01 BC01 DA00 DB13 HB07 HB26 JB03 5C063 AB03 AB07 AC01 AC10 CA03 CA12 CA14 CA16 CA38 5C080 AA10 BB05 DD03 KK02 KK19 DD19

Claims (12)

[Claims] 1. A conversion means for converting a video signal in YCbCr format into a video signal in RGB format, and multiplexing for generating one video signal by time-division multiplexing at least two signals in the video signal in RGB format. Means for outputting a video signal in RGB format other than the time-division multiplexed signal and the one video signal as a new video signal in RGB format to display means for displaying video A video signal conversion device comprising: 2. The video signal conversion device according to claim 1, wherein the multiplexing unit time-division multiplexes at least two video signals. 3. The video signal according to claim 1, wherein the conversion unit generates a control signal, and the multiplexing unit time-division multiplexes the generated control signal and the video signal. Conversion device. 4. A multiplexing unit performs bit inversion processing on a signal to be time-division multiplexed based on information of a control signal, and an output unit excludes the control signal from a new RGB format video signal. The video signal conversion device according to any one of claims 1 to 3, wherein: 5. A conversion unit based on a request from a display unit.
5. The video signal converter according to claim 1, further comprising control means for controlling the multiplexing means and the output means. 6. A conversion means for converting a video signal in YCbCr format into a video signal in RGB format including a video signal having a predetermined transmission speed, and changing a transmission speed of at least one video signal in the video signal in RGB format. And a display means for displaying an image as a new RGB format video signal in a RGB format other than the video signal whose transmission speed has been changed and the video signal whose transmission speed has been changed. A video signal conversion device, comprising: output means capable of outputting. 7. The conversion means generates a control signal having the same transmission speed as the video signal after the change in the change means, and the change means generates the control signal having the transmission speed changed and the generated control signal. 7. The video signal conversion device according to claim 6, wherein the signal is time-division multiplexed. 8. The conversion means performs bit inversion processing on the video signal whose transmission speed has been changed based on the information of the control signal, and the output means converts the control signal into a new RGB signal.
7. A video signal of a format is excluded.
Alternatively, the video signal conversion device according to claim 7. 9. A conversion unit based on a request from the display unit,
9. The video signal conversion device according to claim 6, further comprising control means for controlling the change means and the output means. 10. A communication terminal device comprising the video signal conversion device according to any one of claims 1 to 9. 11. A conversion step of converting a video signal of YCbCr format into a video signal of RGB format, and multiplexing to generate one video signal by time-division multiplexing at least two signals in the video signal of RGB format. Process and
Outputting an RGB video signal other than the time-division multiplexed signal and the one video signal as a new RGB video signal to display means for displaying video, A video signal conversion method, comprising: 12. A converting step of converting a video signal of YCbCr format into a video signal of RGB format including a video signal having a predetermined transmission speed, and changing a transmission speed of at least one video signal in the video signal of RGB format. And a display step of displaying a video as a new RGB format video signal in the RGB format other than the video signal whose transmission speed has been changed and the video signal whose transmission speed has been changed as a new RGB format video signal. An output step capable of outputting the video signal.