JP2001211073A - Pll frequency synthesizer and controlling method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily implement a measure to prevent frequency of spurious outputted from a PLL frequency synthesizer form matching received frequency. SOLUTION: The PLL frequency synthesizer 2 of the present invention comprises a phase comparator 6, a loop filter 7, a voltage control oscillator 8, a prescaler 11 and a programmable counter 12 and so on. The prescaler 11 is constructed to have a plurality of division numbers K, L, and to be able to select desired one out of the plurality of division numbers K, L. Further, the prescaler 11 is constructed such that by switching the division number of the prescaler 11, the frequency of spurious outputted by synthesizer 2, 3 is changed while output frequency of PLL frequency synthesizer being fixed. With this construction, a measure can be readily implemented to prevent the frequency of spurious from matching received frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL suitable for use as a local oscillator of a wireless device such as a portable telephone.
The present invention relates to a frequency synthesizer and a control method thereof.

[0002]

2. Description of the Related Art A radio device such as a cellular phone or a mobile phone is configured so that a large number of radio channels can be switched and used, and includes an oscillation device (local oscillator) composed of a PLL frequency synthesizer. As the PLL frequency synthesizer, various types such as a prescaler fixed frequency dividing method or a pulse swallow method have been conventionally known.

[0003]

By the way, the PLL frequency synthesizer generally generates spurious signals such as reference leaks. Then, in the wireless device, when a receiving operation is performed, the receiving frequency may coincide with the spurious frequency, and when the two coincide, the receiving sensitivity is degraded. .

Here, it has been known that the output frequency of the PLL frequency synthesizer may be changed in order to change the spurious frequency. For this reason, in the conventional configuration, as a countermeasure against the reception sensitivity deterioration, when the reception frequency and the spurious frequency coincide with each other, the frequency of the plurality of frequency signals output from the plurality of PLL frequency synthesizers of the wireless device is reduced. Changing the composition ratio, that is, changing the output frequency of a plurality of PLL frequency synthesizers has been performed. According to this configuration, the spurious frequency changes and the reception frequency does not match the spurious frequency, so that the reception sensitivity is improved.

However, the above-described countermeasures for changing the frequency composition ratio of a plurality of frequency signals output from a plurality of PLL frequency synthesizers are rather troublesome and complicated controls.
In addition, there is a possibility that other high-frequency circuits of the wireless device may be affected. Therefore, as a countermeasure against the reception sensitivity deterioration,
There is a demand for easier measures.

Accordingly, an object of the present invention is to provide a PLL frequency synthesizer and a control method therefor which can easily realize a measure for preventing the frequency of a spurious output from the PLL frequency synthesizer from matching with the reception frequency. It is in.

[0007]

According to the first aspect of the present invention, the prescaler has a plurality of frequency division numbers, and a desired one can be selected from the plurality of frequency division numbers. By changing the frequency of the prescaler, the frequency of the spurious generated by the PLL frequency synthesizer is changed while the output frequency of the PLL frequency synthesizer is fixed. According to this configuration, the output frequency of the PLL frequency synthesizer can be kept fixed, and the frequency of the spurious output from the PLL frequency synthesizer does not match the reception frequency. Therefore, it is possible to easily implement a measure for preventing the frequency of the spurious from being equal to the reception frequency.

The inventor of the present invention considers that when the frequency division number of the prescaler is switched, the spurious frequency generated by the PLL frequency synthesizer changes even when the output frequency of the PLL frequency synthesizer is fixed.
They have discovered (confirmed) them through experiments and the like, and based on this discovery, invented the PLL frequency synthesizer of claim 1 above.

According to the control method of the PLL frequency synthesizer of the second aspect, the same operation and effect as the first aspect of the invention can be obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to, for example, an oscillation device of a portable telephone will be described below with reference to the drawings. First, FIG. 2 is a diagram illustrating a block configuration of an oscillation device (local oscillator) of the mobile phone according to the present embodiment. As shown in FIG. 2, the oscillator 1 includes first and second PLL frequency synthesizers 2 and 3 and a mixing circuit 4.
And a filter circuit 5.

The two PLL frequency synthesizers 2,
No. 3 has the same specific configuration. That is, each of the PLL frequency synthesizers 2 and 3 includes a phase comparator 6, a loop filter (hereinafter, referred to as LPF) 7, and a voltage-controlled oscillator (hereinafter, V
8) and frequency dividing circuits 9 and 10. In this case, in each of the PLL frequency synthesizers 2 and 3, the phase comparator 6, the LPF 7, and the VC
O8 and the frequency dividing circuit 9 are connected in a loop. In the present embodiment, each of the PLL frequency synthesizers 2, 3
Is constituted by, for example, a PLL frequency synthesizer of a prescaler fixed frequency dividing system.

The frequency dividing circuit 9 includes a prescaler 11 and a programmable counter 12 as shown in FIG. The prescaler 11 is a high-speed frequency divider having a fixed frequency division number. In the case of the present embodiment, the prescaler 11 has a plurality of, for example, two division numbers K and L, and is configured to be able to select (switch) any one of these two division numbers K and L. Have been. Here, the frequency division number K is, for example, 128, and the frequency division number L is, for example, 64. Note that other appropriate numerical values may be used as the division numbers K and L.

Further, the prescaler 11 is configured so that it can be switched to one of two frequency division numbers K and L by a control signal from the CPU 13. Then, the prescaler 11 is a PLL frequency synthesizer 2
The frequency fou of the output frequency signal F (out1) of (3)
A frequency fout1 / obtained by dividing t1 by a dividing number K or L
It has a function of outputting a frequency signal of K or fout1 / L.

The CPU 13 has a function of controlling the entire operation of the mobile phone. In this embodiment, illustration and description of other configurations of the mobile phone are omitted.

The programmable counter 12
Is a variable frequency divider, and a variable frequency dividing number N
i is settable. In this case, the programmable counter 12 has a function of outputting a signal of the frequency fout1 / KNi or fout1 / LNi obtained by dividing the frequency fout1 / K or fout1 / L of the output signal from the prescaler 11 by the variable frequency division number Ni. I have.

Now, in the oscillation device 1 having the above configuration,
When the reference signal F (STD) of the reference frequency f (STD) is the first
Is applied to the frequency dividing circuit 10 of the PLL frequency synthesizer 2 of FIG.
The frequency is divided by the frequency division number set to 0. Then, a frequency-divided circuit 10 generates a frequency-divided reference signal F (ref1) having a frequency-divided reference frequency f (ref1), and this signal is supplied to the phase comparator 6.

The intermediate output signal F (out1) of the intermediate output frequency f (out1) output from the VCO 8 is
It is provided to the mixing circuit 4 and the frequency dividing circuit 9. Here, the intermediate output signal F (out1) given to the frequency divider 9 is
The frequency division as described above generates a frequency-divided output signal F (v1) having a frequency-divided output frequency f (v1),
This signal is provided to the phase comparator 6.

In the phase comparator 6, the phase of the frequency-divided reference signal F (ref1) and the frequency-divided output signal F (v
The phases of 1) are compared so that the two phases become equal, that is, the divided reference frequency f (ref1) and the divided output frequency f
(V1) is controlled to be equal. As a result, V
The intermediate output frequency f (out1) of the intermediate output signal F (out1) output from the CO8 is equal to the reference frequency f (ST1).
D) is multiplied by the ratio of the frequency division number of the frequency division circuit 9 to the frequency division number of the frequency division circuit 10 so as to be equal to the frequency.

On the other hand, the second PLL frequency synthesizer 3
, The intermediate output signal F output from the VCO 8 in the same manner as the first PLL frequency synthesizer 2.
The intermediate output frequency f (out2) of (out2) is set to be equal to a frequency obtained by multiplying the reference frequency f (STD) by the ratio between the number of divisions of the frequency divider 9 and the frequency of the frequency divider 10. It is configured.

In the mixing circuit 4, the first P
The intermediate output signal F (ou) from the LL frequency synthesizer 2
t1) the intermediate output frequency f (out1) and the second PL
The intermediate output signal F (out) from the L frequency synthesizer 3
The intermediate output frequency f (out2) of 2) is frequency-mixed. Thereby, the output frequency f
An output signal F (out) of (out) is generated and provided to the filter circuit 5. Here, the output frequency f (o
(ut) is the absolute value of (intermediate output frequency f (out1) ± intermediate output frequency f (out2)).

Further, in the filter circuit 5, the low-frequency side of the output signal F (out) is limited in the pass band. As a result, the carrier frequency f (TX) of the carrier signal F (TX) output from the oscillation device 1 is (intermediate output frequency f (out1) + intermediate output frequency f (out)
2)). Thus, the carrier signal F (TX) having the desired carrier frequency f (TX) can be obtained by changing the number of divisions of the divider circuits 9 and 10 of the two PLL frequency synthesizers 2 and 3. Is configured. In the case of this embodiment, for example, 800 MHz band to 9
It is configured such that a 00 MHz band carrier signal F (TX) can be output at a predetermined channel interval frequency.

Note that two PLL frequency synthesizers 2,
3, any one of the frequency dividers 9 and 10 of the PLL frequency synthesizer may be configured to be variable, or one of the frequency dividers 9 and 10 of the PLL frequency synthesizer. It may be configured to change only the frequency division number of one of the frequency division circuits. In the case of the present embodiment, as described above, the frequency division number of (the programmable counter 12 of) the frequency division circuit 9 is configured to be variable.

Next, the operation of the above configuration, specifically, PL
The control operation of changing the frequency of the spurious generated by the PLL frequency synthesizer 2 (or 3) while keeping the output frequency of the L frequency synthesizer 2 or 3 fixed will be described with reference to the flowchart of FIG. still,
The flowchart of FIG. 3 shows the contents of the control operation of changing the spurious frequency generated by the PLL frequency synthesizer 2 (or 3) in the control operation of the CPU 13. In the following description, only the first PLL frequency synthesizer 2 will be described.

First, with the frequency division number of the prescaler 11 of the frequency division circuit 9 set to, for example, K (= 128),
By performing a reception test on all channels of the reception frequency of the mobile phone, a channel suffering from deterioration in reception sensitivity due to spurious generated by the PLL frequency synthesizer 2 is searched.

Then, the searched channel is stored in the memory of the portable telephone, and only when the searched channel is received, the frequency of the prescaler 11 of the frequency dividing circuit 9 is changed from K (= 128) to L (= 128). = 64). An example of this switching control will be described with reference to the flowchart of FIG.

In the portable telephone, when a channel to be received is set, switching control of the frequency division number of the prescaler 11 in FIG. 3 is executed. In this case, step S1 in FIG.
First, it is determined whether or not the channel {intermediate output frequency f (out1)} to be set in the PLL frequency synthesizer 2 matches the channel in which the reception sensitivity has deteriorated (that is, the channel searched for).

If they do not match, step S1
To "NO" to set the frequency of the prescaler 11 to K
(= 128) (step S2). On the other hand, if they match in step S1, the process proceeds to "YES", and the frequency division number of the prescaler 11 is set to L (= 64) (step S3).

Subsequently, the process proceeds to step S4, in which, for example, a PLLIC that actually configures the prescaler 11 is switched and set so that the frequency division number of the prescaler 11 becomes the frequency division number set above. Thus, the switching control of the frequency division number of the prescaler 11 is completed. The PLLIC used in this embodiment includes a frequency dividing circuit 9 (that is, a prescaler 11 and a programmable counter 12).
A commercially available IC constituting the frequency dividing circuit 10 and the phase comparator 6
It is.

Then, as described above, the prescaler 1
The inventors of the present invention have clearly confirmed through experiments that the frequency of spurious signals generated by the PLL frequency synthesizer 2 is changed and the receiving sensitivity of the channel is improved by switching and setting the frequency division number of 1. According to the experiment of the inventor, the reception sensitivity of the above channel is 3 to 4 d less than that when the reception sensitivity is deteriorated due to spurious.
It was confirmed that B was also improved.

Further, according to the configuration of this embodiment, the spurious frequency output from the PLL frequency synthesizer 2 does not match the reception frequency while the intermediate output frequency f (out1) of the PLL frequency synthesizer 2 is fixed. You can do so. Therefore, a measure for preventing the spurious frequency from being equal to the reception frequency can be easily realized as compared with the conventional configuration.

In the above-described embodiment, the control for changing the spurious frequency generated by the first PLL frequency synthesizer 2 is executed on the first PLL frequency synthesizer 2 while the output frequency is fixed. However, instead of this, the second PLL frequency synthesizer 3
The same control may be performed on the side.

Further, in the above embodiment, for example, the present invention is applied to the PLL frequency synthesizers 2 and 3 of the prescaler fixed frequency dividing system. However, the present invention is not limited to this, and may be applied to the PLL frequency synthesizer of the pulse swallow system. . In the case of the PLL frequency synthesizer of the pulse swallow method, as a 2-modulus prescaler, 1
/ K or 1 / (K + 1) and 1 / L or 1 / (L +
What is necessary is just to employ | adopt the thing of the structure which can switch and set 1).

In the above embodiment, the prescaler 11
As the (or two-modulus prescaler), one having two frequency division numbers is used, but one having three or more frequency division numbers may be used. Further, in the above embodiment, the present invention is applied to the oscillation device of the mobile phone. However, the present invention is not limited to this, and the invention may be applied to the oscillation device of an automobile phone, a PHS terminal, or another wireless device.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL frequency synthesizer according to an embodiment of the present invention.

FIG. 2 is a block diagram of an oscillation device of a mobile phone.

FIG. 3 is a flowchart.

[Explanation of symbols]

1 is an oscillation device, 2 is a first PLL frequency synthesizer,
3 is a second PLL frequency synthesizer, 6 is a phase comparator, 7 is a loop filter, 8 is a voltage controlled oscillator, 9 is a frequency divider, 10 is a frequency divider, 11 is a prescaler, 12 is a programmable counter, and 13 is a CPU. Is shown.

Claims (2)

[Claims] 1. A PLL frequency synthesizer comprising a phase comparator, a loop filter, a voltage controlled oscillator, a prescaler, a programmable counter, and the like, wherein the prescaler has a plurality of frequency division numbers, and the plurality of frequency divisions. It is configured such that a desired one can be selected from among the numbers, and by switching the frequency division number of the prescaler, P
A PLL characterized in that a spurious frequency generated by a PLL frequency synthesizer is changed while an output frequency of the LL frequency synthesizer is fixed.
Frequency synthesizer. 2. A method for controlling a PLL frequency synthesizer comprising a phase comparator, a loop filter, a voltage controlled oscillator, a prescaler, a programmable counter and the like, wherein the prescaler has a plurality of frequency division numbers,
By using a configuration in which a desired one can be selected from among the plurality of frequency division numbers and switching the frequency division number of the prescaler, P
A PLL which controls so as to change the frequency of spurious signals generated by a PLL frequency synthesizer while keeping the output frequency of the LL frequency synthesizer fixed.
Control method of frequency synthesizer.