JP2001203768A - Receive baseband circuit - Google Patents

Abstract

(57) Abstract: A reception baseband circuit capable of detecting symbol timing of a quadrature detection signal by digital signal processing and outputting received data by a demodulation process without delay. SOLUTION: A process of writing sample data obtained by digitally converting a quadrature detection signal into a multiport memory 421, a symbol timing detection process by an eye opening point detection circuit 422, and a reading and demodulation process of symbol timing data by a demodulation circuit 43 are described. By performing these operations in parallel, it is possible to output received data from the demodulation circuit 43 without delay without being affected by the symbol timing detection processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception baseband circuit for performing symbol timing detection of a quadrature detection signal by digital signal processing in wireless digital communication, and more particularly to a reception baseband circuit for outputting received data without delay. About.

[0002]

2. Description of the Related Art In radio digital communication, a receiver of a digital modulation system performs quadrature detection on a received baseband signal, and then performs a quadrature detection on the baseband signal (hereinafter referred to as a quadrature detection signal). A / D
Conversion is performed. A / D conversion of a quadrature detection signal is generally performed at a higher frequency than the symbol rate of the quadrature detection signal.

For example, if the symbol rate of a quadrature detection signal is S (symbols / sec), the receiver performs A / D conversion at a speed of M times the cycle S × M (symbols / sec). Hereinafter, this operation is called M-times oversampling. Generally, as the oversampling magnification, M = 4
An even number of ~ 32 is used. By performing oversampling on the orthogonal detection signal, sampling of the orthogonal detection signal at an ideal timing can be easily performed.

The relationship between the quadrature detection signal and the sample timing will be described with reference to FIG. FIG. 5 is a time chart showing a quadrature detection signal and sample timing when performing 4 × oversampling, and FIG. 6 is an explanatory diagram showing a constellation. Upon receiving the baseband signal, the receiver reproduces the symbol timing clock based on the baseband signal. Depending on the method of reproducing the symbol timing clock at this time,
The phase relationship between the quadrature detection signal and the symbol timing clock is determined.

When the A / D conversion is performed at the rising edge of the symbol timing clock, the symbol timing clock shown in FIG. 5 does not coincide with the point where the eye opening of the quadrature detection signal becomes the maximum, so that sampling by the symbol timing clock is performed. Then, the receiver cannot correctly reproduce the baseband signal during demodulation.

A constellation when the modulation method is QPSK is as shown in FIG. 6. When sampling is performed with a symbol timing clock, a signal point can take any of white circles in each quadrant. Since this deviates from the position of the appropriate signal point, the sampled baseband signal is reproduced in a state where noise is included, which is not preferable for communication.

When 4 times oversampling is performed,
In the oversampling timing clock, M rising edges are generated per symbol of the quadrature detection signal, and the timing at which the eye opening maximum point of the quadrature detection signal becomes more accurate as compared with the case of the symbol timing clock, that is, the symbol Can be sampled at the timing. In the constellation, the signal point is also at the position of the black circle, and the baseband signal is accurately reproduced.

As a method of detecting symbol timing in a receiver provided for digital wireless communication, MAM (M
aximum Amplitude Method), WDM (Wave Difference)
Various methods have been proposed, for example, a ZCM (Zero Crossing Method) and a ZCM (Zero Crossing Method). Regarding these detection methods, see IEICE Technical Report, RCS92-106, pp-43-4.
8, 1993-01, "Symbol Timing Reproduction Method of 16QAM / TDMA System" (Seiichi Sampei).

[0009] Among these detection methods, MAM is a method of detecting a clock having a timing closest to a symbol timing among oversampling clocks.
Hereinafter, a method of detecting symbol timing using MAM will be described. Assume that the received complex baseband signal at time t is represented by the following equation.

[0010]

(Equation 1)

At this time, the number of oversamples is M (1 ≦
m ≦ M), if the number of symbols of the quadrature detection signal to be processed by the MAM and N _a, the symbol timing likelihood function L
_{MA M} (m) can be expressed as the following equation.

[0012]

(Equation 2)

In the above equation, u (t _{k, m} ) means data on the quadrature detection signal at the m-th oversampling timing in the k-th symbol. L _MAM (m) is calculated for each oversampling clock m, and m such that L _MAM (m) has the maximum value can be regarded as the symbol timing. The above is MAM
This is a method for detecting symbol timing using.

The symbol timing likelihood function of the above equation can be applied to a symbol timing detection method based on WDM and ZCM by changing the equation.
It is known that MAM is the most effective method because of its low error rate.

Next, a collective demodulation receiver for conventional wireless digital communication which actually performs symbol timing detection will be described with reference to FIG. FIG. 7 is a configuration block diagram of a reception baseband circuit of a conventional accumulation batch demodulation receiver. As shown in FIG. 7, a reception baseband circuit of a conventional accumulation batch demodulation receiver includes an A / D conversion circuit 11,
It comprises a data storage circuit 12, a demodulation circuit 13, and a symbol timing detection circuit 14.

Each part in FIG. 7 will be specifically described. A
The / D conversion circuit 11 receives the quadrature detection signal a ′, which is an analog signal transmitted from a quadrature detector (not shown), performs digital conversion by oversampling, and outputs the result to the data storage circuit 12 as sample data. .

The data storage circuit 12 includes the A / D conversion circuit 1
The sample data output from 1 is input and stored for a predetermined period, that is, in frame units. The stored sample data is output to the demodulation circuit 13 and the symbol timing detection circuit 14.

The symbol timing detection circuit 14 is based on the sample data output from the data storage circuit 12,
The symbol timing is detected from the oversampling timing using the symbol timing detection method, and the symbol timing information b ', which is the detection result, is demodulated by the demodulation circuit 13.
Output to

The demodulation circuit 13 performs a decoding process on the quadrature detection signal output from the data storage circuit 12 based on the symbol timing information b 'input from the symbol timing detection circuit 14, and as a result, receives the received data c'
Is output. Further, depending on the system configuration, a frame timing detection circuit for detecting the reception timing of the base station signal of the own station may be required, but is not shown here.

Next, the operation of the conventional accumulation batch demodulation receiver will be described with reference to FIG. The modulated wave received by the wireless digital communication receiver passes through the quadrature detector and is output to the A / D conversion circuit 11 as a quadrature detection signal a 'of analog data. The A / D conversion circuit 11 performs A / D conversion on the input quadrature detection signal a 'together with oversampling. The A / D conversion circuit 11 has an A / D
By the conversion, the quadrature detection signal a ′ is converted into digital data sample data and output to the data storage circuit 12.

The data storage circuit 12 receives and stores all the sample data, and outputs the sample data to the demodulation circuit 13 and the symbol timing detection circuit 14. On the other hand, when the sample data is input, the symbol timing detection circuit 14 detects the symbol timing from the oversample timing based on the sample data using a symbol timing detection method such as MAM. The detection result is output to the data storage circuit 12 as symbol timing information b '.

The demodulation circuit 13 performs demodulation processing such as symbol judgment or decoding on the input sample data according to the symbol timing information b ', and outputs received data c'. The above is the operation of the conventional accumulation batch demodulation receiver.

In constructing the accumulation batch demodulation receiver, a DSP (Digital Signal Processor) or the like is often used in design. By using DSP,
Data processing in the data storage circuit and the symbol timing detection circuit can be collectively processed, and processing efficiency is improved.

Next, an accumulation batch demodulation receiver including a reception baseband circuit as shown in FIG.
The operation when applied to an A (Time Division Multiple Access) system will be described with reference to FIG. FIG.
FIG. 2 is a processing flowchart in a reception baseband circuit of a conventional accumulation batch demodulation receiver. 8, the first stage shows the time table of the quadrature detection signal, and the second and third stages show the processing flow of the baseband circuit of the accumulation batch demodulation receiver of FIG. Here, Td indicates the local station frame time, and Td
u indicates the other station frame time.

In the TDMA system, a multi-channel modulated baseband signal is transmitted alternately every unit time, that is, one frame at a time. Among them, the receiver selects and receives only its own frame and performs demodulation processing. In the conventional accumulation batch demodulation receiver, the above-described operation is performed every time the own station frame is received.

More specifically, the receiver outputs a quadrature detection signal each time it receives its own frame (see the first stage in FIG. 8), and the A / D conversion circuit 11 converts the quadrature detection signal into a digital signal. Then, the data is output as sample data, and the data storage circuit 12 stores the sample data for each frame (A in the second and third rows in FIG. 8). A in FIG. 8 indicates data accumulation.

Further, the symbol timing detection circuit 14 detects the symbol timing based on the sample data (B in the second and third stages in FIG. 8) and outputs the detection result to the demodulation circuit 13 as symbol timing information b '. B in FIG. 8 represents symbol timing detection by MAM.

The demodulation circuit 13 performs demodulation processing such as decoding of the inputted quadrature detection signal based on the symbol timing information (C in the second and third stages in FIG. 3) and outputs received data c '. C in FIG. 8 represents a decoding process other than MAM. The receiver repeats these series of processes until the communication ends. The above is the operation when the conventional accumulation batch demodulation receiver is applied to a 4-channel TDMA system.

As shown in FIG. 8, in the conventional accumulation batch demodulation receiver, the symbol timing detection processing and the demodulation processing are performed in series. As shown in the flowchart of the second stage in FIG. 8, the baseband circuit demodulates the own station frame during the time when the other station frame is being transmitted (the other station frame time Tu in FIG. 8). Is completed, the delay time until the reception data is obtained is within the total time of the frame times of all the stations (time Td + Tu in FIG. 8, hereinafter referred to as TDMA frame time).

However, if the processing performed by the baseband circuit becomes complicated, there may be a case where it takes more than one TDMA frame time before the demodulation processing of the own station frame Td in the receiving baseband circuit is completed.

In this case, it is necessary to design the receiver so as to provide a plurality of demodulation processing systems of the reception baseband circuit, as shown in the flowchart of the third stage in FIG. In the case of the flow chart of the third stage in FIG. 8, the delay time until a baseband signal is obtained is equal to or longer than 2 TDMA frame times per processing system. From this, it can be seen that shortening the symbol timing detection processing and demodulation processing time (B + C) directly leads to a reduction in the delay of the received data output.

[0032]

However, the conventional accumulation batch demodulation receiver requires a large amount of calculation processing when performing symbol timing detection processing such as MAM, and it is difficult to reduce the delay time of output of received data. There was a problem.

In the MAM symbol timing likelihood function described above, multiplication and addition are performed twice for each sample. Therefore when performing 16-fold oversampling for 20 symbols _{(M = 16, N a =} 2
0), a total of 1280 calculations are required for multiplication and addition. In this case, assuming that a DSP operating at 20 MHz is used for a receiver, a calculation time by oversampling alone results in a processing time of 64 μsec or more.

In recent years, digital radio communication has come to cope with the sophistication of error correction processing accompanying the improvement of communication quality and the addition of adaptive automatic equalization processing for fading. There is a demand for reducing the processing time required for the processing. For this reason, in the conventional accumulation batch demodulation receiver, wasting time of several tens of microseconds is fatal in reducing the delay time of the output of received data.

On the other hand, there is a method of determining symbol timing in real time by using an analog filter in combination without using digital signal processing.
There is a drawback that the adaptability to the environment where the delay modulation wave exists and the resistance to noise are lower than MAM.

The present invention has been made in view of the above circumstances, and has as its object to provide a reception baseband circuit capable of reducing the delay of reception data due to digital signal processing.

[0037]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems of the prior art comprises a receiving baseband circuit for converting a quadrature detection signal into a digital signal, and reading and decoding symbol timing data. And
A demodulation circuit for obtaining received data and outputting a frame timing, and a symbol timing detection circuit for detecting a symbol timing of a quadrature detection signal converted into a digital signal are provided. The symbol timing detection circuit is required for writing according to the frame timing. A write signal generation circuit for generating a simple control signal, a multiport memory for writing a quadrature detection signal converted into a digital signal in accordance with a control signal required for writing, and reading data based on information required for reading, and a number of oversamples An eye opening point detection circuit that detects, as an eye opening point, the oversampling timing at which the symbol timing likelihood takes the maximum value among the oversamplings in the sample, and reads the symbol timing sample data according to the eye opening point. An output latch for outputting a selection signal, a write signal generation circuit outputs an address and a write clock to the input side of the multiport memory as control signals required for writing, and a demodulation circuit outputs a control signal required for reading. Outputs the address and the read clock to the output side of the multi-port memory. The multi-port memory reads the sample data of the symbol timing to the demodulation circuit according to the control signal necessary for reading from the demodulation circuit and the selection signal from the output latch. Therefore, the delay time of the output of the received data of the demodulation circuit can be reduced.

[0038]

Embodiments of the present invention will be described with reference to the drawings. The receiving baseband circuit according to the embodiment of the present invention includes a conversion circuit that converts a quadrature detection signal into a digital signal, a demodulation circuit that reads and decodes symbol timing data, obtains reception data, and outputs frame timing. A symbol timing detection circuit for detecting a symbol timing of the quadrature detection signal converted into a digital signal, the symbol timing detection circuit comprising: a write signal generation circuit for generating a control signal required for writing according to the frame timing; A multiport memory that writes a quadrature detection signal converted to a digital signal in accordance with a required control signal and reads data based on the information required for reading, and the maximum symbol timing likelihood among the oversamples within the number of oversamples Take over And eye opening point detection circuit for detecting a sample timing as the eye opening point, and has an output latch for outputting a selection signal for reading out sample data of the symbol timing in accordance with the eye opening point. As a result, the symbol timing detection processing can be performed without delaying the output of the received data. The conversion circuit in the claims corresponds to the A / D conversion circuit 41 in FIG.

The configuration of the reception baseband circuit according to the embodiment of the present invention will be described with reference to FIG. FIG.
FIG. 2 is a configuration block diagram of a reception baseband circuit according to the embodiment of the present invention. As shown in FIG. 1, the baseband unit of the accumulation batch demodulation receiver using the symbol timing detection circuit of the present embodiment includes an A / D conversion circuit 41, a symbol timing detection circuit 42, and a demodulation circuit 43. It is configured.

The symbol timing detection circuit 42
Is, as shown in FIG. 1, a multi-port memory 421,
It comprises a write signal generation circuit 422, an eye opening point detection circuit 423, and an output latch 424.

Each part in FIG. 1 will be specifically described. A
The / D conversion circuit 41 receives an analog quadrature detection signal a output from a quadrature detector (not shown), performs digital conversion together with oversampling, and outputs the digital data to the symbol timing detection circuit 42 as sample data b.

The symbol timing detection circuit 42 outputs
When the sample data b output from the D conversion circuit 41 is input and the read control signal e is input from the demodulation circuit 43, the sample data corresponding to the symbol timing is detected after detecting the symbol timing based on the sample data b. The symbol timing data information f is output to the demodulation circuit 43. Here, the read control signal e includes information of a read clock and a read address to the multiport memory 421.

The demodulation circuit 43 outputs a read control signal e to the symbol timing detection circuit 42, and as a result, inputs the symbol timing data information f output from the symbol timing detection circuit 42. Further, the demodulation circuit 43 receives the symbol timing data information f
, And demodulates the received data g as a result. When receiving the own station frame, the demodulation circuit 43 outputs frame timing information h indicating the head of the frame to be received to the symbol timing detection circuit 42.

The multiport memory 421 transfers the sample data b output from the A / D conversion circuit 41 to the port 1
When the control signal e is input to the port 2 side, the symbol timing data information f is output to the demodulation circuit 43 from the port 2 side.

The multiport memory 421 has a port 1
And two data input / output ports, port 2, from which data to be written to the multiport memory 421 is inputted from port 1, and data read from the multiport memory 421 is outputted from port 2.
Port1 of the multiport memory 421 of the present embodiment
A / D conversion circuit 41 and write signal generation circuit 422
However, the demodulation circuit 43 and the output latch 424 are connected to port2.

In the port 1 of the multiport memory 421, the write control signal c output from the write signal generation circuit 422 and the sample data b output from the A / D conversion circuit 41 are input. As a result, the multiport memory 421 The sample data b is stored. Here, the write control signal c includes information of a write clock and a write address to the multiport memory 421.

In port2, the output latch 424
And the read control signal e output from the demodulation circuit 43. The multiport memory 421 determines the address of the symbol timing data based on the information and sets the address to be readable.
The read data is output to the demodulation circuit 43 as symbol timing data f.

Upon receiving the frame timing information h output from the demodulation circuit 43, the write signal generation circuit 422 converts the write control signal c to the multiport memory 421.
Is output to port1.

The eye opening point detection circuit 423 is provided with an A /
When the sample data b output from the D conversion circuit 41 and the frame timing information h output from the demodulation circuit 43 are input, the symbol timing is detected by the MAM based on the sample data b, and the symbol timing information of the detection result is output. Output to the output latch 424.

When inputting the symbol timing information from the eye opening point detection circuit 423, the output latch 424 calculates MAM information d including the address of the multiport memory 421 corresponding to the symbol timing, and outputs it to the port 2 of the multiport memory 421. I do.

Next, the operation of the storage batch demodulation receiver using the reception baseband circuit of the present embodiment applied to a 4-channel TDMA system will be described with reference to FIGS. 1, 3 and 4. I do. FIG. 3 is a processing flowchart of the reception baseband circuit of the present embodiment, and FIG. 4 is a detailed view of access timing of the multiport memory.

First, the demodulation circuit 43 outputs a frame timing signal h to the symbol timing detection circuit 42 at the timing of transmitting its own frame by wireless communication (see the frame timing stage in FIG. 4). In the symbol timing detection circuit 42, the frame timing signal h is input to the write signal generation circuit 422 and the eye opening point detection circuit 423 to activate both circuits.

The write signal generation circuit 422 to which the frame timing signal h has been input outputs the write control signal c to the port 1 of the multiport memory 421. The write signal generation circuit 422 outputs the write control signal c including the write clock and the write address for the number of oversamplings per symbol, that is, four times, to the multiport memory 421 during the transmission of the own frame (see FIG. 4). port1 write clock, port1
(See write address column.)

The receiver outputs a quadrature detection signal a from the quadrature detector to the A / D conversion circuit 41 every time it receives its own frame. The A / D conversion circuit 41 converts the input quadrature detection signal into a digital signal together with the oversampling, and outputs it to the symbol timing detection circuit 42 as sample data b.

The sample data b output from the A / D conversion circuit 41 is input to the port 1 of the multiport memory 421 and the eye opening point detection circuit 423 in the symbol timing detection circuit 42.

The sample data b input to the port 1 of the multiport memory 421 is synchronized with the write clock of the write control signal c output from the write signal generating circuit 422, and the specified write address is written to the multiport memory 421. Is stored. In the present embodiment, the sample data for one frame is stored in the multiport memory 421 in order from the head address.

The eye opening point detection circuit 423 detects the symbol timing using MAM based on all the input sample data b. The eye opening point detection circuit 423 outputs the symbol timing detection result to the output latch 424 as symbol timing information.

When the symbol timing information is input, the output latch 424 calculates a lower address on the multiport memory 421 corresponding to the symbol timing, and uses this as MAM information d, and outputs the PoM of the multiport memory 421.
Output to rt2. As shown in FIG. 3, the timing of outputting the symbol timing information to the output latch 424 may be any time after the symbol timing detection processing is completed and immediately before the reception of the next own station frame (FIG. 3).
Of the MAM information output timing shown in FIG.

In this embodiment, since the oversampling rate is quadrupled, one of the four sample data included in one symbol is regarded as the symbol timing. Therefore, the multiport memory 42
In order to specify the address of the symbol timing data in 1, it is necessary to set the lower two bits of the address.
Similarly, if the oversampling rate is 8 times, the lower 3 bits must be set, and if the oversampling rate is 16 times, the lower 4 bits must be set.

Hereinafter, the result of symbol timing detection by the eye opening point detection circuit 423 and the MAM will be described with reference to FIG.
The relationship with information will be described. FIG. 2 is a diagram showing a relationship between a symbol timing detection result by MAM and a multiport memory address.

The eye opening point detection circuit 423 determines the A / A
All sample data 4 output from the D conversion circuit 41
Based on b, the timing at which the eye opening is maximized by MAM processing, that is, the symbol timing is detected. M
In the AM processing, the symbol timing likelihood function L
Calculate _MAM (m). In the present embodiment, since the oversampling rate is four times, the timing value m is, for example, assuming that each value of m = 00, 01, 10, 11 is taken periodically, and calculate.

The calculation result is as shown in the lower left graph of FIG. 2. Since the timing of m = 00 coincides with the maximum point of the eye opening and the value of L _MAM (m) takes the maximum value, the symbol timing is calculated. You can see that there is. Therefore, the eye opening point detection circuit 423 outputs m to the output latch 424 as symbol timing information.

The output latch 424 calculates the lower address on the multiport memory 421 corresponding to the symbol timing based on the input symbol timing information. In this embodiment, since the multiport memory 421 stores the sample data from the head of the address,
The symbol timing information directly indicates the lower 2 bits of the address. The above is the result of the symbol timing detection by the eye opening point detection circuit 423 and the MAM.
Relationship with information.

In the multiport memory 421, when the MAM information d is input to the port 2, the data at the address specified by the MAM information d is set to be readable.
Further, the demodulation circuit 43 outputs the read control signal e to the symbol timing detection circuit 42 after one symbol time of the baseband signal has elapsed from the output of the frame timing signal h (see the port 2 read clock stage in FIG. 4).

The read control signal e is output from the symbol timing detection circuit 42 to the p of the multiport memory 421.
ort2. Here, the read control signal e is used as read address information as the multiport memory 421.
The bit value of the top address of the above read data (hereinafter,
(Referred to as read start address information).

Next, the multiport memory 421 calculates the address of the symbol timing data by integrating the read head address information and the MAM information, reads the data of the corresponding address, and outputs the data of the corresponding address from the port 2 to the demodulation circuit 43 as the symbol timing data f. Output. For example,
When the read start address information included in the read control signal e is set to “00” and the MAM information d is “00”, “00” + “00” = “0000”
Therefore, the data at the address “0000” on the multiport memory 421 is the symbol timing data f
Is output to the demodulation circuit 43.

The demodulation circuit 43 continues to output a read control signal e including different read start address information to the multiport memory 421 until the last address of the multiport memory 421 is reached, and reads out all symbol timing data. .

To explain using the above example of reading the symbol timing data, the demodulation circuit 43 reads the symbol timing data of the address “0000”, and after a lapse of one symbol time, reads the head address information “01”. The control signal e is output to the port 2 of the multiport memory 421.

In the multiport memory 421, the already input MAM information “00” and the newly input read control signal e are integrated, and the result is “01” + “00” = “010”.
Therefore, the data at address “0100” is output to the demodulation circuit 43 as symbol timing data f.

Thereafter, the demodulation circuit 43 increases the value of the read start address information until all the symbol timing data of its own frame are input, and outputs a read control signal e including this information to the multiport memory 421. When all the symbol timing data is read, the multi-port memory 421 deletes all the stored sample data.

The demodulation circuit 43 performs decoding processing such as frame synchronization and demodulation based on all the input symbol timing data f, outputs received data g, and outputs symbol data for the next own station frame. For detection, a frame timing signal h is output to the symbol timing detection circuit 42, and the above operation is repeated. The above is the operation when the accumulation batch demodulation receiver using the reception baseband circuit according to the present embodiment is applied to a 4-channel TDMA system.

The processing flow of the reception baseband circuit according to the present embodiment is as shown in FIG. 3, and each device of the reception baseband circuit performs processing in parallel without delay. Therefore, according to the reception baseband circuit of the present embodiment, the demodulation processing performed by the demodulation circuit is affected as compared with the conventional reception baseband circuit that performs symbol timing detection-demodulation processing in series. There is an effect that the symbol timing detection processing can be performed without any processing.

Further, since the delay time required to obtain the received data of the own station frame can be converged within one TDMA frame time, only one set of the demodulation processing system of the receiving baseband circuit is required, and the development cost of the circuit can be reduced. This has the effect of saving installation space.

[0074]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An application example of the reception baseband circuit of the present embodiment will be described with reference to FIG. In the reception baseband circuit of this embodiment, if the write signal generation circuit 422 outputs the write control signal c to the eye opening point detection circuit 423, the write signal generation circuit 422 shares the address of the multi-port memory 421. This makes it possible to directly specify the address of the symbol timing data in the multiport memory 421.

Therefore, the sample data and the address are input to the write signal generation circuit 422 at the timing of the oversampling similarly to the multiport memory 421, and the write signal generation circuit 422 outputs the multiport memory 421 as the symbol timing information. Of the output latch 424.
It is not necessary to calculate the lower bits of the address on the multiport memory 421 in the above.

Also, since the multiport memory 421 does not need to calculate the address of the symbol timing data, the read control signal e from the demodulation circuit 43 does not need to specify the read start address information. It is possible to output all the symbol timing information f with only one initial input. Also, the read control signal e output from the demodulation circuit 43
Need not include the read start address information.

According to this application example, in addition to the effects of the invention described with reference to FIGS. 1 to 4, the number of times of outputting the read control signal e from the demodulation circuit 43 can be reduced.
3, the time required for reading and demodulating the sample data can be reduced, and as a result, the delay time of receiving data output can be further reduced.

In the reception baseband circuit of the present embodiment and the application example, MAM is used as a symbol timing detection method.
Is used, but a WDM system, a ZCM system, or another system may be used. Further, in order to improve the efficiency of the symbol timing detection process, the reception baseband circuit may be designed using a DSP.

[0079]

According to the present invention, the write processing of the received sample timing data, the symbol timing detection processing for detecting the point at which the eye opening becomes the maximum point from the sample timing data, and the sample timing data of the symbol timing are read out. Since the demodulation processing for decoding is performed by a reception baseband circuit that performs each processing in parallel, the symbol timing detection processing can be performed without affecting the demodulation processing, and the output of received data by the demodulation processing can be performed without delay. effective.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a reception baseband circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a symbol timing detection result by MAM and a multiport memory address.

FIG. 3 is a processing flowchart of a reception baseband circuit according to the present embodiment.

FIG. 4 is a detailed diagram of access timing of a multiport memory.

FIG. 5 is a diagram illustrating a relationship between a quadrature detection signal and a sample timing in an oversampling operation.

FIG. 6 is an explanatory diagram showing a constellation in an oversampling operation.

FIG. 7 is a configuration diagram of a reception baseband circuit of a conventional accumulation batch demodulation receiver.

FIG. 8 is a processing flowchart in a reception baseband circuit of a conventional accumulation batch demodulation receiver.

[Explanation of symbols]

11, 41: A / D conversion circuit, 12: Data storage circuit, 13, 43: Demodulation circuit, 14, 42: Symbol timing detection circuit, 421: Multi-port memory,
422: write signal generation circuit, 423: eye opening point detection circuit, 424: output latch

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (4)

[Claims] 1. A conversion circuit for converting a quadrature detection signal into a digital signal, a demodulation circuit for reading and decoding symbol timing data to obtain received data and outputting a frame timing, and a quadrature converted to the digital signal. A symbol timing detection circuit for detecting a symbol timing of the detection signal, wherein the symbol timing detection circuit generates a control signal required for writing according to the frame timing, and a control signal required for writing. A multiport memory that writes a quadrature detection signal converted to a digital signal and reads data according to the information required for reading, and an oversample timing that takes the maximum symbol timing likelihood among the oversamples within the number of oversamples A reception baseband circuit, comprising: an eye opening point detection circuit that detects a signal as an eye opening point; and an output latch that outputs a selection signal for reading sample data of symbol timing according to the eye opening point. 2. A write signal generation circuit outputs an address and a write clock to a data input side of a multiport memory as control signals required for writing, and a demodulation circuit outputs an address and a read clock as control signals required for read. Outputting to the data output side of the multi-port memory, the multi-port memory reads symbol-timing sample data to the demodulation circuit based on a control signal necessary for reading from the demodulation circuit and a selection signal from the output latch. The receiving baseband circuit according to claim 1, wherein 3. A write signal generation circuit outputs an address and a write clock to a data input side of a multi-port memory as control signals necessary for writing, and outputs the address to an eye opening point detection circuit. An opening point detection circuit detects an eye opening point using the address, a demodulation circuit outputs a read clock as a control signal required for reading to a data output side of the multiport memory, and the multiport memory outputs 2. The reception baseband circuit according to claim 1, wherein sample data at symbol timing is read out to the demodulation circuit in accordance with a control signal required for reading out from the demodulation circuit and a selection signal from the output latch. 4. The eye opening point detection circuit uses a MAN system, a WDM system, or a ZCM system to detect an eye opening point.
A receiving baseband circuit as described.