JP2001298191A - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applicable to active devices such as MOSFETs (insulated gate type field effect transistors), IGBTs (conductivity modulation type MOSFETs), and bipolar devices, and passive devices such as diodes. The present invention relates to a vertical power semiconductor device that achieves both high performance and large current capacity.

In general, a semiconductor device has an electric power applied to only one side of a substrate.
Horizontal element with poles and vertical with electrodes on both sides of substrate
They can be roughly classified into elements. The vertical element has a drift current when turned on.
Direction of flow and depletion due to reverse bias voltage when off
The direction in which the layer extends is the thickness direction (vertical direction) of the substrate.
You. For example, FIG. 13 shows a normal planar n-channel vertical
It is sectional drawing of a MOSFET. This vertical MOSFET
Is a low-resistance n with which the drain electrode 18 on the back side is in conductive contact.
⁺High resistance n formed on drain layer 11 ⁻Dray
Drift layer 12 and the surface layer of drift layer 12
P-base region as a selectively formed channel diffusion layer
Region (p well) 13 and its surface in p base region 13
High impurity concentration n selectively formed on the side⁺Source area
14 and high impurity to ensure ohmic contact
Substance concentration p⁺Contact region 19 and p base region 13
Among n⁺Sandwiched between the source region 14 and the drift layer 12
Provided on the gated film via the gate insulating film 15
A gate electrode layer 16 such as a recon, and n⁺Source area 14 and
And p⁺A source that makes conductive contact with both surfaces of the contact region 19
And a source electrode layer 17.

In such a vertical element, a high-resistance n
^- portion of the drain-drift layer 12 is extended MOSFET acts as a region for flowing a drift current in the vertical direction when the on-state, the depletion layer depth direction from the pn junction between the p base region 13 is the off state And depletion to increase the breakdown voltage. Reducing the thickness (current path length) of the high-resistance n ^- drain / drift layer 12 has the effect of lowering the substantial on-resistance (drain-source resistance) of the MOSFET because the drift resistance is reduced in the on state. However, in the off state, the extension width of the drain-base depletion layer extending from the pn junction between the p-base region 13 and the n ^- drain / drift layer 12 is reduced, so that the depletion electric field strength is the maximum of silicon ( (Critical) Since the electric field intensity is quickly reached, the breakdown occurs before the drain-source voltage reaches the design value of the element withstand voltage, and the withstand voltage (drain-source voltage) decreases. Conversely, when the n ^- drain / drift layer 12 is formed thick, a high breakdown voltage can be achieved, but the on-resistance is inevitably increased and the on-loss is increased. That is, there is a trade-off relationship between the on-resistance (current capacity) and the withstand voltage. It is known that this relationship also holds true for semiconductor elements such as IGBTs, bipolar transistors, and diodes having a drift layer.

As a solution to this problem, a semiconductor device having a parallel pn structure in which an n-type region having a high impurity concentration and a p-type region having a high impurity concentration are alternately and repeatedly repeated as a vertical drift portion is disclosed in EP0053854 and USP5216.
275, USP 5,438,215, JP-A-9-26631
1, and JP-A-10-223896.

FIG. 14 is a sectional view showing an example of a vertical MOSFET disclosed in US Pat. No. 5,216,275. FIG.
The difference in structure from the semiconductor device of No. 3 is that the drain / drift portion 22 is uniform and has a single n ⁻ conductivity type layer (impurity diffusion layer).
Instead, a parallel pn structure is obtained in which a vertical layered n-type drift circuit region 22a and a vertical layered p-type partition region 22b are alternately repeated to form a multiple junction.
A p-type partition region 22b is connected to the well bottom of the p-base region 13, and an n-type drift circuit region 22a is connected between the well ends of the adjacent p-base regions 13 and 13. Even if the impurity concentration of the parallel pn structure of the drain / drift portion 22 is high, in the off state, the depletion layer expands in both lateral directions from each pn junction oriented in the vertical direction of the parallel pn structure, and the entire drift portion 22 becomes early. Depletion, the breakdown voltage can be increased. Note that a semiconductor device having such a parallel pn structure drain portion 22 is hereinafter referred to as a super junction semiconductor device.

[0006]

In the above-described super junction semiconductor device, the parallel p-type semiconductor device directly under a plurality of p base regions 13 (device active regions) formed in the surface layer portion is provided.
Although the withstand voltage can be ensured in the drain / drift portion 22 having the n-type structure, the depletion layer from the pn junction of the outermost p base region 13 spreads outward and deep into the substrate in the withstand voltage structure around the drain / drift portion 22. Difficultly, the depletion electric field intensity quickly reaches the critical electric field intensity of silicon, so that the withstand voltage decreases in the withstand voltage structure.

Here, in order to ensure the withstand voltage in the breakdown voltage structure of the outermost p base region 13, a guard ring is formed on the surface side of the breakdown voltage structure as well-known depletion electric field control means. It is conceivable to apply the known field plate above. However, by forming the drift portion 22 having the parallel pn structure, the drift portion
In 2, it is expected that a high breakdown voltage can be expected, but in order to secure the breakdown voltage of the breakdown voltage structure, it is increasingly necessary to modify the depletion field strength by adding external guard rings and field plates to the optimal structure by external addition. It is increasingly difficult, the reliability of each semiconductor element is poor, and since the electric field intensity cannot be controlled without being depleted in a deep part away from the guard ring, it cannot keep up with the high withstand voltage in the drift part 22, and as a whole, It becomes difficult to achieve a well-balanced and high breakdown voltage of the element, and the function of the super junction semiconductor element cannot be sufficiently brought out. In addition, additional steps such as mask formation, impurity introduction and diffusion, or metal deposition and patterning for realizing the structure are required.

On the other hand, in a power semiconductor device,
In order to increase the channel width and increase the current capacity, the p-base region 13 and the gate electrode layer 16 are elongated in plan view as annular or striped cells. Layer 17 has a p
It is connected to the n ⁺ source region 14 and the p ⁺ contact region 19 through a connection hole or a connection groove on the base region 13 and is formed as a planar continuous layer that covers each gate electrode layer 16 with an interlayer insulating film interposed therebetween. . The peripheral end of the planar continuous layer generally protrudes outside the drift portion 22 as a field plate for reducing electric field concentration (not shown). In addition, the gate electrode layer 16 of each cell is connected to a gate extraction electrode (bonding pad), and the gate extraction electrode has a defect in a middle portion, a corner portion, or a central portion of one side of the planar continuous layer that is the source electrode layer 17. It is located on a part of the insulating film, and at least a part thereof is close to or surrounded by the field plate part of the source electrode layer 17 (not shown).

In a superjunction semiconductor device in which the drift portion 22 has a parallel pn structure, dynamic dynamics that occur when a reverse bias voltage is generated in a state where carriers remain at the moment of interruption.
Avalanche breakdown (dynamic droop surrender)
In the drift portion 22, the depletion layer expands rapidly even at a low reverse bias voltage (about 50 V), so that it is relatively unlikely to occur.
Even if the dynamic avalanche breakdown occurs in any part on the main surface side of the drift part 22, the contact part of the source electrode layer 17 in the distributed arrangement for each cell is always close to the part where it occurs. Therefore, the generated excess holes are quickly pulled out to the source power supply via the contact portions.

However, the portion immediately below the gate extraction electrode and the portion immediately below the field plate of the source electrode layer 17 are located at positions off the drift portion and are locally n-type regions. Is delayed more than the drift part, carriers are likely to remain, and dynamic avalanche breakdown is likely to occur. In addition, if the dynamic avalanche breakdown occurs immediately below the gate extraction electrode or immediately below the field plate of the source electrode layer 17, the excess holes generated temporarily accumulate at the interface between the gate extraction electrode and the insulating film. After that, simultaneous discharge is performed toward the field plate portion of the source electrode layer 17 surrounding the gate extraction electrode, which causes element destruction due to heat generation or the like. The avalanche breakdown resistance becomes low or the breakdown voltage becomes unstable.

In view of the above problems, the first aspect of the present invention
An object of the present invention is to provide a semiconductor device capable of making the breakdown voltage of the outer peripheral portion larger than that of the drift portion without forming a guard ring or a field plate on the substrate surface.

A second object of the present invention is to suppress dynamic avalanche breakdown in a portion directly below an electrode layer for on / off control such as a gate extraction electrode layer or in a portion immediately below a field plate, thereby achieving stable operation. It is an object of the present invention to provide a semiconductor device capable of ensuring a high withstand voltage and achieving high dynamic avalanche breakdown resistance.

[0013]

The present invention has the following means. First, a semiconductor device according to the present invention comprises a first conductively connected active portion formed on a first main surface side of a substrate.
An electrode layer, a second electrode layer conductively connected to a first conductivity type low resistance layer formed on the second main surface side of the substrate, and an active portion and a low resistance layer, A vertical drift portion which causes a drift current to flow in the vertical direction and is depleted in an off state; and an on / off control formed at the first main surface via an insulating film and at least partially adjacent to the first electrode layer. And a vertical second conductive type in which the vertical drift portion is oriented in the thickness direction of the substrate and a vertical first conductivity type region in which the vertical drift portion is oriented in the thickness direction of the substrate. A first parallel pn structure is formed by alternately and repeatedly joining regions. The first means of the present invention can be applied to a vertical active semiconductor device having three or more terminals. Here, for example, in the case of an n-channel type MOSFET, the active portion includes a source region, a channel diffusion region layer, and the like, the first electrode layer is a source electrode layer, the second electrode layer is a drain electrode layer, A gate extraction electrode is used as an external connection electrode layer. In the case of a bipolar transistor, the second electrode layer is an emitter or a collector, and is a third electrode layer for on / off control.

First, in order to solve the first problem,
The present invention provides a pressure-resistant structure that is interposed between a first main surface and a low-resistance layer around a vertical drift portion and is substantially a non-conductive area in an on state and depleted in an off state in a thickness direction of a substrate. A second parallel pn structure is formed by alternately and repeatedly joining a vertical first conductivity type region oriented in a vertical direction and a vertical second conductivity type region oriented in the thickness direction of the substrate.

Since the second parallel pn structure is arranged in the breakdown voltage structure around the drift portion, in the off state, the depletion layer extends to both sides from the multiple pn junction surfaces, and is not limited to the drift portion. Depletion from the top to the outside or to the deep portion in the direction of the second main surface, the breakdown voltage increases. Also, the length of the side of the active portion is smaller than the length of a straight line of electric force reaching the first conductive type low-resistance layer on the second main surface side from the active portion on the first main surface side via the drift portion. Even if the second parallel pn structure and the drift portion of the breakdown voltage structure have the same impurity concentration, the curved lines of electric force from the portion to the first conductivity type low-resistance layer via the breakdown voltage structure portion are longer than the curve. Since the depletion electric field strength of the second parallel pn structure of the withstand voltage structure is lower than that of the drift portion, the withstand voltage of the withstand voltage structure is higher than the withstand voltage of the drift portion. Therefore, even in a super-junction semiconductor device employing the first parallel pn structure for the drift portion, the withstand voltage of the surrounding withstand voltage structure portion is sufficiently ensured. Therefore, the degree of freedom in designing a super-junction semiconductor device is increased, and the super-junction semiconductor device can be put to practical use.

Second, in order to solve the above second problem, the present invention provides a vertical first conductivity type region in which a portion immediately below a third electrode layer for on / off control is oriented in a thickness direction of a substrate. And a vertical second conductivity type region oriented in the thickness direction of the substrate alternately and repeatedly to form a third parallel pn structure.
The pn repetition pitch of the third parallel pn structure is narrower than the pn repetition pitch of the first parallel pn structure. In the case where the end of the first electrode layer is close to the third electrode layer for on / off control, “the portion directly below the third electrode layer” means “directly below the end of the first electrode layer”. It also includes parts.

The third electrode layer for on / off control is located on the insulating film at a part of the first electrode layer where a part of a side, a corner or a center is missing, and at least a part of the third electrode layer is the first electrode layer. However, since the portion immediately below the third electrode layer also has a parallel pn structure, and the pn repetition pitch thereof is smaller than the pn repetition pitch of the drift portion,
The depletion layer per unit area is more likely to expand in the portion immediately below the third electrode layer than in the drift portion, and the element breakdown voltage is not determined by the portion directly below the third electrode layer. At the moment of the cutoff, the expansion of the depletion layer immediately below the third electrode layer is faster than that of the drift portion, the electric field strength can be reduced, and carriers are locked out to the drift portion side. Dynamic avalanche breakdown is less likely to occur. Therefore, the dynamic avalanche breakdown occurs in the drift portion, the dynamic avalanche breakdown in the portion directly below the third electrode layer can be suppressed, a stable breakdown voltage can be secured, and a high dynamic avalanche breakdown can be achieved. Breakdown resistance can be obtained.

Here, when the impurity concentration of the third parallel pn structure immediately below the third electrode layer is lower than the impurity concentration of the first parallel pn structure, the expansion of the depletion layer is further expanded. Dynamic avalanche breakdown is less likely to occur. Of course, even when the pn repetition pitch of the third parallel pn structure of the withstand voltage structure portion is equal to or wider than the pn repetition pitch of the first parallel pn structure of the drift portion, the impurity concentration of the third parallel pn structure is relatively small. Is set lower than the impurity concentration of the first parallel pn structure, dynamic avalanche breakdown is less likely to occur.

It is desirable that the pn repetition pitch of the second parallel pn structure is narrower than the pn repetition pitch of the first parallel pn structure, and the impurity concentration of the second parallel pn structure is the first parallel pn structure. It is desirable to lower the impurity concentration. This is because the withstand voltage can be determined by the first parallel pn structure of the drift portion, and dynamic avalanche breakdown hardly occurs in the withstand voltage structure portion.

Further, in the configuration in which the first main surface side of the third parallel pn structure is covered with the second conductivity type well region that is conductively connected to the first electrode layer, each vertical pn structure of the third parallel pn structure is turned off when off. The second conductivity type region is surely reverse biased, the depletion layer easily spreads in the depth direction from the pn junction of the second conductivity type region, and the portion immediately below the third electrode layer has a high breakdown voltage, and is more dynamic. Since avalanche breakdown hardly occurs, avalanche withstand capability can be improved. Moreover, in the event that dynamic avalanche breakdown occurs immediately below the third electrode layer, the excess holes generated do not accumulate at the interface between the external connection electrode layer and the insulating film, and are used for carrier extraction. Since the element is pulled out to the first electrode layer through the functioning second conductivity type well region, the element is not destroyed due to heat generation or the like.

Here, focusing on the second conductivity type well region covering the first main surface side of the third parallel pn structure, the second conductivity type well region is located on the first main surface side of the third parallel pn structure. When the third parallel pn structure is partially covered, not only is it difficult to deplete the entire third parallel pn structure, but also the electric field concentration is likely to occur on the curved surface at the well end in the second conductivity type well region.
Dynamic avalanche breakdown easily occurs at the pn junction corresponding to the boundary between the structure and the first parallel pn structure.

Therefore, it is desirable that the third parallel pn structure adopt a structure connected to the bottom of the second conductivity type region except for both ends of the well. In such a case, the entire third parallel pn structure can be uniformly depleted. When the third electrode layer is located in the middle of one side or at the corner of the first electrode layer, which part of the well end of the second conductivity type region is the end of the first parallel pn structure of the drift portion or When the third electrode layer is connected to the end of the second parallel pn structure of the breakdown voltage structure portion and the third electrode layer is located at the center of the first electrode layer, any of the well ends of the second conductivity type region Since the portion is connected to the end of the first parallel pn structure of the drift portion, the third
The pn junction corresponding to the boundary between the parallel pn structure and the first parallel pn structure is connected to the well region of the second conductivity type, so that the occurrence of dynamic avalanche breakdown can be suppressed to the drift portion, and Since the pn junction corresponding to the boundary between the parallel pn structure and the second parallel pn structure is also connected to the second conductivity type well region, a stable breakdown voltage can be secured. In particular, it is desirable that a vertical second conductivity type region is disposed at the extreme end of the first parallel pn structure, and this is connected to the well end side of the second conductivity type well region. This is because charge balance with the vertical first conductivity type region at the end of the adjacent third parallel pn structure can be achieved.

A first parallel pn structure and the second parallel pn structure
The structures may be arranged in parallel or orthogonally. In addition, the first parallel pn structure and the third parallel pn structure may be arranged in parallel or orthogonally. The vertical first conductivity type region and the vertical second conductivity type region constituting the first, second, and third parallel pn structures can be formed in a stripe shape in plan view. The second-conductivity-type region may not be in the form of a layer, but at least one may be in the form of a column, and may be arranged at a three-dimensional lattice point such as a three-dimensional lattice or a three-dimensional lattice. Since the ratio of the pn junction area per unit volume is increased, the breakdown voltage is improved.
The first conductivity type region and the vertical second conductivity type region may each be a continuous diffusion region having a uniform impurity distribution. At least one of the vertical first conductivity type region and the vertical second conductivity type region is in the thickness direction of the substrate. It is desirable to form an association structure in which a plurality of diffusion unit regions discretely embedded in the substrate are interconnected. This is because the formation of the vertical parallel pn structure itself becomes very easy. In such a case, each diffusion unit region has a density distribution in which the central portion becomes the maximum density portion and the density gradually decreases outward.

The first means is applied to a vertical active element having three or more terminals since the third electrode layer is an electrode layer for ON / OFF control. The present invention can also be applied to the vertical passive element.

That is, irrespective of the presence or absence of the third electrode layer in the first means, the second means comprises at least the first electrode layer of the first parallel pn structure or the second parallel pn structure. The pn repetition pitch of the parallel pn structure in a portion immediately below the peripheral portion is narrower than the pn repetition pitch of the first parallel pn structure. The peripheral portion of the first electrode layer generally functions as a field plate.

According to such a means, it is possible to improve the withstand voltage in the portion immediately below the peripheral portion of the first electrode layer and to improve the dynamic avalanche breakdown resistance.
The impurity concentration of the parallel pn structure in the portion immediately below the
Is desirably lower than the impurity concentration of the parallel pn structure.

The first part of the parallel pn structure immediately below the first part is
It is desirable that the main surface side be covered with a second conductivity type well region that is conductively connected to the first electrode layer. This is because the portion immediately below the second conductive type well region can be reliably set to a reverse bias when the device is turned off, and furthermore, if dynamic avalanche breakdown occurs immediately below the portion, the second conductive type well region functioning as a carrier withdrawal is formed. Carriers can be extracted to the first electrode layer via the first electrode layer, and device destruction can be prevented.

In the first parallel pn structure, an endmost vertical second conductivity type region adjacent to the parallel pn structure immediately below the portion is connected to a well end of the second conductivity type well region. Is desirable. A dynamic avalanche break occurs because the pn junction between the endmost vertical first conductivity type region of the parallel pn structure immediately below and the endmost vertical second conductivity type region is connected to the second conductivity type well region. Down hardly occurs. In addition, charge balance can be obtained.

[0029]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following, a layer or a region with an abbreviation of n or p means a layer or a region using electrons or holes as majority carriers, respectively. The superscript + indicates a relatively high impurity concentration, and the superscript − indicates a relatively low impurity concentration.

Embodiment 1 FIG. 1 is a schematic plan view showing a vertical MOSFET device chip according to Embodiment 1 of the present invention, in which a source electrode layer and a gate extraction electrode on a surface active portion and an insulating film of a MOSFET are shown. Omitted. FIG. 2 is an enlarged plan view showing a rectangular range A1-A2-A3-A4 in FIG. FIG. 3 is a cross-sectional view showing a state cut along the line A5-A6 in FIG.

The n-channel vertical MOSFET of the present embodiment has a first parallel pn structure drain / electrode formed on a low-resistance n ⁺⁺ drain layer (drain / contact layer) 11 to which the backside drain electrode 18 is in conductive contact. Drift part 1;
A high impurity concentration p base region (p well) 13 selectively formed as an annular or striped cell on the surface side of drift portion 1, and selectively formed on the surface side in p base region 13. N ⁺ source region 14 having a high impurity concentration, a gate electrode layer 16 such as polysilicon provided on a substrate surface with a gate insulating film 15 interposed therebetween, and a p-type base through a contact hole formed in interlayer insulating film 20. A source electrode 17 that is in conductive contact with both the p ⁺ contact region 19 and the n ⁺ source region 14 in the region 13 is provided. An n ⁺ source region 14 is formed shallowly in a well-shaped p base region 13 to constitute a double diffusion type MOS portion.
Here, the surface active portion of this element corresponds to the p base region 13 and the source region 14.

The drain drift portion 1 has n⁺⁺Do
N-type epitaxy on the substrate of the rain layer 11
Formed as a thick layer with several layers of
Vertical n-type drift circuit in the thickness direction of the substrate
Region 1a and p-type partition region 1 having a layered vertical shape in the thickness direction of the substrate
b is alternately repeated to form a multiple junction. This example
In this case, the n-type drift circuit region 1a is
Is located between the well ends of the substrate region 13, and the upper end is located on the substrate surface.
Surface channel region 12e, the lower end of which is n ⁺⁺Dre
It is in contact with the in-layer 11. Also, the p-type partition region 1b
Have their upper ends removed from both ends of the well of the p base region 13a.
Contact the bottom of the well and the lower end is n⁺⁺For the drain layer 11
In contact. This example has a withstand voltage of 600V class.
Layer thickness of the drift circuit region 1a and the p-type partition region 1b.
Are both 8 μm and the depth is about 40 μm. each
The impurity concentration is 2.5 × 10^Fifteencm^-3But 1 ×
10^{1 5}~ 3 × 10^FifteenIs fine.

As shown in FIG. 1, around the drift portion 1 which mainly occupies the chip plane, between the substrate surface and the n ⁺⁺ drain layer 11, there is a non-circuit region in the on state and a non-conductive region in the off state. A withstand voltage structure portion (element outer peripheral portion) 2 to be depleted is formed. The pressure-resistant structure 2 is formed by alternately repeating a layered vertical n-type region 2a oriented in the thickness direction of the substrate and a layered vertical p-type region 2b oriented in the thickness direction of the substrate. It has a second parallel pn structure.
The first parallel pn structure of the drift section 1 and the second parallel pn structure of the breakdown voltage section 2 are arranged in parallel. That is, the layer surface of the first parallel pn structure of the drift portion 1 and the breakdown voltage structure portion 2
In the second parallel pn structure, the layer surfaces are parallel to each other, and the boundary portions thereof are regions of opposite conductivity types, and pn repetition is continuous. As shown in FIG. 2, the pn repeating end face in the second parallel pn structure of the breakdown voltage structure section 2 is connected to the pn repeating end face in the second parallel pn structure of the drift section 1. In this example, the pn repetition pitch in the second parallel pn structure of the breakdown voltage structure section 2 is the drift section 1
Is smaller than the pn repetition pitch in the first parallel pn structure. Further, the impurity concentration of the breakdown voltage structure 2 is lower than the impurity concentration of the drift portion 1. Both the vertical n-type region 2a and the vertical p-type region 2b have a thickness of 4 μm.
And the depth is about 40 μm. Although each impurity concentration of ^{2.5 × 10 1 3 cm -3,} 2 × 10 14 cm
^-3 or less is sufficient. A thermal oxide film or an oxide film (insulating film) 23 made of phosphor silica glass (PSG) is formed on the surface of the pressure-resistant structure 2 for surface protection and stabilization.

Outside the breakdown voltage structure 2, an n-type channel stopper region 24 oriented in the thickness direction of the substrate and having a relatively large layer thickness is arranged. This n-type channel stopper region 24 is electrically connected to a peripheral electrode 26 having the same potential as the drain voltage via an n ⁺ contact region 25.

The drift portion 1 occupies a rectangular area on the chip plane, and a gate extraction electrode 30 is located on the interlayer insulating film 20 at one halfway of one side. Around the gate extraction electrode 30, a source electrode layer 17 projects as a field plate 17a. Immediately below the gate extraction electrode 30, a portion immediately below the first parallel pn structure of the drift portion 1 and the second parallel pn structure of the breakdown voltage structure portion 2 has a third parallel pn structure. This third parallel pn structure is a layered vertical n-type structure oriented in the thickness direction of the substrate.
Mold region 3a and a layered vertical p oriented in the thickness direction of the substrate.
The mold region 3b is alternately repeated to form a multiple junction. The first parallel pn structure of the drift portion 1 and the third parallel pn structure of the portion 3 immediately below are arranged in parallel with each other. That is, the layer surface of the first parallel pn structure of the drift portion 1 and the layer surface of the third parallel pn structure of the immediately lower portion 3 are in parallel with each other, and at the boundary portions thereof, regions of opposite conductivity type are formed, and pn The repetition is continuous. In addition, the second parallel p
The layer surface of the n structure and the layer surface of the third parallel pn structure of the portion 3 immediately below are parallel to each other, and at the boundary portions thereof, regions of opposite conductivity type are formed, and pn repetition is continuous.

In this example, the pn repetition pitch in the third parallel pn structure of the lower portion 3 is narrower than the pn repetition pitch in the first parallel pn structure of the drift portion 1, and Is the same as the pn repetition pitch in the parallel pn structure. The impurity concentration of the third parallel pn structure in the portion immediately below 3 is lower than the impurity concentration of the drift portion 1, and the second parallel pn structure of the breakdown voltage structure 2.
It is the same as the impurity concentration of the structure. Both the n-type region 3a and the p-type region 3b have a layer thickness of 4 μm and a depth of about 40 μm. Each impurity concentration is 2.5 × 10 ¹³ cm ^−3.
However, it may be 2 × 10 ¹⁴ cm ⁻³ or less.

The surface side of the third parallel pn structure of the portion 3 directly below is covered with a p-type well region 40, and the p-type well region 40 is connected to a contact region via a p ⁺ contact region 41 formed therein. Electrically connected. Immediately below part 3
The third parallel pn structure is connected to the bottom of the p-type well region 40 except for the well end. The outermost vertical partition region 1 b of the drift portion 1 is connected to the well bottom near the inner well end of the p-type well region 40, and the pn junction J between the adjacent immediately lower portion 3 and the n-type region 3 a is formed in the p-type region 40. Connected to well bottom. The outermost p-type region 2 b of the breakdown voltage structure 2 is connected to the p-type well region 40 near the outer well end.

The above parallel pn structure has an association structure in which at least one of a vertical p-type region and a vertical n-type region is interconnected by a plurality of diffusion unit regions discretely embedded in the thickness direction of the substrate. It is desirable that This is because the formation of the parallel pn structure itself becomes very easy. In such cases,
Each diffusion unit region has a density distribution in which the central portion becomes the maximum density portion and the density gradually decreases outward.

Next, the operation of this embodiment will be described. When a predetermined positive potential is applied to the gate electrode layer 16, the n-channel type MOSFET is turned on, and the channel from the source region 14 through the inversion layer induced on the surface of the p base region 13 immediately below the gate electrode layer 16. Electrons are injected into the region 12e, and the injected electrons reach the n ⁺⁺ drain layer 11 through the drift circuit region 1a, and the drain electrode 18
And the source electrode 17 conducts.

When the positive potential applied to the gate electrode layer 16 is removed, the MOSFET is turned off and the p base region 13 is turned off.
The inversion layer induced on the surface of the gate electrode disappears, and the drain electrode 18
And the source electrode 17 is cut off. Further, when the reverse bias voltage (source-drain voltage) is large in the off state, a depletion layer is formed in the p base region 13 and the channel region 12e from the pn junction between the p base region 13 and the channel region 12e. While expanding and depleting, each partition region 1b of the drift portion 1 is electrically connected to the source electrode 17 via the p base region 13, and each drift circuit region 1a of the drift portion 1 is connected to the n ⁺⁺ drain layer 11. Since the depletion layer from the pn junction between the partition region 1b and the drift circuit region 1a is extended to both the partition region 1b and the drift circuit region 1a, Depletion of part 1 is accelerated. Therefore,
Since the high withstand voltage of the drift portion 1 is sufficiently ensured, the impurity concentration of the drift portion 1 can be set high, and a large current capacity can be ensured.

Here, a second parallel pn structure is formed in the withstand voltage structure 2 around the drift portion 1 in this embodiment. Some p-type regions 2b in this second parallel pn structure are:
It is electrically connected to the source electrode 17 via the p base region 13 or the p type region 40, and each n type region 20a is n ⁺⁺
Since it is electrically connected to the drain electrode 18 via the drain layer 11, the depletion layer extended from the pn junction of the breakdown voltage structure portion 2 is substantially depleted over the entire thickness of the substrate. For this reason, it is possible to deplete not only the surface side of the breakdown voltage structure portion 2 but also the outer peripheral portion and the deep portion of the substrate as in the case of the surface guard ring structure and the field plate structure. Strength can be greatly reduced, and high withstand voltage can be secured. Therefore, a high breakdown voltage of the super junction semiconductor element can be realized.

In particular, in this example, the second parallel pn structure of the breakdown voltage structure 2 has a smaller pn repetition pitch and a lower impurity amount (impurity concentration) than the first parallel pn structure of the drift portion 1. Therefore, the breakdown voltage structure portion 2 is depleted earlier than the drift portion 1, so that the breakdown voltage reliability is high. Since the pn repetition end face of the withstand voltage structure section 2 is connected to the pn repetition end face of the drift section 1, the depletion rate of the withstand voltage structure section 2 is high. Therefore, even in a super-junction semiconductor device employing the first parallel pn structure for the drift portion 1, the withstand voltage of the surrounding withstand voltage structure portion 2 is sufficiently ensured by the second parallel pn structure. In addition, the first parallel pn structure of the drift portion 1 can be easily optimized, the degree of freedom in designing a super junction semiconductor device can be increased, and the super junction semiconductor device can be put to practical use.

In this embodiment, the third parallel pn structure in the portion 3 immediately below the gate extraction electrode 30 has a smaller pn repetition pitch and a lower impurity concentration than the first parallel pn structure in the drift portion 1. Therefore, the depletion layer per unit area is more likely to expand in the portion 3 immediately below the gate extraction electrode 30 than in the drift portion 1, and the element breakdown voltage is not determined by the portion 3 directly below. In particular, the third parallel pn
Since the structure has a smaller pn repetition pitch than that of the first parallel pn structure of the drift portion 1, any p
Since the mold region 3b is also connected along the depth direction of the p-type partition region 1b of the drift portion 1, the potential does not float and the depletion of the portion 3 immediately below can be guaranteed. In other words, in the case where the first parallel pn structure of the drift portion 1 and the third parallel pn structure of the immediately lower portion 3 are in an mutually parallel arrangement, p
Even when the mold region 40 does not exist, in order to conduct the source potential to any of the p-type regions 3 b of the immediately lower portion 3, the pn repetition pitch of the third parallel pn structure of the immediately lower portion 3 is set to the first value of the drift portion 1 It is desirable to make the pitch narrower than the pn repetition pitch of the parallel pn structure. Further, at the time of cutoff, the expansion of the depletion layer in the immediately lower portion 3 is faster than that in the drift portion 1 so that the electric field intensity can be reduced and carriers are locked out to the drift portion 1 side, so that a dynamic avalanche breakdown occurs in the immediately lower portion 3 This makes it possible to secure a stable withstand voltage and obtain a high dynamic avalanche breakdown resistance.

Further, since there is a p-type region 40 electrically connected to the source electrode 17 on the surface side of the third parallel pn structure, each p-type region 2 of the third parallel pn structure is turned off when off.
b is surely reverse-biased, and the depletion layer easily spreads in the depth direction from the pn junction of the p-type region 2b.
In this case, the breakdown voltage is high, and the dynamic avalanche breakdown is more difficult to occur, so that the avalanche resistance can be improved. In addition, if dynamic avalanche breakdown occurs in the portion 3 directly below, the excess holes generated are drawn out to the source electrode 17 via the p-type region 40, so that element destruction due to heat generation or the like does not occur. .

Since the third parallel pn structure of the lower portion 3 is connected to the well bottom excluding the well end of the p-type well region 40, the entire third parallel pn structure can be uniformly depleted. Further, the endmost vertical partition region 1 of the drift portion 1
b is connected to the bottom of the well near the inner well end of the p-type well region 40, and the pn with the n-type region 3a of the immediately lower portion 3 adjacent thereto.
The junction J is connected to the well bottom of the p-type well region 40. For this reason, electric field concentration is likely to occur at the inner well end, and dynamic avalanche breakdown is likely to occur. However, the occurrence can be suppressed to the drift section 1 and the end of the adjacent third parallel pn structure can be prevented. Can be balanced with the n-type region 3b.

The n-type regions 1a to 3a and the p-type regions 1b to 3b of the above-mentioned parallel pn structures 1 to 3 are formed in a planar stripe shape as shown in FIG. Alternatively, p-type regions 1b 'to 3b' may be formed in a planar lattice in n-type regions 1a 'to 3a' as the ground. p
The mold regions 1b 'to 3b' are columnar in the depth direction of the substrate.
At least one of the p-type regions 1b 'to 3b' has an association structure in which a plurality of diffusion unit regions discretely embedded in the thickness direction of the substrate are interconnected. And has a density distribution that gradually decreases outward. Of course, the n-type region may be formed in a planar lattice in the p-type region as the ground.

When the breakdown voltage class is changed, the length in the depth direction of each parallel pn structure may be changed to a length corresponding to the breakdown voltage class. For example, in case of 900V class, 60μ
m. Further, in the second and third parallel pn structures, the pitch is narrowed and the impurity concentration is low. However, even if the pitch is the same, only the concentration needs to be lowered. The impurity concentration of the second and third parallel pn structures is
Is preferably about 1/5 to 1/100 of the impurity concentration of the parallel pn structure.

[Embodiment 2] FIG. 5 is an enlarged plan view showing an upper left area of a chip in a vertical MOSFET according to an embodiment 2 of the present invention. As in FIG. 2, a rectangular area A in FIG.
It corresponds to 1-A2-A3-A4.

The structure of the second embodiment differs from that of the first embodiment in that the second parallel pn structure of the breakdown voltage structure 2 and the third parallel pn structure of the portion 3 immediately below the first parallel pn structure of the drift portion 1 are different from each other. Are arranged orthogonally to. That is, the layer surface of the first parallel pn structure of the drift portion 1 is orthogonal to the layer surface of the third parallel pn structure of the portion 3 immediately below, and the layer surface of the first parallel pn structure of the drift portion 1 and the breakdown voltage structure portion 2 Are parallel to the layer plane of the second parallel pn structure. Also, the pn repetition pitch of the parallel pn structure of the portion 3 immediately below and the withstand voltage structure portion 2 is smaller than the pn repetition pitch of the first parallel pn structure of the drift portion 1, which is about half. Further, compared to the impurity concentration of the drift portion 1, the portion 3 immediately below and the breakdown voltage
Has a low impurity concentration. In FIG. 5, the repetitive end face of the third parallel pn structure immediately below the portion 3 and the drift portion 1
Are connected to the p-type partition region 1bb. For this reason,
The first parallel pn structure of the drift portion 1 and the third
And the parallel pn structure is orthogonal to each other,
Even when the p-type well region 40 does not exist, the portion 3
Considering the curvature line at the boundary between the semiconductor device and the drift portion 1, even when the p-type region 40 does not exist, the source potential is reduced to the portion 3
It is possible to conduct electricity to the p-type region 3b, and it is not essential that the pn repetition pitch in the portion 3 immediately below is narrower than the pn repetition pitch in the drift portion 1.

Even in such an arrangement relationship of the three parallel pn structures, the same operation and effect as in the first embodiment can be obtained.

Third Embodiment FIG. 6 is a schematic plan view showing a chip of a vertical MOSFET device according to a third embodiment of the present invention. A source electrode layer and a gate extraction electrode on a surface activated portion of a MOSFET and an insulating film. Is omitted. FIG.
It is a top view which expands and shows the rectangular range B1-B2-B3-B4 in FIG. A cross-sectional view showing a state cut along a line B5-B6 in FIG. 7 is the same as FIG.

In this embodiment, the third parallel pn structure of the portion 3 immediately below the gate extraction electrode is located at the corner of the first parallel pn structure of the drift portion 1. The layer surface of the first parallel pn structure of the drift portion 1 and the third parallel p
The layer surface of the drift structure 1 is parallel to the layer surface of the first parallel pn structure, and the layer surface of the first parallel pn structure of the drift unit 1 is parallel to the layer surface of the second parallel pn structure. The first part of the drift part 1
In comparison with the pn repetition pitch of the parallel pn structure, the pn repetition pitch of the parallel pn structure of the portion 3 immediately below and the breakdown voltage structure 2 is narrower, which is about half. Further, the impurity concentration of the portion 3 immediately below and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1. In particular, the third
Has a smaller pn repetition pitch than the first parallel pn structure of the drift portion 1, even if the p-type well region 40 does not exist,
Since the mold region 3b is also connected along the depth direction of the p-type partition region 1b of the drift portion 1, the potential does not float and the depletion of the portion 3 immediately below can be guaranteed.

As described above, even when the portion 3 immediately below the gate extraction electrode is located at the corner of the drift portion 1, the same operation and effect as those of the first embodiment can be obtained.

[Embodiment 4] FIG. 8 is an enlarged plan view showing an upper left area of a chip in a vertical MOSFET according to an embodiment 4 of the present invention. As in FIG. 7, a rectangular area B in FIG.
It corresponds to 1-B2-B3-B4.

In this embodiment, as in the third embodiment, the third parallel pn structure of the portion 3 immediately below the gate extraction electrode is located at the corner of the first parallel pn structure of the drift portion 1. The layer surface of the first parallel pn structure of the drift portion 1 is orthogonal to the layer surface of the third parallel pn structure of the portion 3 immediately below, and the layer surface of the first parallel pn structure of the drift portion 1 and the breakdown voltage structure portion 2
Are orthogonal to the layer plane of the second parallel pn structure. Also, the pn repetition pitch of the parallel pn structure of the portion 3 immediately below and the withstand voltage structure portion 2 is smaller than the pn repetition pitch of the first parallel pn structure of the drift portion 1, which is about half. Further, the impurity concentration of the portion 3 immediately below and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1.

As described above, even when the portion 3 immediately below the gate extraction electrode is located at the corner of the drift portion 1, the same operation and effect as those of the first embodiment can be obtained. In the corner portion, the boundary between the drift portion 1 and the immediately lower portion 3 is connected with a curve in order to avoid electric field concentration as much as possible, so that the pn repeating end face of the third parallel pn structure in the immediately lower portion 3 is It is difficult to connect to one p-type partition region.
Although it depends on the curvature of the curve, the pn repetition pitch in the immediately lower portion 3 is rather pn in the drift portion 1.
If it is wider than the repetition pitch, the p-type well region 40
, The source potential can be conducted to any of the p-type regions 3b in the portion 3 immediately below.

Fifth Embodiment FIG. 9 is a schematic plan view showing a chip of a vertical MOSFET device according to a fifth embodiment of the present invention. Is omitted. FIG.
10 is an enlarged plan view showing a rectangular range C1-C2-C3-C4 in FIG. FIG. 11 shows C5-C6 in FIG.
It is sectional drawing which shows the state cut | disconnected along the line.

The third parallel pn structure of the portion 3 immediately below the gate extraction electrode 30 in this example is located at the center of the first parallel pn structure of the drift portion 1. The layer surface of the first parallel pn structure of the drift portion 1 and the third parallel p
The layer surface of the drift structure 1 is parallel to the layer surface of the first parallel pn structure, and the layer surface of the first parallel pn structure of the drift unit 1 is parallel to the layer surface of the second parallel pn structure. The first part of the drift part 1
In comparison with the pn repetition pitch of the parallel pn structure, the pn repetition pitch of the parallel pn structure of the portion 3 immediately below and the breakdown voltage structure 2 is narrower, which is about half. Further, the impurity concentration of the portion 3 immediately below and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1. The third parallel pn structure of the lower portion 3 is more p-type than the first parallel pn structure of the drift portion 1.
Since the n-repetition pitch is narrow, the p-type well region 40
Does not exist, since any p-type region 3b of the immediately lower portion 3 is connected along the depth direction of the p-type partition region 1b of the drift portion 1, no potential floating state occurs, and Depletion can be guaranteed.

In this embodiment, the gate extraction electrode 30 does not have the outer peripheral field plate 17 a of the source electrode layer 17,
Since the third parallel pn structure in the lower portion 3 is covered with the p-type region 40, the outer peripheral field plate 17 is located in the region surrounded by the inner peripheral field plate 17b.
The second parallel pn structure immediately below a is covered with a p-type well region 50, and ap ⁺ contact region 51 conductively connected to a source electrode is formed in the p-type well region 50. Depletion immediately under the outer peripheral field plate 17a can be accelerated, and dynamic avalanche breakdown resistance can be secured. Further, since the endmost partition region 1b of the first parallel pn structure is connected to the well bottom of the p-type well region 50, charge balance with the endmost n-type region 2a of the adjacent second parallel pn structure is made. Can be taken.

Embodiment 6 FIG. 12 shows Embodiment 4 of the present invention.
FIG. 3 is an enlarged plan view showing an upper left area of a chip in the vertical MOSFET according to the first embodiment. Similar to FIG. 10, it corresponds to the rectangular range C1-C2-C3-C4 in FIG.

In this embodiment, as in the fifth embodiment, the third parallel pn structure in the portion 3 immediately below the gate extraction electrode is located at the center of the first parallel pn structure in the drift portion 1. The layer surface of the first parallel pn structure of the drift portion 1 and the layer surface of the third parallel pn structure of the portion 3 immediately below are orthogonal to each other, and the layer surface of the first parallel pn structure of the drift portion 1 and the breakdown surface structure 2 The layer plane of the second parallel pn structure is orthogonal to the layer plane. Also,
Compared with the pn repetition pitch of the first parallel pn structure of the drift portion 1, the pn repetition pitch of the parallel pn structure of the portion 3 immediately below and the withstand voltage structure portion 2 is smaller, which is about half. Further, the impurity concentration of the portion 3 immediately below and the breakdown voltage structure portion 2 is lower than the impurity concentration of the drift portion 1.

Since the pn repeating end face of the third parallel pn structure in the lower portion 3 is connected to one p-type partition region, even when the p-type well region 40 does not exist, the source potential is reduced to any one of the lower portion 3. It becomes possible to conduct electricity to the p-type region 3b. Then, even when the portion 3 immediately below the gate extraction electrode is located at the corner of the drift portion 1, the same operation and effect as those of the fifth embodiment can be obtained.

In each of the above embodiments, a double diffusion type vertical MOSFET has been described.
The present invention can be applied not only to vertical active devices having three or more terminals such as (conductivity modulation type MOSFET) and bipolar transistors but also to passive devices having two terminals.

[0064]

As described above, according to the present invention, the withstand voltage structure around the drift portion has a parallel pn structure.
The portion immediately below the third electrode layer and the portion immediately below the peripheral portion of the first electrode layer also have a parallel pn structure, and the pn of the portion immediately below the parallel
It is characterized in that the repetition pitch is made narrower than that of the drift portion, or the impurity concentration in the portion immediately below it is lower than that of the drift portion,
The following effects are obtained.

(1) Since the parallel pn structure is disposed around the drift portion, in the off state, the depletion layer expands from the multiple pn junction surfaces, and is not limited to the vicinity of the active portion, but also in the outward direction or the second direction. Since the main surface side is depleted, the breakdown voltage of the breakdown voltage structure is higher than the breakdown voltage of the drift portion. Therefore, even in a super-junction semiconductor device employing a vertical parallel pn structure for the drift portion, the withstand voltage of the withstand voltage structure portion is sufficiently guaranteed, so that the parallel pn structure of the drift portion can be easily optimized. The degree of freedom in designing the super-junction semiconductor element is increased, and the super-junction semiconductor element can be put to practical use. When the parallel pn structure of the breakdown voltage structure has a smaller amount of impurities than the parallel pn structure of the drift portion, or when the parallel pn structure of the breakdown voltage structure has a smaller pn repetition pitch than the parallel pn structure of the drift portion, The withstand voltage can be surely made higher than the withstand voltage of the drift portion, and the reliability is improved.

(2) The portion immediately below the third electrode layer or the portion immediately below the peripheral portion of the first electrode layer also has a parallel pn structure, and the pn repetition pitch is smaller than the pn repetition pitch of the drift portion. Therefore, the depletion layer per unit area is easy to expand in the portion directly below the drift portion, and is not determined in the portion directly below. In addition, at the moment of cutoff, the expansion of the depletion layer in the immediately lower part is faster than in the drift part, the electric field intensity can be reduced, and carriers are locked out to the drift part side, so that dynamic avalanche breakdown is less likely to occur in the immediately lower part. Become. Therefore, the dynamic avalanche breakdown occurs in the drift portion, the dynamic avalanche breakdown in the portion directly below can be suppressed, a stable breakdown voltage can be secured, and a high dynamic avalanche breakdown resistance can be obtained. be able to. The same effect can be obtained when the impurity concentration in the portion immediately below is lower than that in the drift portion.

(3) In the configuration in which the first main surface side of the immediately lower portion is covered with the second conductivity type well region that is conductively connected to the first electrode layer, each of the vertical parallel second structures of the third parallel pn structure is turned off.
The conductivity type region is surely reverse biased, and the depletion layer easily spreads in the depth direction from the pn junction of the second conductivity type region.
Since a high breakdown voltage is provided immediately below the electrode layer and dynamic avalanche breakdown is more unlikely to occur, the avalanche withstand capability can be improved. In addition, if a dynamic avalanche breakdown occurs immediately below the third electrode layer, the dynamic avalanche breakdown is drawn to the first electrode layer via the second conductive type well region functioning as a carrier withdrawal. No element destruction is caused.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a chip of a vertical MOSFET device according to Embodiment 1 of the present invention.

FIG. 2 is an enlarged plan view showing a rectangular range A1-A2-A3-A4 in FIG.

FIG. 3 is a cross-sectional view showing a state cut along line A5-A6 in FIG. 2;

FIG. 4 is a plan view showing a modification of the parallel pn structure in the first embodiment.

FIG. 5 is an enlarged plan view showing an upper left area of a chip in a vertical MOSFET according to a second embodiment of the present invention.

FIG. 6 is a schematic plan view showing a chip of a vertical MOSFET device according to a third embodiment of the present invention.

FIG. 7 is an enlarged plan view showing a rectangular range B1-B2-B3-B4 in FIG. 6;

FIG. 8 is an enlarged plan view showing an upper left area of a chip in a vertical MOSFET according to Embodiment 4 of the present invention.

FIG. 9 is a schematic plan view showing a chip of a vertical MOSFET device according to Embodiment 5 of the present invention.

FIG. 10 is an enlarged plan view showing a rectangular range C1-C2-C3-C4 in FIG. 9;

11 is a cross-sectional view showing a state cut along the line C5-C6 in FIG.

FIG. 12 is an enlarged plan view showing an upper left area of a chip in a vertical MOSFET according to Embodiment 6 of the present invention.

FIG. 13 shows a conventional vertical M having a drift layer of a single conductivity type.
FIG. 3 is a partial cross-sectional view illustrating an OSFET.

FIG. 14 is a partial cross-sectional view showing a conventional vertical MOSFET having a drift layer having a parallel pn structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Drain drift part 1a, 1a '... N-type drift circuit area 1b, 1b' ... P-type partition area 2 ... Withstand voltage structure part 2a, 2a ', 3a, 3a' ... Vertical n-type area 2b, 2b ', 3b .., 3b '... vertical p-type region 3 ... directly below the gate extraction electrode 11 ... n ⁺ drain layer 12e ... channel region 13 ... p base region (p well) with high impurity concentration 14 ... n ⁺ source region 15 ... gate insulating film Reference Signs List 16 gate electrode layer 17 source electrode 17a, 17b field plate 18 drain electrode 19, 21, 51 p ⁺ contact region 20 interlayer insulating film 24 n-type channel stopper region 25 n ⁺ contact region 26 peripheral edge Electrode 30: gate extraction electrode 40, 50: p-type well region J: pn junction

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Katsunori Ueno 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Yasuhiko Onishi No. 1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-ku, Kanagawa No. 1 Inside Fuji Electric Co., Ltd. (72) Takahiro Sato 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Tatsushi Nagaoka, No. 1 Tanabe Nitta, Kawasaki-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fuji Electric Co., Ltd.

Claims (23)

[Claims] 1. A first electrode layer conductively connected to an active portion formed on a first main surface side of a substrate and a first conductive type low resistance layer formed on a second main surface side of the substrate. A second electrode layer for conductive connection, interposed between the active portion and the low resistance layer,
A vertical drift portion in which a drift current flows in a vertical direction in an on state and is depleted in an off state; and a vertical drift portion formed on the first main surface via an insulating film, and at least partially adjacent to the first electrode layer. A vertical first conductivity type region in which the vertical drift portion is oriented in the thickness direction of the substrate, and a vertical second conductivity type region in which the vertical drift portion is oriented in the thickness direction of the substrate; In a first parallel pn structure formed by alternately and repeatedly joining the semiconductor device, wherein the semiconductor device is interposed between the first main surface and the low resistance layer around the vertical drift portion, and is substantially in an on state. In the non-circuit area, the withstand voltage structure portion that is depleted in the off state alternates between a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. The second one that is repeatedly joined A parallel pn structure, in which a portion immediately below the third electrode layer alternates between a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. A third parallel pn structure formed by joining the first parallel pn structure with the pn repetition pitch of the third parallel pn structure.
A semiconductor device characterized by being narrower than n repetition pitches. 2. The method according to claim 1, wherein said third parallel pn
A semiconductor device, wherein the impurity concentration of the structure is lower than the impurity concentration of the first parallel pn structure. 3. A first electrode layer conductively connected to an active portion formed on a first main surface side of a substrate and a first conductive type low resistance layer formed on a second main surface side of the substrate. A second electrode layer for conductive connection, interposed between the active portion and the low resistance layer,
A vertical drift portion in which a drift current flows in a vertical direction in an on state and is depleted in an off state; and an on-state portion formed on the one main surface via an insulating film and at least partially surrounded by the first electrode layer. A third electrode layer for off control, wherein a vertical first conductivity type region in which the vertical drift portion is oriented in the thickness direction of the substrate and a vertical second conductivity type region in which the vertical drift portion is oriented in the thickness direction of the substrate; In a semiconductor device having a first parallel pn structure formed by alternately and repeatedly joining, the semiconductor device is interposed between the first main surface and the low resistance layer around the vertical drift portion, and is substantially non-conductive in an on state. The withstand voltage structure portion, which is a circuit region and is depleted in the off state, alternates between a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. Second line consisting of A column pn structure, wherein a portion immediately below the third electrode layer alternates between a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. A third parallel pn structure formed by junction with the first parallel pn structure, wherein the impurity concentration of the third parallel pn structure is lower than the impurity concentration of the first parallel pn structure. 4. The semiconductor according to claim 1, wherein a pn repetition pitch of the second parallel pn structure is smaller than a pn repetition pitch of the first parallel pn structure. apparatus. 5. The semiconductor device according to claim 1, wherein the impurity concentration of the second parallel pn structure is lower than the impurity concentration of the first parallel pn structure. . 6. The third conductive pn structure according to claim 1, wherein the first main surface side of the third parallel pn structure is covered with a second conductivity type well region that is conductively connected to the first electrode layer. A semiconductor device comprising: 7. The method of claim 6, wherein the third parallel pn
A semiconductor device, wherein the first main surface side of the structure is connected to the well bottom excluding both ends of the well of the second conductivity type region. 8. The method according to claim 1, wherein the first parallel pn structure and the second parallel pn structure are connected to each other.
A semiconductor device, wherein the structure is such that the layer surfaces are arranged in parallel with each other. 9. The method according to claim 1, wherein the first parallel pn structure and the second parallel pn structure are connected to each other.
A semiconductor device, wherein the structure is such that the layer surfaces are arranged orthogonal to each other. 10. The device according to claim 1, wherein the first parallel pn structure and the third parallel pn structure are connected to each other.
A semiconductor device characterized in that the n-type structure has layer surfaces arranged in parallel with each other. 11. The method according to claim 1, wherein the first parallel pn structure and the third parallel pn structure are connected to each other.
A semiconductor device characterized in that the n-structure is such that the layer surfaces are arranged orthogonal to each other. 12. The vertical first conductivity type region and the vertical second conductivity type region constituting the first, second, and third parallel pn structures according to any one of claims 1 to 11, A semiconductor device having a stripe shape in plan view. 13. A first electrode layer conductively connected to an active portion formed on a first main surface side of a substrate and a first conductivity type low resistance layer formed on a second main surface side of the substrate. Conductive connection second
A vertical drift portion that is interposed between the active portion and the low resistance layer and that vertically flows a drift current in an on state and is depleted in an off state. A vertical first member oriented in the thickness direction of the substrate;
A first parallel pn formed by alternately and repeatedly joining a conductive type region and a vertical second conductive type oriented in the thickness direction of the substrate.
In the semiconductor device having a structure, a withstand voltage structure interposed between the first main surface and the low-resistance layer around the vertical drift portion, and is substantially a non-circuit region in an on state and depleted in an off state. A second parallel pn structure formed by alternately and repeatedly joining a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. In the first parallel pn structure or the second parallel pn structure, the pn repetition pitch of the parallel pn structure in at least a portion directly below the peripheral portion of the first electrode layer is the first pn structure.
Characterized in that the pitch is smaller than the pn repetition pitch of the parallel pn structure. 14. The parallel pn structure according to claim 13, wherein an impurity concentration of the parallel pn structure in the immediately lower portion is equal to the first parallel pn structure.
A semiconductor device having a lower impurity concentration than a structure. 15. A first electrode layer conductively connected to an active portion formed on a first main surface side of a substrate and a first conductive type low resistance layer formed on a second main surface side of the substrate. Conductive connection second
A vertical drift portion that is interposed between the active portion and the low resistance layer and that vertically flows a drift current in an on state and is depleted in an off state. A vertical first member oriented in the thickness direction of the substrate;
A first parallel pn formed by alternately and repeatedly joining a conductive type region and a vertical second conductive type oriented in the thickness direction of the substrate.
In a semiconductor device having a structure, a withstand voltage structure interposed between the first main surface and the low-resistance layer around the vertical drift portion, and is substantially a non-circuit region in an on state and depleted in an off state. A second parallel pn structure formed by alternately and repeatedly joining a vertical first conductivity type region oriented in the thickness direction of the substrate and a vertical second conductivity type region oriented in the thickness direction of the substrate. In the first parallel pn structure or the second parallel pn structure, the impurity concentration of the parallel pn structure in at least a portion directly below the peripheral portion of the first electrode layer is the first parallel pn structure.
A semiconductor device having a lower impurity concentration than an n-type structure. 16. The semiconductor according to claim 13, wherein a pn repetition pitch of the second parallel pn structure is smaller than a pn repetition pitch of the first parallel pn structure. apparatus. 17. The semiconductor device according to claim 13, wherein an impurity concentration of the second parallel pn structure is lower than an impurity concentration of the first parallel pn structure. . 18. The well of any one of claims 13 to 17, wherein the first main surface side of the parallel pn structure immediately below the portion is covered with a second conductivity type well region conductively connected to the first electrode layer. A semiconductor device comprising: 19. The second conductive type well region according to claim 18, wherein an end of the first parallel pn structure, which is the last vertical second conductive type region adjacent to the parallel pn structure immediately below, is the well end of the second conductive type well region. A semiconductor device which is connected to a unit. 20. The semiconductor device according to claim 13, wherein a peripheral portion of the first electrode layer is a field plate. 21. The method according to claim 13, wherein the first parallel pn structure and the second parallel pn structure are arranged such that their layer surfaces are parallel to each other. Semiconductor device. 22. The method according to claim 13, wherein the first parallel pn structure and the second parallel pn structure are arranged such that their layer surfaces are orthogonal to each other. Semiconductor device. 23. The vertical first conductivity type region and the vertical second conductivity type region forming the first and second parallel pn structures according to any one of claims 13 to 22, wherein A semiconductor device characterized by having a stripe shape.