JP2001292058A - Clock divider - Google Patents

Abstract

(57) [Summary] [Problem] To generate a frequency-divided clock with a high-precision duty at any frequency division set value. SOLUTION: An even / odd determination unit 201 has a frequency division set value N.
Is determined to be an even number or an odd number.
2 divides the basic clock so that both the high and low duties of the divided clock become N / 2 when the division set value N is an even number, and the basic clock is divided when the division set value N is an odd number. Frequency division is performed such that one of the high and low duties of the frequency-divided clock becomes (N + 1) / 2 and the other duty becomes (N-1) / 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock frequency dividing device for dividing a basic clock by an arbitrarily set frequency dividing value N to generate a frequency-divided clock having a predetermined frequency.

[0002]

2. Description of the Related Art As a conventional example of this kind, for example, as shown in Japanese Patent Application Laid-Open No. 5-313777, the number of pulses of a basic clock is counted, and the counting result is used as a divided value of the basic clock and the local clock. A method of dividing the frequency has been proposed.

[0003]

However, the above-mentioned conventional method aims at obtaining the same frequency from a plurality of different original oscillations. Therefore, the frequency of the original oscillation depends on the frequency of the frequency-divided clock to be obtained. In addition, when the division value setting is not an even number or is not an integer, there is a problem that the division accuracy is reduced.

Accordingly, an object of the present invention is to provide a clock frequency dividing device capable of improving the frequency dividing accuracy.

[0005]

In order to achieve the above-mentioned object, a first means is an even / odd judgment means for judging whether a frequency division set value N which is an arbitrary integer value is even or odd, and a frequency dividing means. When the set value N is an even number, the basic clock is divided so that both the high and low duties of the divided clock become N / 2, and when the divided set value N is an odd number, the basic clock is divided by the divided clock. High duty or low duty is (N + 1) /
2, a frequency dividing means for dividing the frequency so that the other duty becomes (N-1) / 2.

The second means is such that when the frequency division set value N is an odd number in the first means, the frequency dividing means divides the basic clock into high and low duty ratios of the divided clock by (N + 1) / 2.
Or (N-1) / 2, or (N-1)
And (N + 1) / 2.

The third means is characterized by further comprising means for stopping the output of the divided clock until the clock divided by the dividing means in the first and second means is stabilized.

A fourth means is the second means, wherein the even / odd number judging means outputs an odd number judging flag to the selecting means when the frequency dividing set value N is judged to be an odd number. The output means outputs a duty selection flag to the even / odd determination means.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a general clock generation circuit, FIG. 2 is a block diagram showing one embodiment of a clock frequency dividing device according to the present invention, and FIG. 3 is a basic clock, frequency setting value and frequency dividing of FIG. 6 is a timing chart showing a clock.

FIG. 1 shows a general clock generation circuit. First, to the phase comparator 103 of the PLL circuit 109, a clock fin / r obtained by dividing the basic clock fin by a dividing ratio = 1 / r by the frequency divider (/ r) 101 is applied. The phase comparator 103 compares the phase of the clock fin / r with the phase of the clock fout / n divided by the feedback frequency divider (/ n) 107. Charge pump 104
Outputs a pulse in the positive direction with respect to the reference voltage when the phase of the clock fin / r is advanced, and outputs the pulse in the negative direction when the phase of the clock fout / n is advanced, based on the comparison result. Output pulse.

A pulse having this polarity is an LPF (Low
The integrated value (voltage) is integrated by a VCO (Voltage Controlled Oscillator) 10.
6 is input. Since the VCO 106 is an element whose output frequency fout varies according to the input voltage, the clock fin
When the phase of / r is advanced, that is, when a pulse in the + direction is output, a voltage higher than the reference voltage is applied to the LPF.
The output frequency fout rises, and falls in the opposite case.

By this operation, the clocks fin / r, fo
The phase and frequency of ut / n become the same, and the output frequency fout is obtained as fout = fin × n / r. Here, the feedback frequency divider (/ n) 1
07 and the frequency divider r of the frequency divider (/ r) 101
It can be understood that the output frequency fout can be arbitrarily changed (although it is actually a discrete value) by setting.

The clock generating circuit shown in FIG. 1 further includes a clock fout and clocks fout / 2 (110) and fout / 4 (111) obtained by dividing the frequency by 1/2 and 1/4.
And one of the basic clocks fin is selected by the multiplexer 112, and the selected clock is frequency-divided by the PCLK frequency divider 113 in synchronization with the synchronization detection signal.
Clock divided by CLK frequency divider 113 and CPU
One of the clocks from 116 is selected by the multiplexer 114, and the selected clock is output via the output driver 115 as the clock PCLK.

In the first embodiment, in a clock frequency dividing device for dividing a basic clock by an arbitrarily given set value N and generating a frequency-divided clock of a predetermined frequency, a frequency division setting which is an arbitrary integer value It is determined whether the value N is an even number or an odd number. When the division setting value N is an even number, both the duty of H and L of the divided clock are set to N / 2, and when the division setting value N is an odd number, the division is performed. Either H or L duty of the clock is (N + 1) / 2, and the other duty is (N-1) / 2.
And

FIG. 2 shows an example of the frequency divider 10 shown in FIG.
1 is shown in detail. However, in FIG. 2, fin = fRE
Let F, fin / r = fDIV, r = N. First, the CPU 11
6 sets a frequency division set value N, which is an arbitrary integer value for frequency division of the basic clock frequency fREF, to the even / odd number determination unit 201 and the frequency division value calculation counter (1 / N) 202. At this time, the even / odd determination unit 201 refers to the least significant bit LSB of the set value N from the register of the CPU 116 and
When SB = 0, it is determined to be an even number, and when LSB = 1, it is determined to be an odd number. When N = even number, divided clock: H → N / 2, L → N / 2 When N = odd, divided clock: H → (N−1) / 2 + 1 = (N + 1) /
2, L → (N−1) / 2 or frequency-divided clock: H → (N−1) / 2 = (N−1) / 2,
The duty of L → (N + 1) / 2 is set in the frequency division value calculation counter 202.

FIG. 3 shows the timing at this time. The frequency of the basic clock is fREF, and the frequency of the divided clock is fD
Assuming IV, the frequency division setting value is N = fREF / fDIV. The output frequency-divided clock fDIV is cleared by setting a predetermined frequency division ratio in a register in the system to clear the counter 202 and fDIV = fREF / N.

The default output of this frequency divider is
The initial value of the register becomes the divided value of the basic clock frequency, and the divided clock is free-run output. The initial value of the register may be arbitrarily determined by the system. As described above, a frequency-divided clock can be generated with a highly accurate duty at any set value of the basic clock frequency.

<Second Embodiment> In the second embodiment,
Compared to the first embodiment, when the division setting value N is an odd number, the duty of either H or L of the divided clock: (N +
1) / 2 or (N-1) / 2 can be selected. That is, as shown by the line composed of the halftone dots in FIG. 2, when the even / odd number determination unit 201 determines that the set value N is an odd number, it outputs an odd number determination flag F1 to the CPU 116, and the CPU 116 sets the duty selection flag F2 to Even number
By outputting to the odd number judgment unit 201, (N + 1) /
2 or (N-1) / 2. In this case, the default may be set to any combination of the duties. With the above configuration, even if the set value N from the register is an odd number, the duty ratio of the divided clock can be arbitrarily changed.

<Third Embodiment> In the third embodiment,
When dividing the basic clock by the division setting value N given by an arbitrary integer value with respect to the first and second embodiments,
The time when the frequency division by the set value is completed is detected, and the detected information of the frequency division end is used for the output control of the frequency-divided clock. That is, in FIG.
When it is determined that the frequency division by the set value with respect to the basic clock is completed, the clock frequency division end detection flag F3 is set together with the frequency division clock fDIV and the frequency division clock output control circuit 20
6 is output. The divided clock output control circuit 206 is shown in FIG.
As shown in the figure, the output level of the divided clock fDIV is fixed at "L" or "H" until the flag F3 becomes valid, and when the flag F3 becomes valid, the divided clock fDIV becomes effective.
Is output. As described above, unnecessary clock output is stopped until the frequency-divided clock is stabilized, and the cause of radio interference can be eliminated.

[0020]

As described above, according to the first aspect of the present invention, when the frequency division setting value N is an even number, the basic clock is divided into both high and low duties of N / 2.
When the division setting value N is an odd number, the basic clock is divided into one of high and low duty cycles of (N + 1) / 2 and the other of (N-1) /
Since the frequency division is made to be 2, the frequency division accuracy can be improved.

According to the second aspect of the present invention, when the division setting value N is an odd number, the basic clock is set to the high level of the divided clock,
The frequency is divided so that the row duty becomes (N + 1) / 2 and (N-1) / 2, or (N-1) / 2 and (N + 1) /
Since it became possible to select whether to divide the frequency to be 2,
The duty can be arbitrarily selected and changed.

According to the third aspect of the present invention, the output of the divided clock is stopped until the frequency of the divided clock is stabilized. Can be reduced.

According to the fourth aspect of the invention, when the even / odd number determination means determines that the frequency division set value N is an odd number, it outputs the odd number determination flag to the means for selecting the odd number determination flag. Since the flag is output to the even / odd determination means, the duty ratio of the divided clock can be arbitrarily changed even when the set value N from the register is an odd number.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a general clock generation circuit.

FIG. 2 is a block diagram showing an embodiment of a clock frequency dividing device according to the present invention.

FIG. 3 is a timing chart showing a basic clock, a division setting value, and a division clock of FIG. 2;

FIG. 4 is a block diagram illustrating an embodiment of a clock frequency dividing device according to a third embodiment.

FIG. 5 is a timing chart showing a basic clock, a division setting value, a clock division end detection flag, and a division clock of FIG. 4;

[Explanation of symbols]

 116 CPU 210 Even / Odd Number Determination Unit 202 Divided Value Operation Counter 206 Divided Clock Output Control Circuit

Claims (4)

[Claims] 1. An even / odd determining means for determining whether a division setting value N which is an arbitrary integer value is an even number or an odd number. If the division setting value N is an even number, a basic clock is set to a high of the division clock. The frequency is divided so that the low duty is both N / 2. When the division setting value N is an odd number, the basic clock is divided into one of the high and low duties of the divided clock (N +
1) / 2, a frequency dividing means for dividing the frequency so that the other duty becomes (N-1) / 2. 2. When the division setting value N is determined to be an odd number by the even / odd number determination means, the frequency division means sets the basic clock to a high or low duty of the divided clock (N
+1) / 2 and (N-1) / 2, or
2. The clock frequency divider according to claim 1, further comprising means for selecting whether to divide the frequency so that (N-1) / 2 and (N + 1) / 2. 3. The clock frequency dividing device according to claim 1, further comprising: means for stopping the output of the frequency-divided clock until the clock frequency-divided by the frequency dividing means is stabilized. 4. When the even / odd number determining means determines that the frequency division set value N is an odd number, the even / odd number determining means outputs an odd number determination flag to the selection means, and the selection means sets a duty selection flag to the even number / odd number. 3. The clock frequency dividing device according to claim 2, wherein the clock frequency is outputted to an odd number judging means.