JP2001291875A - Thin film transistor, method of manufacturing the same, circuit using the same, and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor having a structure in which deterioration of characteristics is reduced, a leakage current of a TFT is reduced, and a variation in a leakage current is suppressed, a method of manufacturing the same, a circuit using the same, and a liquid crystal display device. The purpose is to provide. A thin film transistor having a structure capable of reducing deterioration of Vgs-Ids characteristics. The thin film transistor 16 has a source region 1 composed of an N-type impurity diffusion region.
7, a drain region 18 and a gate electrode 19, and a channel region 30 immediately below the gate electrode 19. Further, the source electrode 2 is formed in the source region 17 and the drain region 18 through a plurality of contact holes 20.
1 and the drain electrode 22 are connected to each other. Then, the P-type impurity diffusion region 23 is formed inside the channel region 30.
Are formed at a plurality of locations at regular intervals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor, a method of manufacturing the same, a circuit using the same, and a liquid crystal display device.

[0002]

2. Description of the Related Art Polycrystalline silicon thin film transistors (Polycrystalline Silicon Thin Films) that can be formed at low process temperatures
2. Description of the Related Art Film Transistors, so-called “low-temperature process polysilicon TFTs”, have attracted attention as elements capable of forming a high-definition liquid crystal display having a driver built on a large glass substrate.

FIG. 38 (A) and FIG. 38 (B), which is a sectional view taken along the line BB of FIG. 38, show an example of a conventional polysilicon TFT, and show a polysilicon thin film forming source and drain regions. Indicates a top gate type TFT in which a gate electrode is located on the lower side and a gate electrode is located on the upper side. This polysilicon TFT is an example of an N-channel TFT.

As shown in FIGS. 38A and 38B, a buffer layer 2 made of a silicon oxide film is formed on a glass substrate 1, and a polysilicon thin film 3 is formed thereon. Further, a gate insulating film 4 made of a silicon oxide film covering the polysilicon thin film 3 is formed, and a gate electrode 5 made of a tantalum nitride film, an aluminum (Al) film or the like is formed.
Are formed. Then, a source region 6 and a drain region 7, which are N-type impurity introduction regions, are formed in portions of the polysilicon thin film 3 other than immediately below the gate electrode. In addition, an interlayer insulating film 8 made of a silicon oxide film is formed, contact holes 9 are opened, and a source electrode 10 and a drain electrode 11 are formed.

In the field of general semiconductor devices, attention has recently been paid to the use of SOI (Silicon On Insulator) structures along with the miniaturization of devices in order to further increase the speed, lower the power consumption, and enhance the functions of the devices. Are gathering. The SOI structure is, for example, a single-crystal silicon layer formed on a surface of a silicon substrate with a silicon oxide film interposed therebetween. However, although the SOI structure has the above advantages, the effect of the substrate floating effect becomes remarkable because the transistor formation region and the supporting substrate are electrically insulated. In this case, a problem caused by the substrate floating effect is, for example, a decrease in withstand voltage between the source and the drain. This mechanism is based on the fact that holes generated in the high electric field region near the drain region accumulate below the channel and raise the potential of the channel. Therefore, a parasitic bipolar transistor with the source, channel, and drain regions as the emitter, base, and collector, respectively. Is turned on.

On the other hand, when a polysilicon TFT having a structure as shown in FIGS. 38A and 38B is used as a liquid crystal driving element, a source electrode 10 and a drain electrode 11 are used.
In the meantime, a signal voltage is applied to the gate electrode 5 and a scanning voltage is applied. In this case, it has been clarified that the same characteristic deterioration as the substrate floating effect which has been a problem in the SOI structure occurs.

[0007] Further, remarkable deterioration of the TFT has been clarified. Since the channel portion of the TFT is surrounded by the insulating film, the structure is such that heat hardly escapes. Therefore, deterioration occurs due to the heat of the TFT itself generated during operation. Such deterioration is particularly remarkable in a TFT having a large channel width.

In addition, a polycrystalline silicon TFT has a larger off-state leak current (off-state current) and a larger variation in the amount of current than a single-crystal silicon transistor. This tendency is more remarkable in a TFT formed by a low-temperature process than in a TFT formed by a high-temperature process.

For example, if the leak current (off current) of the TFT in the pixel portion is large, the luminance fluctuation of the display screen becomes large,
If the leak current (off current) varies, it becomes difficult to design the TFT.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to reduce the deterioration of characteristics and improve the TF
It is an object of the present invention to provide a thin film transistor having a structure in which T leakage current (off current) is reduced and a variation in leakage current (off current) is suppressed, a method of manufacturing the same, a circuit using the same, and a liquid crystal display device. .

[0011]

In order to achieve the above object, a thin film transistor according to the present invention comprises a channel region formed in a non-single-crystal silicon thin film on a substrate, and a channel region formed in the non-single-crystal silicon thin film. Having a first region and a second region of a first conductivity type formed to be separated from each other with the first conductivity type generated in a high electric field region near the first region or the second region. A carrier injection region into which carriers of the opposite conductivity type flow is provided.

According to the present invention, since the carrier injection region into which the hot carriers generated in the electric field region flow is provided, the injection amount of the hot carriers into the first region or the second region is smaller than that of the conventional thin film transistor. Thus, characteristic deterioration can be greatly reduced.

A thin film transistor according to the present invention comprises: a channel region formed in a non-single-crystal silicon thin film on a substrate;
A first region and a second region of a first conductivity type formed in the non-single-crystal silicon thin film so as to sandwich the channel region, and the non-single-crystal silicon between the first and second regions; And at least one third region having a conductivity type opposite to the first conductivity type formed in the thin film.

[0014] In the present invention, the plurality of third regions include:
It may be formed on the non-single-crystal silicon thin film.

The third region includes the first region and the second region.
The non-single-crystal silicon thin film may be formed between at least one of the regions and the channel region.

[0016] The third region may be formed in at least a part of the channel region.

The first conductivity type may be N-type.

The non-single-crystal silicon thin film may be a polycrystalline silicon thin film.

The polycrystalline silicon thin film having the channel region, the first region and the second region may be formed by a low temperature process.

A thin film transistor according to the present invention comprises: a channel region formed in a non-single-crystal silicon thin film on a substrate;
A first conductivity type first region and a second region formed in the non-single-crystal silicon thin film so as to sandwich the channel region, wherein at least the width of the channel region of the non-single-crystal silicon thin film is , Larger than the minimum width of the first region and the second region.

The width of the channel region is preferably 50 μm or more.

Preferably, the width of the channel region is at least 100 μm.

A thin film transistor according to the present invention comprises: a plurality of non-single-crystal silicon thin films formed on a substrate so as to intersect a gate electrode; a channel region formed in each of the non-single-crystal silicon thin films; A first conductivity type first region and a second region formed in the silicon thin film so as to sandwich the channel region therebetween; the first regions of the plurality of non-single-crystal silicon thin films and the second region; Are connected to a common electrode.

The channel width of each of the non-single-crystal silicon thin films is preferably 10 μm or less.

Preferably, a dimension between outermost sides of the plurality of non-single-crystal silicon thin films is 50 μm or more.

The length of the channel region is preferably 4 μm or less.

According to the thin film transistor of the present invention, a semiconductor thin film island provided on a substrate, a source layer and a drain layer formed by selectively introducing impurities into the semiconductor thin film island, A gate electrode layer provided facing the semiconductor thin film island, wherein at least one of the source layer or the drain layer is formed inside by a given distance from an outer edge of the semiconductor thin film island. I have.

The large leak current (off current) of a TFT is generally attributable to the "quality of crystal". However, the inventor of the present application has further studied variously, and found that “an electric field between the gate electrode and the edge of the high-concentration source or drain layer that forms a part of the outer edge (outer periphery) of the thin film island” indicates that the TFT It has an important effect on the leakage current (off current) of the semiconductor device.

That is, it was found that when the electric field applied to the source layer and the drain layer was increased, the leak current (off current) of the TFT was also increased.

Therefore, by providing a high-concentration source layer or drain layer inside the thin film island and providing a "space" at the outer edge, the space reduces the above-mentioned electric field applied to the source and drain layers. Thus, a reduction in leakage current (off current) and suppression of its variation are achieved.

In a region avoiding the source layer and the drain layer, at least a portion of the outer edge of the semiconductor thin film island overlapping with the gate electrode is an intrinsic layer into which impurities are not introduced. Good.

This clarifies that the "space" portion is an intrinsic layer (intrinsic layer). In the intrinsic layer, the depletion layer easily spreads, and this depletion layer absorbs the electric field. Therefore, the electric field applied to the high-concentration source layer / drain layer is reduced, the leak current (off current) of the TFT is reduced, and variation is suppressed.

In a region avoiding the source layer and the drain layer, at least a portion of the outer edge portion of the semiconductor thin film island which overlaps with the gate electrode has impurities of opposite conductivity type to the source layer and the drain layer. It may be composed of an introduced impurity layer and an intrinsic layer connected to the impurity layer.

For example, in the case of an NMOS transistor, at least a portion of the outer edge of the thin film island that overlaps the gate electrode has a p-layer and an i-layer (intrinsic layer). Also in this case, similarly to the case of the second aspect, the effect of relaxing the electric field can be obtained, and the leakage current (off current) can be reduced and the variation can be suppressed.

The given distance from the outer edge of the semiconductor thin film island to the source or drain is 1 μm
It is preferably at least 5 μm.

If the distance from the outer edge of the semiconductor thin film island to the source (drain) is less than 1 μm, actual processing is difficult. If the distance is more than 5 μm, the size of the semiconductor thin film island becomes large and the design specifications are not satisfied. . Therefore, the thickness is preferably 1 μm or more and 5 μm or less.

[0037] The semiconductor thin film island may be made of polysilicon formed by annealing amorphous silicon.

Polysilicon TFT by low temperature process
Since the high temperature treatment is not performed, the recovery from crystal damage is weak, and the leak current (off current) of the TFT tends to increase. Therefore, the application of the present invention is effective.

The thin film transistor may have an offset in the relative positional relationship between the gate electrode and the drain layer.

The so-called "offset structure" is effective in reducing the leak current (off current) because the gate and drain do not overlap, but on the other hand, when the offset amount is large, the on current decreases. This leads to an increase in the threshold voltage. Therefore, it is difficult to adjust the offset amount.

If the present invention is applied to a MOS transistor having an offset structure, the leak current (off current) can be effectively reduced without increasing the offset amount so much.
Further, the variation is suppressed, and thus, the securing of the on-current and the design are facilitated.

The thin film transistor may have a dual gate structure in which two gate electrodes are arranged in parallel with each other.

The MOSFET of the dual gate structure has two
In this configuration, the MOS transistors are connected in series. Then, by adopting the electric field relaxation structure of the present invention, each M
OSFET leakage current is reduced, one MOSFET
When the reduction rate (the amount of leakage current after application of the present invention / the amount of leakage current before application of the present invention) is “F (<1)”, 2
The reduction rate of the leakage current in the entire MOSFET is “F
× F ”, and the amount of leak current is further reduced as compared with the case of one MOSFET.

A thin film transistor according to the present invention comprises a semiconductor thin film island provided on a substrate, a source layer and a drain layer formed by selectively introducing impurities into the semiconductor thin film island, and an outer edge of the semiconductor thin film island. A first insulating film provided so as to overlap only with the portion, a second insulating film formed to cover the surface of the semiconductor thin film island and the first insulating film, and the second insulating film A gate electrode layer provided thereon.

According to the present invention, in order to reduce the electric field between the gate electrode and the source / drain, the first insulating film is provided so as to overlap the outer edge of the thin film island.
The distance to the edge of the gate is increased by the thickness of the insulating film. As a result, the electric field applied to the source / drain is reduced, and the leak current (off current) of the TFT decreases,
Variation is also suppressed.

A circuit according to the present invention has the above-mentioned thin film transistor.

A liquid crystal display device according to the present invention is of a type with a built-in driver circuit, and has the above-mentioned thin film transistor.

By using the thin film transistor of the present invention, it is possible to realize a liquid crystal display device having good image quality with less occurrence of circuit malfunction and the like.

In the above liquid crystal display device, it is preferable that the thin film transistor is used in a circuit section.

In the above liquid crystal display device, it is preferable that the thin film transistor is used as an analog switch of the circuit section.

A liquid crystal display device according to the present invention has the above thin film transistor in a pixel portion.

The leak current (off current) of the TFT in the pixel portion
Is reduced, and the luminance fluctuation of the display screen is reduced. Also,
Variations in the leak current (off current) of the TFT are suppressed, and the design of the active matrix substrate is easy. Therefore, a high-performance liquid crystal display device is realized.

The liquid crystal display device according to the present invention is constituted by using the above-mentioned thin film transistor.

When a peripheral circuit such as a liquid crystal driver circuit is constituted by the TFT of the present invention, a high-performance circuit can be formed. It is easy to form the circuit on an active matrix substrate. Therefore, a high-performance liquid crystal display device is realized.

In the method of manufacturing a thin film transistor according to the present invention, a channel region formed in a non-single-crystal silicon thin film on a substrate and a first region formed in the non-single-crystal silicon thin film so as to sandwich the channel region are formed. First made of conductive type
A third region of a conductivity type opposite to the first conductivity type, which is formed both in a region and a second region, and between the first region and the channel region and between the second region and the channel region; A thin film transistor forming a non-single-crystal silicon thin film on a substrate, wherein the channel region has a conductivity type opposite to the first conductivity type. Forming a third region by ion-implanting an impurity of a conductivity type opposite to the first conductivity type into a portion of the silicon thin film; and forming a gate on the third region of the non-single-crystal silicon thin film. A gate electrode forming step of forming a gate electrode through an insulating film; and a first conductivity type impurity ion-implanted with a smaller dose than the ion implanted dose in the third region forming step. First and second regions forming a first region and a second region, with a city.

In the method of manufacturing a thin film transistor according to the present invention, a channel region formed in a non-single-crystal silicon thin film on a substrate and a first region formed in the non-single-crystal silicon thin film so as to sandwich the channel region are formed. First made of conductive type
A third region of a conductivity type opposite to the first conductivity type, which is formed both in a region and a second region, and between the first region and the channel region and between the second region and the channel region; A thin film forming step for forming a non-single-crystal silicon thin film on a substrate, and forming a gate electrode on the non-single-crystal silicon thin film via a gate insulating film. And a first step using a mask material that covers the first region and the second region while using the gate electrode as a mask.
A third region forming step of forming a third region in a region adjacent to the channel region by ion-implanting an impurity of a conductivity type opposite to the conductivity type, and a dose amount during the ion implantation in the third region forming step First and second regions for forming the first region and the second region in a region adjacent to the third region of the non-single-crystal silicon thin film by ion-implanting a first conductivity type impurity with a smaller dose. Forming step.

The method of manufacturing a thin film transistor according to the present invention is used for a liquid crystal display device having a complementary thin film transistor having both P-type and N-type, and a channel region formed in a non-single-crystal silicon thin film on a substrate, A first region and a second region of a first conductivity type formed in a single-crystal silicon thin film so as to sandwich the channel region, and the non-single-crystal silicon thin film between the first region and the second region And a third region having a conductivity type opposite to the first conductivity type formed in the thin film transistor, wherein the formation of the third region comprises a conductivity type opposite to the first conductivity type. This is performed simultaneously with the formation of the first region and the second region of the transistor.

In the method of manufacturing a thin film transistor according to the present invention, a step of depositing an amorphous silicon thin film on a substrate and a step of irradiating the amorphous silicon thin film with laser light to obtain a crystallized polysilicon thin film. And, patterning the polysilicon thin film obtained by laser irradiation to form a polysilicon island,
Forming a gate insulating film on the polysilicon island, forming a gate electrode on the gate insulating film; forming an insulating layer covering at least a part of an outer edge of the polysilicon island; Forming a source layer and a drain layer by introducing an impurity into the polysilicon island using the electrode and the insulating layer as a mask; and forming a source electrode and a drain electrode.

Using the gate electrode and the insulating layer as a mask, the source layer and the drain layer can be formed inside the outer edge of the thin film island by self-alignment.

[0060]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. 1 (A) to 3 (D).

FIGS. 1A and 1B show a thin film transistor 16 according to the present embodiment. The thin film transistor 16 is, for example, a polysilicon TFT used as an analog switch of a liquid crystal display.

FIG. 1A is a plan view of the thin film transistor 16. As shown in FIG.
Has a source region 17 (first region) and a drain region 18 (second region), both of which are N-type (first conductivity type) impurity diffusion regions, and a gate electrode 19. This is an area 30.

The ratio between the channel length L and the channel width W of the thin film transistor 16 is, for example, about 5 μm / 100 μm. Further, a source electrode 21 and a drain electrode 22 are connected to the source region 17 and the drain region 18 through a plurality of contact holes 20, 20,. Then, the drain region 18, the channel region 30,
And P continuously formed over source region 17.
Type impurity diffusion regions 23 (carrier injection regions, third regions having a conductivity type opposite to the first conductivity type) are formed at a plurality of locations and at regular intervals. For example, the width of the P-type impurity diffusion region 23 is about 5 μm, and the interval between the P-type impurity diffusion regions 23 is about 5 μm.

FIG. 1B is a sectional view taken along the line II of FIG. 1A. As shown in this figure, a base insulating film 25 made of a silicon oxide film, a source,
Drain regions 17, 18 and P-type impurity diffusion region 23
Are sequentially formed. Then, a gate electrode 19 is formed thereover via a gate insulating film 27. Further, an interlayer insulating film 28 made of a silicon oxide film is formed thereon,
Contact holes 20, 20 penetrating the interlayer insulating film 28 and leading to the source region 17 and the drain region 18 are opened, and a source electrode 21 and a drain electrode 22 are formed.

Next, a method of manufacturing the thin film transistor having the above configuration will be described with reference to FIGS. The manufacturing method described below uses, for example, a CVD method instead of a thermal oxidation method for forming a gate insulating film, and manufactures at a low process temperature of 450 ° C. or less throughout the entire process. Thereby, glass can be used as the material of the substrate.

First, as shown in FIG. 2A, a film having a thickness of 100 to 50
A silicon oxide film of about 0 nm is formed to form a base insulating film 25.
And Next, an amorphous silicon thin film having a thickness of about 50 nm is formed on the entire surface of the base insulating film 25 by a CVD method using disilane (Si ₂ H ₆ ) or monosilane (SiH ₄ ) as a raw material. The polycrystal is formed by performing excimer laser annealing. Then, the polycrystalline silicon thin film 26 is patterned using a well-known photolithography / etching technique (silicon thin film forming step).

Next, as shown in FIG. 2B, after forming a photoresist pattern 29 having an opening only in a region where a P-type impurity diffusion region is to be formed, B ₂ H ₆ / H ₂ was used. The P-type impurity diffusion region 23 is formed by performing ion doping (third region formation step). The dose during ion doping is, for example, 1 to 10 ×
It is about 10 ¹⁵ atoms / cm ² . Then, after removing the photoresist pattern 29, as shown in FIG.
ECR-CVD (Electron Cyclotron ResonanceChemic
The gate insulating film 27 made of a silicon oxide film having a thickness of about 120 nm is formed by using an Al Vapor Deposition method or the like.

Next, a film thickness of 600 to 80 is formed by sputtering.
A tantalum film of about 0 nm is deposited on the entire surface, and FIG.
As shown in (1), a gate electrode 19 is formed by patterning this (gate electrode forming step). Then, as shown in FIG. 3 (B), ion doping using PH ₃ / H ₂ is performed using the gate electrode 19 as a mask, so that the source region 1 which is an N-type impurity diffusion region is formed.
7. Form the drain region 18 (first and second region forming steps). The dose during ion doping is 1-1.
The dose may be about 0 × 10 ¹⁵ atoms / cm ² , but is set to be smaller than the dose of B ₂ H ₆ / H ₂ in the ion doping step of FIG. At this time, both the P-type impurity and the N-type impurity are introduced into the region 23a between the channel region 30 and the source / drain regions 17, 18, but by setting the dose amount as described above, 23a remains P-type. Next, N ₂ annealing is performed at 300 ° C. for 2 hours.

Then, as shown in FIG.
An interlayer insulating film 28 made of a silicon oxide film having a thickness of about 500 to 1000 nm is formed by a method. Finally, FIG.
As shown in (D), the source region 17 and the drain region 1 on the polycrystalline silicon thin film 26 penetrate through the interlayer insulating film 28.
After opening the contact holes 20, 20 leading to 8,
By depositing an Al—Si—Cu film on the entire surface and patterning it, the source electrode 21 and the drain electrode 2 are formed.
Form 2

In the thin film transistor 16 of this embodiment, when a voltage is applied between the source electrode 21 and the drain electrode 22 when the analog switch is turned on, electrons are injected from the source region 17 to the drain region 18. The electrons are accelerated in a high electric field region near the drain region 18 and hot carriers (electron-hole pairs) are generated by impact ionization. At this time, in the thin film transistor 16 of the present embodiment, unlike the conventional thin film transistor, the p-type impurity diffusion region 23 is formed in the drain region 18.
Is provided, some of the generated holes flow into the P-type impurity diffusion region 23 having a low potential. As a result, the amount of holes injected into the source region 17 is significantly smaller than that of the conventional thin film transistor.
-The characteristic degradation that the Ids characteristic curve moves to the depletion side can be greatly reduced.

Further, according to the structure of the present embodiment, the P-type impurity diffusion region 23 is provided not only in one place but also in a plurality of places, so that the holes generated at any place in the drain region 18 are formed. Can easily flow into the P-type impurity diffusion region 23, and the effect of reducing characteristic deterioration can be enhanced.

In the present embodiment, the structure is such that the P-type impurity diffusion region 23 is connected to the source region 17 and the drain region 18. However, the P-type impurity diffusion region is formed independently inside the channel region. The structure may be modified.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described.
Will be described with reference to FIGS. 4A to 7D.

FIGS. 4A and 4B are views showing a thin film transistor 31 according to the present embodiment.
FIG. 4 is a sectional view taken along line IV-IV in FIG. Note that the thin film transistor 31 of the present embodiment is different from the thin film transistor of the first embodiment only in the structure of the P-type impurity diffusion region. 1A and 1B are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIGS. 4A and 4B, both of the thin film transistors 31 are N-type (first conductivity type).
It has a source region 17 (first region) and a drain region 18 (second region), which are impurity diffusion regions, and a gate electrode 19, and a channel region 30 immediately below the gate electrode 19. The source region 17 and the drain region 18
Are connected to a source electrode 21 and a drain electrode 22, respectively, through a plurality of contact holes 20, 20,. Unlike the first embodiment, a plurality of P-type impurity diffusion regions 32, 32,.
Regions) are formed in the drain region 18 and the source region 17 except for the channel region 30.
It is configured to be divided into two areas.

Next, a method of manufacturing the thin film transistor according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 5A, a film having a thickness of 100 to 50
A silicon oxide film of about 0 nm is formed to form a base insulating film 25.
And Next, a film thickness of 5 is formed on the entire surface of the base insulating film 25 by a CVD method using disilane or monosilane as a raw material.
After forming an amorphous silicon thin film of about 0 nm,
Excimer laser annealing such as XeCl is performed to perform polycrystallization. Then, the polycrystalline silicon thin film 26 is patterned using a well-known photolithography / etching technique (silicon thin film forming step).

Next, as shown in FIG.
A gate insulating film 27 made of a silicon oxide film having a thickness of about 120 nm is formed by a CVD method. Then, a tantalum film having a thickness of about 600 to 800 nm is deposited on the entire surface by a sputtering method, and the gate electrode 19 is formed by patterning the tantalum film (gate electrode forming step).

Next, as shown in FIG. 5C, the region where the P-type impurity diffusion region 32 is to be formed and the gate electrode 1 are formed.
Pattern 2 in which region 9 is formed is opened
9 is formed, ion implantation using B ₂ H ₆ / H ₂ is performed, and ions are implanted using the gate electrode 19 and the photoresist pattern 29 as a mask material. Only the P-type impurity diffusion region 32 is formed (third region formation step). The dose at the time of ion doping is, for example, 1 to 10 × 10 ¹⁵
about atoms / cm ² .

After the photoresist pattern 29 is removed, as shown in FIG. 6A, ion doping using PH ₃ / H ₂ is performed using the gate electrode 19 as a mask, thereby forming an N-type impurity diffusion region. Are formed (first and second region forming steps). The dose during ion doping is 1 to
The dose may be about 10 × 10 ¹⁵ atoms / cm ² , but is set to be smaller than the dose amount of B ₂ H ₆ / H ₂ in the ion doping step of FIG. At this time, both the P-type impurity and the N-type impurity are introduced into the region 32 between the channel region 30 and the source / drain regions 17 and 18, but by setting the dose amount as described above, 32 remains P-type. Next, N ₂ annealing is performed at 300 ° C. for 2 hours.

Then, as shown in FIG.
An interlayer insulating film 28 made of a silicon oxide film having a thickness of about 500 to 1000 nm is formed by a method. Finally, FIG.
As shown in (C), the source region 17 and the drain region 1 on the polycrystalline silicon thin film 26 penetrate through the interlayer insulating film 28.
After opening the contact holes 20, 20 leading to 8,
By depositing an Al—Si—Cu film on the entire surface and patterning it, the source electrode 21 and the drain electrode 2 are formed.
Form 2

The manufacturing method in the case of using only an N-channel TFT has been described above. However, in the case of a liquid crystal display device having a complementary (CMOS type) TFT having both a P-channel TFT and an N-channel TFT, a thin-film transistor which is an N-channel TFT The formation of the P-type impurity diffusion region 32 of FIG.
It can be performed simultaneously with the formation of the source and drain regions of the channel TFT. Hereinafter, the example will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 7A, a film having a thickness of 100 to 50
A silicon oxide film of about 0 nm is formed, and a base insulating film 25 is formed.
And Next, a film thickness of 5 is formed on the entire surface of the base insulating film 25 by a CVD method using disilane or monosilane as a raw material.
After forming an amorphous silicon thin film of about 0 nm,
It is polycrystallized by performing excimer laser annealing such as XeCl. Then, the polycrystalline silicon thin film is patterned using a well-known photolithography and etching technique to form a polycrystalline silicon thin film 26 (silicon thin film forming step).

Next, as shown in FIG. 7B, the surface of the polycrystalline silicon thin film 26 and the underlying insulating film 25 are covered with ECR.
A gate insulating film 27 made of a silicon oxide film having a thickness of about 120 nm is formed by using the CVD method; Then, a tantalum film having a thickness of about 600 to 800 nm is deposited on the entire surface by a sputtering method, and the gate electrode 19 is formed by patterning the tantalum film (gate electrode forming step). In the steps described above, the N-channel TFT side and the P-channel TFT
Similar processing is performed on both the FT side.

Next, as shown in FIG. 7C, a photoresist pattern 29a is formed in which a region where the P-type impurity diffusion region on the N-channel TFT side is to be formed and all the regions on the P-channel TFT side are open. After that, ion doping using B ₂ H ₆ / H ₂ is performed. Then, on the N-channel TFT side, ions are implanted using the photoresist pattern 29a and the gate electrode 19 as a mask, so that the P-type impurity diffusion region 32 is formed on the side of the channel region 30 immediately below the gate electrode 19 ( Third region forming step). On the other hand, on the P-channel TFT side, ions are implanted using the gate electrode 19 as a mask, so that the source region 49 (first region) and the drain region 50 (second region) sandwich the channel region 48 immediately below the gate electrode 19. Is formed. Thus, the P-type impurity diffusion region 32 of the N-channel TFT and the source / drain region 49 of the P-channel TFT
50 can be formed simultaneously. The dose during ion doping is, for example, 1 to 10 × 10 ¹⁵ atoms /
and cm ^2.

Thereafter, the photoresist pattern 29a is
After the removal, as shown in FIG.
Photoresist pattern 29b covering all regions on the T side
Is formed and PH is used as a mask._Three/ H_TwoIo using
Doping. Then, on the P channel TFT side
Is not ion-implanted and N-type impurities are present on the N-channel TFT side.
The source region 17 and the drain region 18 which are material diffusion regions
It is formed (first and second region forming steps). Also, ion
The dose during doping is 1-10 × 10^Fifteenatoms / cm^Two
Although it may be sufficient, the ion doping process of FIG.
B_TwoH₆/ H _TwoIs set to be smaller than the dose amount. This
At this time, the channel region 30 on the N-channel TFT side is
Region 32 between the drain and drain regions 17 and 18 is a P-type impurity.
And N-type impurities will be introduced.
By setting the shift amount as described above, the region 32 remains P-type.
It will be normal.

Thereafter, as in the manufacturing method of the first embodiment, the formation of the interlayer insulating film, the opening of the contact hole, and the formation of the source and drain electrodes may be performed in order. In this method, the P-type impurity diffusion region 32 of the N-channel TFT and the source / drain regions 49 and 50 of the P-channel TFT are first placed before the source / drain region 17 of the N-channel TFT.
18 was later formed, but conversely, the N-channel TF
First, the source / drain regions 17 and 18 of T, the P-type impurity diffusion region 32 of the N-channel TFT and the P-channel TFT
May be formed later (the order of FIGS. 7C and 7D may be reversed).

In the case where a CMOS-TFT is provided, using this method, the P-type impurity diffusion region 32 of the N-channel TFT and the source / drain region 49 of the P-channel TFT can be formed in one photolithography step and P-type ion implantation step.
Since 50 can be simultaneously formed, a thin film transistor having an impurity diffusion region for preventing characteristic deterioration can be manufactured without increasing the number of steps.

Also in the thin film transistor 31 of the present embodiment, since the generated holes flow into the P-type impurity diffusion region 32, the amount of holes injected into the source region 21 is reduced, so that the Vgs-Ids characteristic curve The same effect as that of the first embodiment, in which the characteristic deterioration of movement to the depletion side can be reduced, can be obtained.

In the first and second embodiments,
An example in which the P-type impurity diffusion region is formed so as to protrude from the channel region below the gate electrode has been described. For example, FIG. 8A is a cross-sectional view taken along the line VIII-VIII of FIG. ), The source from the channel region 30;
The P-type impurity diffusion region 71 having a shape not protruding toward the drain regions 17 and 18 may be used.
As shown in FIG. 9B, which is a cross-sectional view taken along the line IX, a structure in which a part of the channel region 30 in the channel length direction is a P-type impurity diffusion region 72 may be employed. FIG.
9A and 9B, FIG. 1A and FIG.
4 (A) and 4 (B) are denoted by the same reference numerals.

In the thin film transistors of the first and second embodiments, the P-type impurity diffusion region is provided also on the source region side. However, holes are generated only in the vicinity of the drain region. The P-type impurity diffusion region does not necessarily need to be provided on the source region side, and may be provided at least on the drain region side.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described.
Will be described with reference to FIGS. 10A and 10B. FIG.

FIGS. 10A and 10B are diagrams showing a thin film transistor 34 of the present embodiment.
Although the P-type impurity diffusion region is provided in the thin-film transistor of the second embodiment, the thin-film transistor 34 of this embodiment does not have the P-type impurity diffusion region, and the source, the drain region, and the channel region have planar shapes. It is something devised.

FIG. 10A is a plan view of the thin film transistor 34 of the present embodiment. As shown in this figure, the thin film transistor 34 has a source region 35 and a drain region 36, both of which are N-type impurity diffusion regions, and a gate electrode 37, and a channel region 38 immediately below the gate electrode 37. Further, the source and drain regions 35,
36, opposite to the gate electrode 37, that is, the source electrode 3
9. The end portion on the side connected to the drain electrode 40 has a narrow width, and the side of the gate electrode 37 has a width of about 10 μm wider on one side and extends outward (vertical direction in the figure).
5a and 36a (carrier injection regions). In the present embodiment, for example, the channel length L is 5 μm, the source,
The width W1 (minimum width) on the narrow side of the drain region is 100 μm
m, and the width W2 of the channel region is equal to the width W of the narrow portion.
It is about 20 μm larger than 1. The source electrode 39 and the drain electrode 40 are connected to the source region 35 and the drain region 36 through a plurality of contact holes 41, 41, respectively.

FIG. 10B is a sectional view taken along line XX of FIG. 10A. As shown in FIG.
2, a base insulating film 43 made of a silicon oxide film, source and drain regions 35 and 36, and a polycrystalline silicon thin film 44 to be a channel region 38 are sequentially formed. Then, a gate electrode 37 made of a tantalum film is formed thereon via a gate insulating film 45. An interlayer insulating film 46 made of a silicon oxide film is formed thereon, and the source region 35
Contact holes 41, 41 leading to the drain region 36
Are formed, and a source electrode 39 and a drain electrode 40 are formed.

By the way, carriers (electrons and holes) are generally used.
There are drift and diffusion in the moving mechanism. Drift is the flow of carriers moving by an electric field, and diffusion is the flow of carriers moving by a concentration gradient. Therefore, in the thin film transistor 34 of the present embodiment, the flow of holes generated near the drain region 36 also has a component flowing toward the source region 35 due to drift and a component flowing in an arbitrary direction due to diffusion. Some of the components flow toward the overhang portions 35a and 36a. On the other hand, when a voltage is applied from the source / drain electrodes 39 and 40 to generate an electric field, the region which actually functions as a transistor is a region of a narrow portion of the source / drain regions 35 and 36 and the channel region 38. It is. Therefore, the holes flowing into the overhang portions 35a and 36a do not affect the transistor characteristics. As a result, the ratio of holes effectively injected into the source region 35 is lower than that of the conventional thin film transistor. Therefore, characteristic deterioration can be reduced.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described.
The embodiment will be described with reference to FIGS. 11 (A) and 11 (B).

FIGS. 11A and 11B show a thin-film transistor 51 of the present embodiment. The thin-film transistor 51 of the present embodiment also has the same P-type impurity diffusion as the third embodiment. This is a mode in which a plurality of transistors each having no region and having a small channel width are connected in parallel. Note that in FIG. 11A and FIG. 11B, the same components as those in FIG. 10A and FIG.

FIG. 11A is a plan view of the thin film transistor 51 of the present embodiment. As shown in this figure, a plurality of thin film transistors 51 (in the case of this embodiment, 4
) Of the polycrystalline silicon thin film 52 into one gate electrode 37.
Are formed so as to cross each other. In each polycrystalline silicon thin film 52, a source region 53 (first region) and a drain region 54 (second region), which are N-type impurity diffusion regions sandwiching the channel region 38 below the gate electrode 37, are provided.
Are formed. Then, each polycrystalline silicon thin film 52
A contact hole 41 is formed in the source region 53 and the drain region 54 of the source electrode 53, and the source region 53 and the drain region 54 share a common source electrode 39 and drain electrode 4.
0. In the present embodiment, as an example of the dimensions, the channel length L is 5 μm, the width W1 of each channel region 38 is 10 μm, and the dimension W2 between the outermost sides of the plurality of polycrystalline silicon thin films 52 is 70 μm. ing. W1 is 10 μm or less, and W2 is 50 μm.
It is desirable that this is the case.

FIG. 11B is a cross-sectional view taken along the line XI-XI of FIG. As shown in FIG.
2, a base insulating film 43 made of a silicon oxide film, source and drain regions 53 and 54, and a polycrystalline silicon thin film 52 to be a channel region 38 are sequentially formed. Then, a gate electrode 37 made of a tantalum film is formed thereon via a gate insulating film 45. An interlayer insulating film 46 made of a silicon oxide film is formed thereon, and a source region 53
Contact holes 41, 41 leading to drain region 54
Are formed, and a source electrode 39 and a drain electrode 40 are formed.

The operating temperature of a TFT having a larger channel width is higher. This is because, when the channel width is large, the heat generated near the center of the channel is dissipated only in the vertical direction, and is hard to dissipate in the horizontal direction. Therefore, the reliability decreases as the TFT has a larger channel width. From this viewpoint, in this embodiment, by connecting a plurality of transistors having a small width in parallel, heat during operation is efficiently dissipated, and sufficient reliability can be secured.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described.
Will be described with reference to FIG.

This embodiment relates to a liquid crystal display device using the thin film transistor of the present invention. FIG. 12 is a block diagram showing the structure of the liquid crystal display device.

As shown in FIG. 12, this liquid crystal display device 5
Reference numeral 5 denotes a device having a built-in driver circuit, which includes a source line driver circuit 56, a gate line driver circuit 57, and a pixel matrix 58. The source line driver circuit 56 includes a shift register 59, video signal buses 60a, 60b, 60c, and an analog switch 61.
a, 61b, 61c, etc., and the gate line driver circuit 57 has a shift register 62, a buffer 63, and the like. The transistors (not shown) constituting these driver circuits 56, 57 have the same configuration. It is a CMOS type. On the other hand, the pixel matrix 58 has pixels 64 arranged in a matrix, and each pixel includes a pixel transistor 65, a liquid crystal cell 66, and a counter electrode 67. Then, source lines 68a, 68b, 68c extend from the source line driver circuit 56 to each pixel transistor 65 of the pixel matrix 58, and a gate line extends from the gate line driver circuit 57 to each pixel transistor 65 of the pixel matrix 58. 69a and 69b extend.

In this liquid crystal display device, the thin film transistor of the present invention is applied to each part or a part of a circuit portion such as a source line driver circuit and a gate line driver circuit, an analog switch, and a pixel transistor. With this configuration, it is possible to realize a liquid crystal display device with less occurrence of a circuit malfunction or the like and excellent image quality.

Next, a description will be given of a consideration regarding a mechanism of generating a leak current (off current) in a polysilicon TFT.

As shown in FIG. 13A, a polysilicon TFT (n-channel enhancement type MOSFET) is used.
T) The leak current (off current) “ID” of M1 is obtained when the potential of the gate (G) is set to 0 V or less and a predetermined voltage is applied between the source (S) and the drain (D) (drain potential> source). Potential, drain current> 0).

FIG. 14 shows an example of the relationship between the gate-source voltage (VGS) and the drain-source current (IDS) of a polysilicon TFT formed by a low-temperature process. It can be seen that the leak current (off current) is quite large and the width of variation (Q) is wide.

The reason why the leakage current (off-state current) of the polysilicon thin film MOSFET is larger than that of the single crystal MOSFET is that there is a leakage current mechanism unique to the polysilicon FET. The consideration made by the inventor of the present application will be described with reference to FIG.

FIG. 15 is an energy band diagram of the N-type MOSFET in the storage state (gate is reverse biased). Under the influence of the negative gate voltage, the energy band is inclined. Ei indicates the intrinsic level, Ev indicates the upper limit level of the valence band, and Ec indicates the lower limit level of the conduction band.

For example, suppose that electron-hole pairs are generated in the valence band due to light irradiation to the polysilicon MOSFET or excitation by noise.

Various localized levels J1,
J2, J3 to Jn are present, and therefore, with the help of the electric field, the newly generated electrons will be localized levels J1, J
Through J2, J3, etc., it is possible to reach a high level of localized level Jn. If the width “d” between the forbidden band and the conduction band at that level is as short as the de Broglie wavelength due to the bending of the band, electrons can pass through the forbidden band and move to the conductor by the tunnel effect. Thus, a leak current (off current) is generated.

As described above, the polysilicon MOSFET
The "electric field" in, the excitation through the localized level of electrons,
Alternatively, the band is sharply bent. That is,
The “electric field” has an important effect on the leakage current characteristics of the TFT.

According to the study of the present inventor, FIG.
As shown in FIG. 4B, in a MOSFET configured using a polysilicon island on a substrate 930, a portion where the outer edge portion (outer peripheral portion) of the island overlaps with the gate electrode 22 is in contact with the source 132 and the drain 142. In the two edge portions (a) to (d), a strong electric field
In addition to the drain, it has been found that this is a cause of an increase in leakage current.

The strong electric field at the four edge portions (a) to (d) is due to the thickness of the island,
This is because a step is generated between 0 and the island, and the thickness of the gate insulating film becomes thinner at this portion, and because the edge of the island is at an acute angle, electric field concentration tends to occur.

(Sixth Embodiment) FIG. 16 is a plan view of a MOSFET according to a sixth embodiment of the present invention.

This MOSFET is characterized in that an intrinsic layer (i-layer) 11 is formed on the outer edge of the polysilicon island.
0 is provided. That is, FIG.
Unlike this, the outer edge (outer periphery) of the polysilicon island does not coincide with the outer edges of the source layer 130 and the drain layer 140, and the source layer 130 and the drain layer 140 are provided inside the island. In FIG. 16, reference numeral 120 denotes a gate electrode layer, and reference numeral 930 denotes an insulating substrate.

FIG. 17 is a sectional view of the device taken along the line XVII--XVII in FIG. 16, and FIG.
FIG. 8 is a cross-sectional view of the device along the line XVIII. 17 and 18A, reference numeral 150 denotes a gate insulating film (SiO ₂ film).

As shown in FIG. 18A, at the edge portions (a) and (b) of the polysilicon island, the thicknesses L1 and L2 of the gate insulating film are different from each other due to a step caused by the thickness of the island. Thinner than the thickness of the flat part,
In addition, the edge of the island is at an acute angle and electric field concentration is likely to occur, so that the electric field is strong.

However, in the structure of FIG. 18A, the intrinsic layer (i-layer) 110 reduces the electric field applied to the source layer 130. That is, as shown in FIG.
When an electric field E is applied, the intrinsic layer (i) layer 110
The depletion layer extends in the inside and absorbs the electric field. Therefore, the electric field applied to the source layer 130 decreases. As described above, the electric field affects the generation of the leak current (off current). Therefore, as the electric field becomes smaller, the leak current (off current) decreases and the variation is suppressed.

FIGS. 19 and 20 show the relationship between the drain-source current (IDS) and the gate-source voltage (VGS) of a polysilicon TFT (n-type MOSFET) produced by a low-temperature process, as measured by the present inventors. Indicates a value. FIG. 19 shows a case where the present invention is not applied.
0 indicates the case where the present invention was applied (in the case of the structure of FIG. 16), and the leakage current amount was actually measured for 12 samples.

In FIG. 19, when VGS = −10 V, IDS = 10 ⁻¹⁰ A at maximum, but in FIG. 20, under the same conditions, IDS = 10 ⁻¹¹ A at maximum, and the amount of leakage current is One order of magnitude has been reduced.

[0123] Also, in the case of FIG. 19, when VGS = -10 V, the variation range of the IDS is "10 ^{-1 1} ~10 ^-13 (A)"
In the case of FIG. 20, under the same conditions, IDS
Is in the order of “10 ⁻¹¹ to 10 ⁻¹² (A)”, and the variation is reduced by one digit.

As described above, according to the configuration of FIG. 16, the amount of leak current (off current) can be reduced and its variation can be suppressed.

In FIG. 16, an intrinsic layer (i-layer) 110 is provided so as to surround the polysilicon island in consideration of convenience of a mask pattern for forming a source layer and a drain layer. It suffices that the intrinsic layer (i) be provided in a portion overlapping with the gate electrode layer 120, particularly in the portions (a), (b), (c), and (d) of FIG.

In FIG. 16, for convenience of explanation, an intrinsic layer (i-layer) is interposed for both the source (S) and the drain (D). It is sufficient that an intrinsic layer (i-layer) is interposed.

However, for example, the T of the pixel portion of the liquid crystal display device is
In the case of FT, the potential fluctuates variously, and the source and drain cannot be specified. In such a case, it is necessary to have a structure in which an intrinsic layer (i-layer) is interposed in both of the two impurity layers serving as a source (or a drain).

(Seventh Embodiment) FIG. 21 is a sectional view of a device according to a seventh embodiment of the present invention (see FIG. 16).
It is sectional drawing which follows the XVIII-XVIII line.

In the present embodiment, in portions (a) and (b) where the electric field is strong, p layer 160 and an intrinsic layer (i layer) 162 connected to the p layer are formed on the outer edge of the polysilicon island. It is provided.

According to the experiment of the present inventor, in this case also, the same effect as that of the above-described embodiment was obtained.

(Eighth Embodiment) FIG. 22 shows a sectional structure (upper side) of a device according to an eighth embodiment of the present invention.
It is a figure which shows a planar structure (lower side).

This embodiment is characterized in that an insulating film (SiO ₂ film) 1 is formed so as to overlap the outer edge of a polysilicon island.
70 is provided to increase the thickness of the insulating film at the edge portion, thereby alleviating the electric field.

As shown in the upper part of FIG. 22, an insulating film (SiO ₂ film) 17 is provided between the edge of the polysilicon island and the gate electrode layer 120 at the edge.
0 (thickness L3a, L3b) and the gate insulating film 150 (thickness L4a, L4b) overlap and exist. Thereby, the electric field applied to n ⁺ layer (source or drain) 130 is reduced.

(Ninth Embodiment) FIG. 23A shows a plan structure of a device according to a ninth embodiment of the present invention, and FIG. 23B shows an equivalent circuit thereof.

A feature of the present invention is that the structure shown in FIG. 16 is applied to a dual gate type MOSFET.

The dual-gate type MOSFET shown in FIG.
3 (B), two MOS transistors M
1 and M2 are connected in series. Note that FIG.
In FIG. 3A, reference numeral 120 is a first gate, reference numeral 22 is a second gate, and reference numeral 180 is
Is a source layer.

By adopting the electric field relaxation structure using the intrinsic layer shown in FIG. 16 in at least each of the parts (a) to (h) shown in FIG. 23 (A), the leak current of each MOSFET is reduced. .

When the reduction rate of the leak current for one MOSFET (the amount of leakage current after application of the present invention / the amount of leakage current before application) is “F (<1)”, two MOs
The reduction rate of the leakage current in the entire SFET is “F × F”, and the leakage current amount is further reduced as compared with the case of one MOSFET. In addition, variations in leakage current are reduced.

(Tenth Embodiment) FIG. 24 is a diagram showing a planar structure (upper side) and a sectional structure (lower side) of a device according to a tenth embodiment of the present invention.

This embodiment is characterized in that the structure shown in FIG.
This is applied to a so-called “offset MOSFET”.

An offset MOSFET is a transistor having a structure in which at least a drain layer is arranged with an offset with respect to a gate electrode (ie, has an offset in a relative positional relationship). Note that FIG.
In No. 4, an offset is provided not only in the drain layer 142 but also in the source layer 132.

The offset structure is effective in reducing the leak current (off current) because the gate and drain do not overlap, but on the other hand, when the offset amount is large, the on current decreases and the threshold voltage decreases. Increase. Therefore, it is difficult to adjust the offset amount.

If the structure shown in FIG. 16 is applied to a MOS transistor having an offset structure, the leak current (off current) can be effectively reduced and the variation can be suppressed without increasing the offset amount so much. Therefore, it is easy to secure the ON current and design.

For example, when the present invention is not applied, 2 μm is required to reduce the leak current (off current) to a desired level.
Assuming that an offset amount of m is required, by adopting the structure of the present embodiment, for example, the offset amount is 1 μm
And the design becomes easier.

(Eleventh Embodiment) An example of a method of manufacturing a TFT having a CMOS structure employing the structure of FIG. 16 is shown in FIG.
5 to 31 are shown.

(Step 1) As shown in FIG. 25, an amorphous silicon thin film (or polysilicon thin film) 2 deposited on a glass substrate 930 by LPCVD.
Then, laser irradiation is performed on the polysilicon thin film with an excimer laser, and the polysilicon thin film is recrystallized by annealing.

(Step 2) Subsequently, as shown in FIG. 26, patterning is performed to form islands 210a and 210b.
To form

(Step 3) As shown in FIG. 27, the gate insulating film 300 covering the islands 210a and 210b
a and 300b are formed.

(Step 4) As shown in FIG.
Gate electrodes 400a, 400 made of l, Cr, Ta, etc.
b is formed.

(Step 5) As shown in FIG. 29, mask layers 450a and 450b made of polyimide or the like are formed,
Gate electrode 400a and mask layers 450a and 450b
Is used as a mask, for example, boron (B) ion implantation is performed in a self-aligned manner. Thereby, the p ⁺ layer 50
0a and 500b are formed. Accompanying this, intrinsic layers 510a and 510b are automatically formed.

(Step 6) As shown in FIG. 30, mask layers 460a and 460b made of polyimide or the like are formed.
Gate electrode 400b and mask layers 460a, 460b
Is used as a mask, for example, phosphorus (P) ion implantation is performed in a self-aligned manner. Thereby, the n ⁺ layer 60
0a and 600b are formed. Accompanying this, the intrinsic layers 610a and 610b are automatically formed.

(Step 7) As shown in FIG. 31, an interlayer insulating film 700 is formed, and after selectively forming a contact hole, electrodes 810, 820, and 830 are formed.

As described above, according to the present embodiment, the source layer and the drain layer can be formed inside the outer edge of the polysilicon island by self-alignment using the gate electrode and the insulating layer as a mask. That is, the intrinsic layer (i) can be automatically formed at the outer edge of the polysilicon island by self-alignment.

(Twelfth Embodiment) FIGS. 32 and 3
FIG. 3 shows an outline of a liquid crystal display device to which the first to eleventh embodiments according to the present invention are applied.

The liquid crystal display device includes, for example, as shown in FIG. 32, an active matrix section (pixel section) 101, a data line driver 110, and a scanning line driver 102. In FIG. 32, reference numeral 103 denotes a timing controller, reference numeral 104 denotes a video signal amplifier circuit, and reference numeral 105 denotes a video signal generator.

In this embodiment mode, the TFTs in the active matrix section (pixel section) 101 and the TFTs constituting the data line driver 110 and the scanning line driver 102
Both have the structure shown in FIG. 16 or any of the structures shown in FIGS.

As shown in FIG. 33, on the active matrix substrate 940, not only the TFT of the pixel portion 100 but also the data line driver 110 and the scanning line driver 1 are provided.
02 are formed by the same manufacturing process. That is, a liquid crystal display device is formed using the driver-mounted active matrix substrate 940.

As shown in FIG. 33, for example, the liquid crystal display device comprises a backlight 900, a polarizing plate 920, an active matrix substrate 940, a liquid crystal 950, a color filter substrate (counter substrate) 960, and a polarizing plate 970.

In the liquid crystal display device of this embodiment mode, the leak current (off current) of the TFT in the pixel portion is reduced, and the fluctuation of the luminance of the display screen is reduced. Further, variations in the leak current (off current) of the TFT are suppressed, and therefore, the active matrix substrate can be easily designed. In addition, since a high-performance liquid crystal driver circuit configured using the TFT of the present invention is mounted, the performance is high.

An electronic apparatus using the liquid crystal display device of the above-described embodiment has a display information output source 1 shown in FIG.
000, display information processing circuit 1002, display drive circuit 10
04, a display panel 1006 such as a liquid crystal panel, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a memory such as a ROM or a RAM, a tuning circuit for tuning and outputting a television signal, and the like, and outputs display information such as a video signal based on a clock from a clock generation circuit 1008. I do. The display information processing circuit 1002 includes a clock generation circuit 1
The display information is processed and output based on the clock from 008. The display information processing circuit 1002 can include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. The display driving circuit 1004 includes a scanning side driving circuit and a data side driving circuit, and drives the liquid crystal panel 1006 for display. The power supply circuit 1010 supplies power to each of the above circuits.

FIG. 35 shows an electronic apparatus having such a configuration.
36, a personal computer (PC) and an engineering workstation (EWS) for multimedia shown in FIG. 36, a pager shown in FIG. 37, or a mobile phone, a word processor, a television, a viewfinder type video or a monitor direct view type video. Examples include a tape recorder, an electronic organizer, an electronic desk calculator, a car navigation device, a POS terminal, and a device having a touch panel.

The liquid crystal projector shown in FIG. 35 is a projection type projector using a transmission type liquid crystal panel as a light valve, and uses, for example, a three-plate prism type optical system.

Referring to FIG. 35, in a projector 1100, a projection light emitted from a lamp unit 1102 of a white light source is divided into R, G, and B light by a plurality of mirrors 1106 and two dichroic mirrors 1108 inside a light guide 1104. Three liquid crystal panels 1110R, 1110 that are divided into primary colors and display images of each color
G and 1110B. The light modulated by each of the liquid crystal panels 1110R, 1110G and 1110B is applied to a dichroic prism 1112.
Is incident from three directions. Dichroic prism 11
In 12, the red R and blue B lights are bent by 90 ° and the green G light goes straight, so that the images of the respective colors are synthesized, and a color image is projected on a screen or the like through the projection lens 1114.

The personal computer 12 shown in FIG.
00 is a main body 1204 having a keyboard 1202
And a liquid crystal display screen 1206.

The pager 1300 shown in FIG. 37 includes a liquid crystal display substrate 1304, a light guide 1306 provided with a backlight 1306a, a circuit board 1308, and first and second shield plates 1310, 13 in a metal frame 1302.
12, two elastic conductors 1314 and 1316, and a film carrier tape 1318. Two elastic conductors 1314 and 1316 and film carrier tape 13
Reference numeral 18 denotes a connection between the liquid crystal display substrate 1304 and the circuit board 1308.

Here, the liquid crystal display substrate 1304 has liquid crystal sealed between two transparent substrates 1304a and 1304b, thereby forming at least a dot matrix type liquid crystal display panel. On one transparent substrate, FIG.
Or a display information processing circuit 1002 in addition to the above. The circuit not mounted on the liquid crystal display substrate 1304 is an external circuit of the liquid crystal display substrate, and can be mounted on the circuit substrate 1308 in the case of FIG.

FIG. 37 shows the configuration of the pager, and therefore requires a circuit board 1308 in addition to the liquid crystal display substrate 1304. However, this is a case where a liquid crystal display device is used as one component for electronic equipment. When a display driving circuit or the like is mounted on a transparent substrate, the minimum unit of the liquid crystal display device is the liquid crystal display substrate 1304. Alternatively, a structure in which the liquid crystal display substrate 1304 is fixed to a metal frame 1302 serving as a housing can be used as a liquid crystal display device which is one component for electronic devices. Further, in the case of a backlight type, a liquid crystal display substrate 1304 and a light guide 1306 provided with a backlight 1306a can be incorporated in a metal frame 1302 to constitute a liquid crystal display device. Instead of these, as shown in FIG.
Two transparent substrates 130 constituting the liquid crystal display substrate 1304
A TCP (Tape Carrier Package) 1320 in which an IC chip 1324 is mounted on a polyimide tape 1322 on which a metal conductive film is formed is connected to one of 4a and 1304b, and is used as a liquid crystal display device which is one component for electronic equipment. You can also.

Note that the present invention is not limited to the above embodiment. For example, the present invention is not limited to being applied to the driving of the above-described various liquid crystal panels, but is also applicable to electroluminescence and plasma display devices.

Further, the present invention relates to a MOSFE having an LDD structure.
It can also be applied to T.

Further, in the first to fourth embodiments, the example of the N-channel TFT has been described. However, the problem of characteristic deterioration due to hot carriers is not so remarkable as that of the N-channel TFT. Is also a possible problem. Therefore, the present invention relates to a P-channel TFT.
In this case, an N-type impurity diffusion region may be formed instead of the P-type impurity diffusion region in the first and second embodiments. The silicon thin film forming the channel region, the source, and the drain region is not limited to the polycrystalline silicon thin film, but may be an amorphous silicon thin film.

Then, the dimensions of the P-type impurity diffusion regions and the number of the P-type impurity diffusion regions in the first and second embodiments, or the dimensions of the overhang portion in the third embodiment and the fourth Specific numerical values such as the width of each channel region and the entire width in the embodiment can be appropriately designed. Further, in the liquid crystal display device, the thin film transistor of the present invention is not limited to a pixel transistor and an analog switch, and can be applied to various circuit components. Further, although an example of a top gate thin film transistor is described in the above embodiment, the present invention can be applied to a bottom gate thin film transistor.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing a thin film transistor according to a first embodiment of the present invention.

FIGS. 2A to 2C are process flow charts showing the steps of manufacturing the thin film transistor in order.

FIGS. 3A to 3D are process flow charts showing the steps of manufacturing a thin film transistor in order.

FIGS. 4A and 4B are diagrams showing a thin film transistor according to a second embodiment of the present invention.

5 (A) to 5 (C) are process flow charts showing a method of manufacturing a thin film transistor in order.

FIGS. 6A to 6C are process flow charts sequentially showing a method of manufacturing a thin film transistor.

FIGS. 7A to 7D are process flow charts sequentially showing another method of manufacturing a thin film transistor.

FIGS. 8A and 8B are diagrams showing a thin film transistor according to another embodiment in which the shape of a P-type impurity diffusion region is different.

FIGS. 9A and 9B are diagrams showing a thin film transistor of still another embodiment in which the shape of a P-type impurity diffusion region is different.

FIGS. 10A and 10B are diagrams showing a thin film transistor according to a third embodiment of the present invention.

FIGS. 11A and 11B are diagrams showing a thin film transistor according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 13A shows a TFT (n-type MOSFET).
FIG. 7 is a diagram for explaining a leak current (off current) of
FIG. 13B is a diagram showing a planar structure of a TFT (n-type MOSFET).

FIG. 14 is a diagram showing voltage-current characteristics of a polysilicon TFT.

FIG. 15 is a diagram for explaining a cause of a leak current (off current) in a polysilicon TFT.

FIG. 16 is a plan view of a MOSFET according to a sixth embodiment of the present invention.

FIG. 17 is a cross-sectional view of the MOSFET of FIG. 16 taken along the line XVII-XVII.

FIG. 18 (A) is an XVIII-X of the device of FIG.
FIG. 18 is a sectional view of the MOSFET along the line VIII,
(B) is a diagram for explaining the effect of electric field relaxation.

FIG. 19 is a diagram illustrating a relationship between a gate-source voltage (VGS) and a drain-source current (IDS) of a comparative example.

FIG. 20 is a MOSFE of the present invention shown in FIG.
FIG. 6 is a diagram showing a relationship between a gate-source voltage (VGS) and a drain-source current (IDS) of T.

FIG. 21 is a sectional view of the device according to the seventh embodiment of the present invention (a sectional view taken along line XVIII-XVIII in FIG. 16).

FIG. 22 is a cross-sectional structure (upper side) and a planar structure (lower side) of a device according to an eighth embodiment of the present invention.
FIG.

FIG. 23A is a diagram showing a planar structure of a device according to a ninth embodiment of the present invention.
(B) is a diagram showing an equivalent circuit thereof.

FIG. 24 is a diagram showing a planar structure (upper side) and a cross-sectional structure (lower side) of a device according to a tenth embodiment of the present invention.

FIG. 25 is a diagram showing a first step for manufacturing the CMOS (TFT) of the present invention.

FIG. 26 is a diagram showing a second step for manufacturing the CMOS (TFT) of the present invention.

FIG. 27 is a diagram showing a third step for manufacturing the CMOS (TFT) of the present invention.

FIG. 28 is a diagram showing a fourth step for manufacturing the CMOS (TFT) of the present invention.

FIG. 29 is a diagram showing a fifth step for manufacturing the CMOS (TFT) of the present invention.

FIG. 30 is a diagram showing a sixth step for manufacturing the CMOS (TFT) of the present invention.

FIG. 31 is a diagram showing a seventh step for manufacturing the CMOS (TFT) of the present invention.

FIG. 32 is a block diagram illustrating a configuration of a liquid crystal display device.

FIG. 33 is a diagram illustrating a configuration of a liquid crystal display device.

FIG. 34 is a diagram illustrating an electronic device including the liquid crystal display device according to an embodiment;

FIG. 35 is a diagram illustrating a liquid crystal projector configured using the liquid crystal display device of the embodiment.

FIG. 36 is a diagram illustrating a personal computer including the liquid crystal display device according to an embodiment;

FIG. 37 is a diagram illustrating a pager configured using the liquid crystal display device according to the embodiment;

38A and 38B illustrate an example of a conventional thin film transistor.

[Explanation of symbols]

 Reference Signs List 16 thin film transistor 17 source region (first region) 18 drain region (second region) 19 gate electrode 30 channel region 20 contact hole 21 source electrode 22 drain electrode 23 p-type impurity diffusion region (third region) 24 glass substrate 25 base insulation Film 26 polycrystalline silicon thin film 27 gate insulating film 28 interlayer insulating film 29 photoresist pattern 30 channel region

Claims (29)

[Claims] A channel region formed in a non-single-crystal silicon thin film on a substrate; a first region of a first conductivity type formed in the non-single-crystal silicon thin film so as to sandwich the channel region; A thin film transistor comprising: a second region; and a carrier injection region into which carriers of a conductivity type opposite to the first conductivity type generated in a high electric field region near the first region or the second region flow. 2. A channel region formed in a non-single-crystal silicon thin film on a substrate, a first region of a first conductivity type formed in said non-single-crystal silicon thin film so as to sandwich said channel region, and A thin film transistor comprising: a second region; and at least one third region having a conductivity type opposite to the first conductivity type formed in the non-single-crystal silicon thin film between the first region and the second region. 3. The thin film transistor according to claim 2, wherein the plurality of third regions are formed on the non-single-crystal silicon thin film. 4. The thin film transistor according to claim 2, wherein the third region is formed on the non-single-crystal silicon thin film between at least one of the first region and the second region and the channel region. 5. The thin film transistor according to claim 2, wherein the third region is formed in at least a part of the channel region. 6. The thin film transistor according to claim 1, wherein the first conductivity type is N-type. 7. The thin film transistor according to claim 1, wherein said non-single-crystal silicon thin film is a polycrystalline silicon thin film. 8. The thin film transistor according to claim 7, wherein the polycrystalline silicon thin film having the channel region, the first region, and the second region is formed by a low-temperature process. 9. A channel region formed in a non-single-crystal silicon thin film on a substrate, a first region of a first conductivity type formed in said non-single-crystal silicon thin film so as to sandwich said channel region, and And a second region, wherein the width of at least the channel region of the non-single-crystal silicon thin film is larger than the minimum width of the first region and the second region. 10. The thin film transistor according to claim 9, wherein the width of the channel region is 50 μm or more. 11. The thin film transistor according to claim 9, wherein the width of the channel region is 100 μm or more. 12. A channel region formed in a non-single-crystal silicon thin film on a substrate, a first region of a first conductivity type formed in said non-single-crystal silicon thin film so as to sandwich said channel region, and A second region, and a third region having a conductivity type opposite to the first conductivity type formed both between the first region and the channel region and between the second region and the channel region; A method of manufacturing a thin film transistor, wherein the channel region has a conductivity type opposite to the first conductivity type, wherein a non-single-crystal silicon thin film forming step of forming a non-single-crystal silicon thin film on a substrate; Forming a third region by ion-implanting an impurity of a conductivity type opposite to the first conductivity type into a part of the third region; and forming a gate insulating film on the third region of the non-single-crystal silicon thin film. Forming a gate electrode through the first region; and ion-implanting a first conductivity type impurity with a dose smaller than the dose during the ion implantation in the third region forming step. First forming a second region
A second region forming step; and a method of manufacturing a thin film transistor. 13. A channel region formed in a non-single-crystal silicon thin film on a substrate, a first region of a first conductivity type formed in said non-single-crystal silicon thin film so as to sandwich said channel region, and A second region, and a third region having a conductivity type opposite to the first conductivity type formed both between the first region and the channel region and between the second region and the channel region; A thin film forming step of forming a non-single-crystal silicon thin film on a substrate; and a gate electrode forming step of forming a gate electrode on the non-single-crystal silicon thin film via a gate insulating film. Using the gate electrode as a mask and ion-implanting impurities of a conductivity type opposite to the first conductivity type using a mask material covering the first region and the second region. Forming a third region in a region adjacent to the channel region, and ion-implanting a first conductivity type impurity with a smaller dose than the ion implantation in the third region forming process. Forming a first region and a second region in a region adjacent to a third region of the non-single-crystal silicon thin film.
Forming a second region. 14. A channel region formed in a non-single-crystal silicon thin film on a substrate and used in a liquid crystal display device having a complementary thin film transistor having both P-type and N-type, and a channel region formed in the non-single-crystal silicon thin film. A first region and a second region of the first conductivity type formed to be separated from each other so as to sandwich the first conductive type formed on the non-single-crystal silicon thin film between the first region and the second region. A method of manufacturing a thin film transistor having a third region having a conductivity type opposite to a first conductivity type, wherein the formation of the third region includes a first region and a second region of a transistor having a conductivity type opposite to the first conductivity type. A method for manufacturing a thin film transistor which is performed simultaneously with formation of a region. 15. A step of depositing a thin film of amorphous silicon on a substrate, a step of irradiating the amorphous silicon thin film with laser light to obtain a crystallized polysilicon thin film, and Patterning the polysilicon thin film to form a polysilicon island, forming a gate insulating film on the polysilicon island, and forming a gate electrode on the gate insulating film; and an outer edge of the polysilicon island. Forming an insulating layer covering at least a part of the source electrode, introducing impurities into the polysilicon island using the gate electrode and the insulating layer as a mask, and forming a source layer and a drain layer; And a step of forming a drain electrode. 16. A semiconductor thin-film island provided on a substrate, a source layer and a drain layer formed by selectively introducing impurities into the semiconductor thin-film island, and facing the semiconductor thin-film island via an insulating film. A thin film transistor, wherein at least one of the source layer and the drain layer is formed at a predetermined distance inside from an outer edge of the semiconductor thin film island. 17. The semiconductor device according to claim 16, wherein at least a portion of the outer edge of the semiconductor thin film island that overlaps with the gate electrode, which is a region avoiding the source layer and the drain layer, has no impurity introduced therein. Thin film transistor that is a trinic layer. 18. The semiconductor device according to claim 16, wherein a portion of the outer edge portion of the semiconductor thin film island that overlaps at least the gate electrode is a region avoiding the source layer and the drain layer. Is a thin film transistor comprising an impurity layer into which an impurity of the opposite conductivity type is introduced, and an intrinsic layer connected to the impurity layer. 19. The thin film transistor according to claim 16, wherein said predetermined distance from an outer edge of said semiconductor thin film island to said source or drain is 1 μm or more and 5 μm or less. 20. The thin film transistor according to claim 16, wherein said semiconductor thin film island is made of polysilicon formed by annealing amorphous silicon. 21. The thin film transistor according to claim 16, wherein the thin film transistor has an offset in a relative positional relationship between the gate electrode and the drain layer. 22. The thin film transistor according to claim 16, wherein the thin film transistor has a dual gate structure in which two gate electrodes are arranged in parallel with each other. 23. A semiconductor thin-film island provided on a substrate, a source layer and a drain layer formed by selectively introducing impurities into the semiconductor thin-film island, and an outer edge of the semiconductor thin-film island. A first insulating film provided and provided; a second insulating film formed to cover the surface of the semiconductor thin film island and the first insulating film; and a second insulating film provided on the second insulating film. And a gate electrode layer. 24. A circuit comprising the thin film transistor according to claim 1. 25. A liquid crystal display device with a built-in driver circuit, comprising the thin film transistor according to claim 1. 26. The liquid crystal display device according to claim 25, wherein the thin film transistor is used in a circuit section. 27. The liquid crystal display device according to claim 26, wherein the thin film transistor is used as an analog switch of the circuit section. 28. A liquid crystal display device having the thin film transistor according to claim 16 in a pixel portion. 29. A liquid crystal display device comprising a liquid crystal drive circuit formed using the thin film transistor according to claim 16.