JP2001284469A - Method for manufacturing semiconductor device - Google Patents

Abstract

[PROBLEMS] To form two or more types of semiconductor devices by minimizing contamination due to a photoresist or the like and forming oxide films having different thicknesses while suppressing an increase in the number of manufacturing steps.
It is an object of the present invention to provide a method of manufacturing an inexpensive and highly reliable semiconductor device in which a one-layer polysilicon nonvolatile memory and a high-speed logic circuit are formed on the same substrate. SOLUTION: First and second semiconductor devices are on the same substrate 21.
A method of manufacturing a semiconductor device provided thereon and having a thickness of a gate oxide film different between semiconductor devices, comprising forming an impurity diffusion layer 22C having a controlled surface impurity concentration in a first semiconductor device formation region 21C. , Second semiconductor device formation region 2
A method of manufacturing a semiconductor device, comprising the steps of forming a gate oxide film 23B on the first semiconductor device formation region 21C and simultaneously forming a gate oxide film 23C thicker than the gate oxide film 23B on the first semiconductor device formation region 21C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having two or more different gate oxide films, for example, a single-layer polysilicon type EEPROM or EPROM having a floating gate and a high-speed semiconductor device. And a logic circuit formed on the same substrate.

[0002]

2. Description of the Related Art In recent years, a demand for a system-on-chip has rapidly increased in the fields of communication and audio / video. In addition, the development cycle of products has become shorter, and there is a need to support high-mix low-volume production. In order to respond to these demands, a technique for embedding a nonvolatile memory in a logic circuit is required. Some non-volatile memories have a floating gate and perform writing and erasing by injecting or extracting electrons through a tunnel oxide film. When writing to such a nonvolatile memory cell, for example, 1
A high voltage of about 2 to 15 V is applied, and the same high voltage is applied to the source region during erasing. At such an applied voltage, the tunnel oxide film generally has
A film having a thickness of about nm is used. Also, a high voltage is applied to the transistors constituting the peripheral circuits of the nonvolatile memory (for example, word line and bit line drive circuits) in the same manner as described above. The gate oxide film of such a transistor generally needs to have a thickness of about 15 nm or more. On the other hand, a transistor in a logic circuit has been reduced in voltage, and the gate oxide film has been reduced in thickness with the progress of the process. For example,
As shown in Table 1, in a transistor in a general logic circuit, a gate oxide film corresponding to the transistor is becoming thinner as the minimum gate length becomes finer.

[0003]

[Table 1]

As described above, in a semiconductor device provided with a nonvolatile memory and a logic circuit, a gate oxide film of a peripheral circuit (high breakdown voltage region) of the nonvolatile memory, a tunnel oxide film of the nonvolatile memory, and a gate of the logic circuit are provided. It is necessary to form an oxide film and three types of oxide films.

In general, as the thickness of an oxide film decreases, the oxide film becomes more sensitive to impurities, so that a cleaner manufacturing technique is required. For example, when a gate oxide film having a thickness of about 10 nm or less is exposed to a photoresist, the gate oxide film is damaged, resulting in a decrease in device performance and reliability. Therefore, when an oxide film having two or more film thicknesses is usually formed, first, the thickest oxide film is formed by combining an oxidation process with photolithography and an etching process using HF or BHF, These steps are sequentially repeated to form another oxide film, and finally the thinnest oxide film is formed. Note that the thickest oxide film is contaminated by the photoresist and is damaged when sequentially forming a thin oxide film.

The minimum gate length of the transistor is 0.5 μm
In the above process, the tunnel oxide film is the thinnest, so that the tunnel oxide film is formed last. Therefore,
The contamination of the tunnel oxide film by a resist or the like was minimized, and did not affect the data retention characteristics of the memory cell.

However, as shown in Table 1, in a process in which the minimum gate length is 0.35 μm or less, the thicknesses of the gate oxide film in the logic circuit and the tunnel oxide film of the nonvolatile memory cell are reversed, and the logic The gate thickness of the circuit is smaller. Therefore, the formation of the tunnel oxide film is performed before the formation of the gate oxide film of the logic circuit, so that the contamination of the tunnel oxide film with the photoresist cannot be prevented.
There is a concern that the data retention characteristics of the nonvolatile memory may deteriorate.

Therefore, a method for preventing the contamination of the tunnel oxide film with the photoresist has been proposed (for example, see Japanese Patent Application Laid-Open No. Hei 10-223850).

According to this method, as shown in FIG. 3A, a peripheral circuit area (hereinafter referred to as "high breakdown voltage area") 1A of a nonvolatile memory and a logic circuit area (hereinafter referred to as "logic area"). 1) A uniform oxide film 2 having a thickness of about 8 nm is formed on a semiconductor substrate 1 having three regions 1B and a nonvolatile memory cell region (hereinafter referred to as a "tunnel oxide film region") 1C. 3 is deposited. This polysilicon layer 3 is doped with impurities to the extent required for the floating gate of the nonvolatile memory cell.

Next, as shown in FIG. 3B, a photoresist 1 is formed by a known photolithography and etching process so as to cover only the tunnel oxide film region 1C.
Form 1C. Using the photoresist 11C as a mask, the polysilicon layer 3 on the high breakdown voltage region 1A and the logic region 1B is removed by dry etching. Further, the oxide film 2 on both regions is removed by wet etching using HF or BHF. The oxide film 2C and the polysilicon layer 3C remaining on the tunnel oxide film region 1C can function as a tunnel oxide film and a floating gate of a nonvolatile memory cell, respectively.

Subsequently, after removing the photoresist 11C, as shown in FIG.
Is thermally oxidized so that a film thickness of 11
The second oxide film 4 is formed with a thickness of about nm. Here, since the second oxide film 4C formed on the tunnel oxide film region 1C is formed by oxidizing the doped polysilicon layer, the oxide film 4C directly formed on the semiconductor substrate 1 is formed.
The film becomes thicker than A and 4B, and has a thickness of about 17 nm.

Next, as shown in FIG. 3D, a photoresist 12 having an opening only on the logic region 1B is formed.
Is formed, and the second oxide film 4B is removed by wet etching using the photoresist 12 as a mask.

Further, after the photoresist 12 is removed, as shown in FIG.
A third oxide film 5 having a thickness of about 5 nm is formed on the entire upper surface, and a polysilicon layer 6 is deposited thereon.

Next, as shown in FIG. 3F, a photoresist 1 having an opening only in the tunnel oxide film region 1C is formed.
3 is formed and the tunnel oxide film region 1C is formed by dry etching using the photoresist 13 as a mask.
Then, the third oxide film 5C and the second oxide film 4C are removed by wet etching.

By removing the photoresist 13, as shown in FIG. 3 (g), a film thickness of about 16 nm is formed on the high withstand voltage region 1A by a laminated film of the second oxide film 4A and the third oxide film 5A. A gate oxide film and a polysilicon layer 6B capable of functioning as a gate oxide film and a gate electrode are formed in the logic region 1B, and a gate oxide film and a polysilicon layer 6B having a thickness of about 5 nm by the third oxide film 5B are formed in the logic region 1B. A tunnel oxide film made of an oxide film 2C having a thickness of about 8 nm and a polysilicon layer 3C that can be a floating gate are formed.

According to such a method, it is possible to prevent the oxide film as thin as 10 nm or less from being contaminated by the photoresist.

[0017]

However, in the above method, in order to form oxide films having different thicknesses, it is necessary to perform a plurality of steps such as an oxidation step and an oxide film removal step a plurality of times. This leads to an increase in the number of steps. That is, after forming the oxide film 2C to be the tunnel oxide film, it is necessary to form the polysilicon layer 3C only on the tunnel oxide film 2C in order to prevent the contamination, and furthermore, the high breakdown voltage region 1A and the logic region The polysilicon layer 6 must be formed again on 1B. Further, the oxidation step, the photolithography and the etching step are performed in each of the regions 1A, 1B, and 1C.
It is necessary to perform each of them. As described above, in the case of manufacturing a single-layer polysilicon nonvolatile memory, the manufacturing cost increases each time the formation of the polysilicon layer increases once. In addition, since the number of steps such as an oxidation step is increased,
Manufacturing costs are further increased. The present invention has been made in view of the above problems, and minimizes contamination by a photoresist or the like, suppresses an increase in the number of manufacturing steps, and forms oxide films having different thicknesses. It is an object of the present invention to provide a method for manufacturing a semiconductor device, for example, a low-cost and highly-reliable semiconductor device in which a polysilicon non-volatile memory and a high-speed logic circuit are provided on the same substrate.

[0018]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a first semiconductor device and a second semiconductor device are provided on the same substrate and the thickness of a gate oxide film differs between the semiconductor devices. Forming an impurity diffusion layer having a controlled surface impurity concentration in a first semiconductor device formation region, forming a second gate oxide film on a second semiconductor device formation region, and simultaneously forming the first semiconductor device. There is provided a method of manufacturing a semiconductor device including a step of forming a gate oxide film thicker than the second gate oxide film in a formation region.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein the first, second and third semiconductor devices are provided on the same substrate, and the thickness of the gate oxide film differs between the semiconductor devices. Forming an impurity diffusion layer having a controlled surface impurity concentration in the first semiconductor device formation region, and forming a first oxide film on the first, second, and third semiconductor device formation regions; A resist is formed on the formation region, the first oxide film on the first and second semiconductor device formation regions is removed using the resist as a mask, and after removing the resist, the second and third semiconductor device formation regions are removed. There is provided a method of manufacturing a semiconductor device, comprising a step of forming a second oxide film thereon and simultaneously forming a third oxide film thicker than the second oxide film on the first semiconductor device formation region.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, when two or more types of semiconductor devices having gate oxide films having different thicknesses are formed on the same substrate, the thin gate oxide film is contaminated with a minimum number of manufacturing steps. It is a method of forming without.

In the present invention, a substrate for manufacturing a semiconductor device is not particularly limited as long as it can be used as a substrate of a semiconductor device. For example, an elemental semiconductor substrate such as silicon, germanium, etc. Ga
Various substrates such as compound semiconductors such as As and InGaAs can be used. Among them, a silicon substrate is preferable. The semiconductor substrate has a relatively low resistance (for example, about 20 Ωcm or less, preferably
(About 0 Ωcm) is preferable. Before the semiconductor device manufacturing process, various pretreatments,
For example, it is preferable to clean the substrate surface. It is preferable that the semiconductor substrate has an element isolation film formed in advance.

The semiconductor devices provided on the substrate include two or more types of semiconductor devices having different gate oxide film thicknesses, that is,
It is preferable that two or more types have different functions / operations or different applied voltages. For example, a combination of two or more of various semiconductor devices included in a logic circuit, a memory such as a RAM or a ROM, a microprocessor, a digital signal processing circuit, an analog circuit, and the like can be given. Among them, a combination of a memory such as an EEPROM or an EPROM and peripheral circuits and / or logic circuits is suitable.

In the method of manufacturing a semiconductor device according to the present invention, after preparing the semiconductor substrate as described above, first, the first
An impurity diffusion layer having a controlled surface impurity concentration is formed in a semiconductor device formation region.

The impurity diffusion layer may be formed by any method as long as the impurity concentration on the surface can be controlled to a predetermined value. For example, a region of the semiconductor substrate where the impurity diffusion layer is formed may be formed. Solid-phase diffusion, in which impurity-doped polysilicon is formed on the surface of the substrate, and diffusion of the impurity to the surface of the semiconductor substrate by heat treatment or the like; gas-phase diffusion, in which the semiconductor substrate is subjected to heat treatment in a gas atmosphere containing the impurity; There are various methods such as a method of ion implantation into the substrate. Above all, ion implantation is preferable. Note that the impurity diffusion layer needs to be formed on the surface of the semiconductor substrate,
The position or range can be adjusted by the thickness of the semiconductor substrate, oxidation conditions described later, and the like. For example, it is appropriate to form it at a position or range at a depth of about 0.1 μm to 0.3 μm from the surface of the semiconductor substrate.

The kind of impurities may be any kind as long as it contributes to accelerated oxidation of the impurity diffusion layer when the semiconductor substrate is oxidized under predetermined conditions, and examples thereof include phosphorus, arsenic, and boron. Of these, phosphorus and arsenic, which can form a nonvolatile memory with NMOS, are preferable. When phosphorus is used for ion implantation, the acceleration energy is about 80 to 200 keV, and when arsenic is used, the acceleration energy is about 50 to 200 keV.
About 200 keV is mentioned.

The surface impurity concentration of the impurity diffusion layer is not particularly limited as long as it can accelerate oxidation when the semiconductor substrate is oxidized under the predetermined conditions as described above. It can be appropriately adjusted depending on conditions and the like. Here, the accelerated oxidation means that the semiconductor substrate is more easily oxidized than the semiconductor substrate on which the impurity diffusion layer is not formed, and for example, is oxidized about 1.2 to 2 times, and further about 1.5 to 1.8 times. It is preferable to have an easy surface impurity concentration. Specifically, when phosphorus or arsenic is used as an impurity, the concentration is about 10 ¹⁹ to 10 ²⁰ cm ⁻³ .

Next, a gate oxide film is formed on the second semiconductor device formation region. Here, the second semiconductor device formation region means a region where the impurity diffusion layer as described above is not formed.

The method of forming the gate oxide film includes a thermal oxidation method and the like. Among them, the thermal oxidation method is preferred. Although the conditions of the thermal oxidation method are not particularly limited, for example, a method of performing a heat treatment in an atmosphere containing oxygen gas at a temperature range of about 850 to 950 ° C. for about 1 second to 100 minutes can be mentioned. By such heat treatment, the gate oxide film is
It can be formed with a film thickness of about 3 to 6 nm. At the same time, a gate oxide film thicker than the gate oxide film on the second semiconductor device formation region is formed in the first semiconductor device formation region with a thickness of 7 mm.
It can be formed to about 15 nm.

Further, in the present invention, three or more types of gate oxide films having different thicknesses are combined with an appropriate masking process, etching process, re-oxidation process, and the like. The present invention can be applied to a method for manufacturing a semiconductor device having gate oxide films having different thicknesses.

That is, first, similarly to the above, an impurity diffusion layer having a controlled surface impurity concentration is formed in the first semiconductor device formation region.

Next, a first oxide film is formed on the first, second and third semiconductor device formation regions substantially in the same manner as described above. At this time, the first oxide film formed on the second and third semiconductor device formation regions is, for example, about 10 to 25 nm. Further, since the impurity diffusion layer is formed in the first semiconductor device formation region, the first oxide film in this region is
A film thicker than the first oxide film on the second and third semiconductor device formation regions, for example, an oxide film having a thickness of about 14 to 50 nm is formed.

Further, a resist is formed on the third semiconductor device formation region, and the first oxide film on the first and second semiconductor device formation regions is removed using the resist as a mask. The formation of the resist and the removal of the oxide film can be performed by any method that is usually used in a semiconductor device manufacturing process. This allows the first oxide film to remain only in the third semiconductor device formation region.

Subsequently, after removing the resist, a second oxide film is formed on the second and third semiconductor device formation regions. The formation of the second oxide film includes the same method as described above. Of these, the thermal oxidation method is preferred. The thickness of the second oxide film is not particularly limited, but may be a thickness corresponding to the thickness of the thinnest gate oxide film or tunnel oxide film among the first, second, or third semiconductor devices. Is preferred. For example, about 3 to 8 nm is mentioned. At the same time, a third oxide film having a thickness of about 6 to 15 nm is formed in the first semiconductor device formation region.

By combining such a series of steps, ie, two oxidation steps, one mask step, and one etching step, the first semiconductor device formation region has a medium oxide film made of a third oxide film. A gate oxide film having a film thickness can be formed, a thinnest gate oxide film of the second oxide film can be formed in the second semiconductor device formation region, and the first oxide film can be formed in the third semiconductor device formation region. A thick gate oxide film can be formed by stacking the film and the second oxide film.

After this series of steps, formation of a gate electrode by forming and patterning a polysilicon layer,
Various semiconductor devices can be completed by combining ordinary semiconductor processes such as formation of source / drain regions, heat treatment, formation of an interlayer insulating film, formation of contact holes, and formation of wiring.

An embodiment of the method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

First, as shown in FIG. 1A, an element isolation region (not shown) is formed, and a peripheral circuit region (hereinafter, referred to as a "high breakdown voltage region") 21A of the nonvolatile memory, a logic circuit region (Hereinafter referred to as "logic region") 21B and a nonvolatile memory cell region (hereinafter referred to as "tunnel oxide film region").
An impurity is implanted into the semiconductor substrate 21 having three regions 21C. The impurity implantation at this time uses, for example, phosphorus or arsenic, and the implantation energy is 80 keV to 2 phosphorus.
00 keV, 50 keV to 200 keV for arsenic, and the implantation amount was 5 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ⁻² . Then 90
Heat treatment was performed for about 100 minutes or less in a temperature range of 0 to 950 ° C., and the impurity concentration on the surface was adjusted to 10 ¹⁹ to 10 ²⁰ cm ⁻³ . Thereby, impurity diffusion layer 22C is formed only on the surface of tunnel oxide film region 21C of semiconductor substrate 21.

Next, as shown in FIG. 1B, the obtained semiconductor substrate 21 is subjected to, for example, thermal oxidation to form an oxide film 23 having a thickness of about 10 nm to 25 nm. Note that the oxide film 23C formed in the tunnel oxide film region 23C is acceleratedly oxidized as compared with other regions.
The film is formed as thick as about 14 to 50 nm.

Subsequently, as shown in FIG. 1C, a resist 31A covering the high breakdown voltage region 21A and having openings in the logic region 21B and the tunnel oxide film region 21C is formed by a known photolithography and etching process. Form. Using this resist 31A as a mask, HF
Alternatively, the oxide films 23B and 23C on the logic region 21B and the tunnel oxide film region 21C are removed by wet etching using BHF.

Next, after the resist 31A is removed by a known method, a second oxide film 24 is formed as shown in FIG. At this time, as shown in FIG. 2, the oxide film is formed by oxidizing in an O ₂ + HCl gas atmosphere for several minutes in a temperature range of 850 ° C. to 950 ° C., and then in an inert gas atmosphere.
Oxidation is performed in such a sequence that annealing is performed for several tens of minutes in a temperature range of 50 ° C. to 1050 ° C. This allows
The thickness of the second oxide film 24 is such that the minimum gate length dimension is 0.25.
The thickness can be set to about 5 nm so as to correspond to the thickness of the gate oxide film in the logic region in the case of μm. on the other hand,
On tunnel oxide film region 21C, the film thickness is about 8 nm to 9 nm because the oxidation is accelerated by the impurity doped in advance.

Subsequently, as shown in FIG.
On the oxide film 24, a polysilicon layer 25 having a thickness of about 200 to 300 nm is deposited.

In this manner, 15 to 3
An oxide film and a polysilicon layer of about 0 nm, about 5 nm in the logic area, and about 8 to 9 nm in the tunnel oxide film area can be formed.

Thereafter, the polysilicon layer 25 is formed by a known method.
Is processed as a gate electrode, and an LSI is completed through processes such as an interlayer insulating film and metal wiring.

[0044]

According to the present invention, when forming a semiconductor device having two or more kinds of gate oxide films having different thicknesses, an impurity diffusion layer is formed in one semiconductor device formation region, and the impurity diffusion layer is mainly formed. By forming the gate oxide film after enabling the accelerated oxidation by controlling the impurity concentration of the layer, oxide films having different thicknesses can be simultaneously formed by one oxidation step. Therefore, it is possible to provide a method for manufacturing a semiconductor device in which manufacturing steps are prevented from being complicated and manufacturing costs are reduced.

In particular, when the impurity diffusion layer is formed using phosphorus or arsenic, multiplication oxidation can be easily realized.

When one of the semiconductor devices is a nonvolatile semiconductor device and the other is a logic semiconductor device, the gate oxide film of one semiconductor device is a tunnel oxide film, and the other is the gate oxide film of the logic semiconductor device. In the case of an oxide film, according to the present invention, it is possible to form an extremely thin gate oxide film or tunnel oxide film without being damaged by a resist, and a highly reliable semiconductor device can be provided.

Further, according to the present invention, by applying the above method to a method for manufacturing a semiconductor device having three or more different gate oxide films, it is possible to prevent contamination by a resist while minimizing the number of manufacturing steps. In addition, it is possible to manufacture a semiconductor device having a gate oxide film having a thickness corresponding to the function / function of various semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional process drawing of a main part for describing a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a graph showing a relationship between temperature and time for explaining an oxidation step in the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional process diagram of a main part for describing a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 21 semiconductor substrate 21A high breakdown voltage region 21B logic region 21C tunnel oxide film region 22C impurity diffusion layer 23, 23A, 23B, 23C oxide film 31A resist 24, 24A, 24B, 24C second oxide film 25, 25A, 25B, 25C polysilicon layer

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 29/792 F-term (Reference) 5F001 AA61 AA62 AD44 AG02 AG12 AG24 AG30 AG40 5F048 AB01 AB03 AB10 AC03 BB16 DA00 DA09 5F083 EP45 ER21 GA28 LA10 PR13 PR14 PR33 PR36 ZA07 ZA08 ZA12 ZA13 ZA15 5F101 BA34 BA35 BD27 BH03 BH07 BH09 BH16 BH21

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor device, wherein a first semiconductor device and a second semiconductor device are provided on the same substrate, and a thickness of a gate oxide film differs between the semiconductor devices, wherein a surface impurity concentration is controlled. Forming the impurity diffusion layer in the first semiconductor device formation region, forming a gate oxide film on the second semiconductor device formation region, and simultaneously forming a gate oxide film thicker than the gate oxide film in the first semiconductor device formation region. A method for manufacturing a semiconductor device, comprising a step of forming a film. 2. The method according to claim 1, wherein the impurity diffusion layer is formed using phosphorus and / or arsenic. 3. The semiconductor device according to claim 1, wherein the first and second semiconductor devices are a nonvolatile semiconductor device and a logic semiconductor device.
The method described in. 4. The semiconductor device according to claim 1, wherein one of the gate oxide films on the first and second semiconductor device formation regions is a tunnel oxide film and the other is a gate oxide film of a logic semiconductor device. The described method. 5. A method of manufacturing a semiconductor device in which first, second, and third semiconductor devices are provided on the same substrate, and a thickness of a gate oxide film differs between the semiconductor devices, wherein a surface impurity concentration is controlled. Forming the impurity diffusion layer in the first semiconductor device formation region, forming a first oxide film on the first, second, and third semiconductor device formation regions, and forming a resist on the third semiconductor device formation region. Forming a first oxide film on the first and second semiconductor device forming regions using the resist as a mask; removing the resist; and then forming a second oxide film on the second and third semiconductor device forming regions. Forming a third oxide film thicker than the second oxide film on the first semiconductor device formation region at the same time as forming the semiconductor device.