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JP2001284380A - Semiconductor device mounting method - Google Patents

Semiconductor device mounting method

Info

Publication number
JP2001284380A
JP2001284380A JP2000091050A JP2000091050A JP2001284380A JP 2001284380 A JP2001284380 A JP 2001284380A JP 2000091050 A JP2000091050 A JP 2000091050A JP 2000091050 A JP2000091050 A JP 2000091050A JP 2001284380 A JP2001284380 A JP 2001284380A
Authority
JP
Japan
Prior art keywords
semiconductor chip
circuit board
chip
semiconductor device
gap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000091050A
Other languages
Japanese (ja)
Inventor
Yuusuke Igarashi
優助 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2000091050A priority Critical patent/JP2001284380A/en
Publication of JP2001284380A publication Critical patent/JP2001284380A/en
Pending legal-status Critical Current

Links

Classifications

    • H10W72/20
    • H10W72/072
    • H10W72/07227
    • H10W72/07251
    • H10W72/227
    • H10W72/241
    • H10W72/257
    • H10W72/263
    • H10W72/267
    • H10W72/5522
    • H10W74/15
    • H10W90/724
    • H10W90/734

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】従来では、突起電極はフェースダウンボンディ
ングの際に、溶融した半田が接続パッドから流れ出し、
突起電極の高さが低下し、半導体チップと回路基板の隙
間が狭くなり、熱硬化性樹脂をこの隙間に注入できなく
なる問題点があった。 【解決手段】本発明では、表面に多数の突起電極2を形
成した半導体チップ1を準備し、半導体チップ1の表面
に突起電極2を加熱溶融しても溶融されない複数個の金
属のバンプ7を設け、回路基板3に半導体チップ1の突
起電極2を加熱溶融して固着される際に金属のバンプ7
で回路基板3と半導体チップ1の間に一定の隙間を形成
することにより従来の課題を解決した半導体装置の実装
方法を実現する。
(57) [Summary] [PROBLEMS] Conventionally, at the time of face-down bonding, molten solder flows out of a connection pad during face-down bonding,
There has been a problem that the height of the protruding electrode is reduced, the gap between the semiconductor chip and the circuit board is narrowed, and the thermosetting resin cannot be injected into this gap. According to the present invention, a semiconductor chip having a large number of protruding electrodes formed on a surface thereof is prepared. When the bumps 2 of the semiconductor chip 1 are fixed to the circuit board 3 by heating and melting, the metal bumps 7
Thus, a constant gap is formed between the circuit board 3 and the semiconductor chip 1 to realize a semiconductor device mounting method which solves the conventional problem.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の実装方
法、特に多数の突起電極を有するチップの実装方法に関
する。
The present invention relates to a method of mounting a semiconductor device, and more particularly to a method of mounting a chip having a large number of projecting electrodes.

【0002】[0002]

【従来の技術】図4にフリップチップ方式の半導体装置
の実装方法を示す。
2. Description of the Related Art FIG. 4 shows a method of mounting a flip-chip type semiconductor device.

【0003】半導体チップ1の一主面には周辺に一定の
間隔で多数の突起電極2を形成している。すなわち、突
起電極2を形成する部分に内部の回路と接続されたニッ
ケル層と金層からなる下地電極6を設け、半田リフロー
装置でこの下地電極6の上に高さ100μmの半田より
なる突起電極2を設ける。続いて、突起電極2を下に向
けてフェースダウンボンディングにより回路基板3の銅
箔等で形成された接続パッド4にこの突起電極2を接続
する。この工程は還元雰囲気中で突起電極2を加熱溶融
させて、半導体チップ1を回路基板3にフェースダウン
ボンディングして実装する。この際に、突起電極2の半
田は接続パッド4から導電路を約200μm位流出し、
突起電極2の高さは元の100μmから20μm以下ま
で減少する。このために半導体チップ1と回路基板3の
隙間は極めて狭くなる。
[0003] On one main surface of a semiconductor chip 1, a number of protruding electrodes 2 are formed at regular intervals around the periphery. That is, a base electrode 6 made of a nickel layer and a gold layer connected to an internal circuit is provided in a portion where the bump electrode 2 is formed, and a bump electrode made of 100 μm high solder is provided on the base electrode 6 by a solder reflow apparatus. 2 is provided. Subsequently, the protruding electrode 2 is connected to a connection pad 4 formed of a copper foil or the like of the circuit board 3 by face-down bonding with the protruding electrode 2 facing downward. In this step, the bump electrode 2 is heated and melted in a reducing atmosphere, and the semiconductor chip 1 is mounted on the circuit board 3 by face-down bonding. At this time, the solder of the protruding electrode 2 flows out of the conductive path from the connection pad 4 by about 200 μm,
The height of the protruding electrode 2 decreases from the original 100 μm to 20 μm or less. Therefore, the gap between the semiconductor chip 1 and the circuit board 3 becomes extremely narrow.

【0004】この半導体チップ1と回路基板3は熱膨張
係数が異なるのでこのストレスが突起電極2の半田に加
わり、突起電極2が接続パッド4から剥がれるのを防止
するためと、外気から半導体チップ1を保護するために
半導体チップ1と回路基板3の隙間には熱硬化性樹脂5
が注入されている。
Since the semiconductor chip 1 and the circuit board 3 have different coefficients of thermal expansion, the stress is applied to the solder of the protruding electrodes 2 to prevent the protruding electrodes 2 from peeling off from the connection pads 4 and to prevent the semiconductor chip 1 from being exposed to the outside air. A thermosetting resin 5 is provided in the gap between the semiconductor chip 1 and the circuit board 3 to protect the
Has been injected.

【0005】最近では素子の多ピン化のために、突起電
極2のピッチはどんどん狭くなり、その高さも100μ
mから50μmに移行しつつある。
Recently, the pitch of the protruding electrodes 2 has been steadily reduced due to the increase in the number of pins of the device, and the height of the protruding electrodes 2 has been reduced to 100 μm.
m to 50 μm.

【0006】[0006]

【発明が解決しようとする課題】かかる従来の半導体装
置の実装方法では、種々の問題点を有していた。
The conventional method for mounting a semiconductor device has various problems.

【0007】突起電極2は約100μmの高さに形成さ
れるが、フェースダウンボンディングの際に溶融した半
田が接続パッド4からそれと接続された導電路まで流れ
出し、突起電極2の高さが約20μmまで低下する。こ
のために半導体チップ1と回路基板3の隙間が約20μ
mとなり、熱硬化性樹脂5を毛細管現象を利用してこの
隙間に注入できなくなる。特に、突起電極2の高さが5
0μmとなるとさらにこの傾向は強くなり、ひどい場合
は突起電極2の高さが無くなり、熱硬化性樹脂5の注入
は不可能となる。
The protruding electrode 2 is formed to a height of about 100 μm. During the face-down bonding, the molten solder flows out from the connection pad 4 to the conductive path connected thereto, and the height of the protruding electrode 2 becomes about 20 μm. Down to Therefore, the gap between the semiconductor chip 1 and the circuit board 3 is about 20 μm.
m, and the thermosetting resin 5 cannot be injected into this gap by utilizing the capillary phenomenon. In particular, when the height of the projecting electrode 2 is 5
When the thickness is 0 μm, this tendency is further increased. In a severe case, the height of the protruding electrode 2 is lost, and the injection of the thermosetting resin 5 becomes impossible.

【0008】このために半導体チップ1は熱硬化性樹脂
5で保護することができなくなり、熱ストレスで突起電
極2が回路基板3の接続パッド4から剥がれたり、半導
体チップ1を外気から十分に保護できなくなる。
As a result, the semiconductor chip 1 cannot be protected by the thermosetting resin 5, and the protruding electrodes 2 are peeled off from the connection pads 4 of the circuit board 3 by thermal stress, and the semiconductor chip 1 is sufficiently protected from the outside air. become unable.

【0009】[0009]

【課題を解決するための手段】本発明はかかる問題点に
鑑みてなされ、表面に多数の突起電極を形成したチップ
を準備し、前記チップの表面に前記突起電極を加熱溶融
しても溶融されない複数個の金属のバンプを設け、回路
基板に前記チップの突起電極を加熱溶融して固着される
際に前記金属のバンプで前記回路基板と前記チップの間
に一定の隙間を形成することを特徴を有する。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a chip having a large number of projecting electrodes formed on a surface thereof is not melted by heating and melting the projecting electrode on the surface of the chip. A plurality of metal bumps are provided, and a fixed gap is formed between the circuit board and the chip by the metal bumps when the bump electrodes of the chip are fixed to the circuit board by heating and melting. Having.

【0010】[0010]

【発明の実施の形態】本発明に依る半導体装置の実装方
法を図1から図3を参照して説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for mounting a semiconductor device according to the present invention will be described with reference to FIGS.

【0011】図1は本発明に用いる半導体チップの平面
図を示している。半導体チップ1の一主面には周辺に一
定の間隔で多数の突起電極2を形成している。すなわ
ち、突起電極2を形成する部分に内部の回路と接続され
たニッケル層と金層からなる下地電極6を設け、半田リ
フロー装置でこの下地電極6の上に高さ100μmの半
田よりなる突起電極2を設ける。
FIG. 1 is a plan view of a semiconductor chip used in the present invention. On one main surface of the semiconductor chip 1, a number of protruding electrodes 2 are formed at regular intervals around the periphery. That is, a base electrode 6 made of a nickel layer and a gold layer connected to an internal circuit is provided in a portion where the bump electrode 2 is formed, and a bump electrode made of 100 μm high solder is provided on the base electrode 6 by a solder reflow apparatus. 2 is provided.

【0012】本発明の特徴は複数個の金属のバンプ7を
設けることにある。金属のバンプ7は25μmから30
μm直径の金線をボールボンディング装置で水素トーチ
を用いて加熱溶融して形成したボールを半導体チップ1
の4角に設けた下地電極6に熱圧着して形成する。この
金属のバンプ7は一例として、直径が60μmから80
μmで高さが約50μmに形成される。金属のバンプ7
は少なくとも半導体チップ1の対角線上の2角に設けて
半導体チップ1と回路基板3との隙間を50μm維持す
るように作用させる。理想的には金属のバンプ7は半導
体チップ1の4角に設けると、半導体チップ1を安定し
て支持することできる。
A feature of the present invention is to provide a plurality of metal bumps 7. Metal bump 7 should be between 25 μm and 30
A ball formed by heating and melting a gold wire having a diameter of μm using a hydrogen torch with a ball bonding apparatus is used as a semiconductor chip 1.
Are formed by thermocompression bonding to the base electrodes 6 provided at the four corners. The metal bump 7 has a diameter of, for example, 60 μm to 80 μm.
The height is about 50 μm. Metal bump 7
Are provided at least at two corners on the diagonal line of the semiconductor chip 1 so that the gap between the semiconductor chip 1 and the circuit board 3 is maintained at 50 μm. Ideally, if the metal bumps 7 are provided at the four corners of the semiconductor chip 1, the semiconductor chip 1 can be stably supported.

【0013】また金属のバンプ7としては約50μmの
厚みの金属片で構成できる。鉄や銅の金属片を半導体チ
ップ1の2角から4角の位置に接着剤等で固着する。
The metal bump 7 can be made of a metal piece having a thickness of about 50 μm. A metal piece of iron or copper is fixed to a position between two and four corners of the semiconductor chip 1 with an adhesive or the like.

【0014】上記した半導体チップ1は突起電極2を下
側にして、回路基板3に設けた銅箔等で形成された導電
路に接続された接続パッド4に突起電極2を当接させ
て、還元雰囲気中、またはN2雰囲気中、あるいは大気
雰囲気中で半田接合にフラックスを用いて突起電極2を
加熱溶融させて半導体チップ1を回路基板3にフェース
ダウンボンディングして実装する。この際に、突起電極
2の半田は接続パッド4から導電路を約200μm位流
出し、突起電極2の高さは元の100μmから減少する
が、金属のバンプ7は溶融せず半導体チップ1は回路基
板3と約50μmの隙間を形成して支えられる。従っ
て、突起電極2は貝柱状になり、接続パッド4と良好な
接続が得られる。
In the semiconductor chip 1 described above, the protruding electrode 2 is brought into contact with a connection pad 4 connected to a conductive path formed of a copper foil or the like provided on the circuit board 3 with the protruding electrode 2 facing downward. In a reducing atmosphere, an N 2 atmosphere, or an air atmosphere, the projecting electrode 2 is heated and melted using a flux for solder bonding, and the semiconductor chip 1 is mounted on the circuit board 3 by face-down bonding. At this time, the solder of the protruding electrode 2 flows out of the connection pad 4 through the conductive path by about 200 μm, and the height of the protruding electrode 2 is reduced from the original 100 μm, but the metal bump 7 does not melt and the semiconductor chip 1 It is supported by forming a gap of about 50 μm with the circuit board 3. Accordingly, the protruding electrode 2 has a column shape, and good connection with the connection pad 4 can be obtained.

【0015】半導体チップ1と回路基板3との隙間には
エポキシ樹脂等で構成されるアンダーフィル樹脂となる
熱硬化性樹脂5が毛細管現象を利用して充填される。こ
の熱硬化性樹脂5は半導体チップ1のサイドに液状のも
のを滴下してこの隙間に注入される。熱硬化性樹脂5は
半導体チップ1と回路基板3の熱膨張係数の差異により
発生するストレスが突起電極2の半田に加わり、突起電
極2が接続パッド4から剥がれるのを防止する。また、
外気から半導体チップ1を外気から保護する働きも有す
る。
A space between the semiconductor chip 1 and the circuit board 3 is filled with a thermosetting resin 5 serving as an underfill resin made of an epoxy resin or the like by utilizing a capillary phenomenon. This thermosetting resin 5 is dropped into a liquid on the side of the semiconductor chip 1 and injected into the gap. The thermosetting resin 5 prevents a stress generated due to a difference in thermal expansion coefficient between the semiconductor chip 1 and the circuit board 3 from being applied to the solder of the projecting electrode 2, thereby preventing the projecting electrode 2 from peeling off from the connection pad 4. Also,
It also has a function of protecting the semiconductor chip 1 from the outside air.

【0016】[0016]

【発明の効果】本発明に依れば、第1に半導体チップ1
の表面に突起電極2を加熱溶融しても溶融されない複数
個の金属のバンプ7を設け、回路基板3に半導体チップ
1の突起電極2を加熱溶融して固着される際に金属のバ
ンプ7で回路基板3と半導体チップ1の間に一定の隙間
を形成することにより、熱硬化性樹脂5の注入を毛細管
現象を利用して短時間に行え、しかも一定の隙間である
ために均一に注入できる利点を有する。
According to the present invention, first, the semiconductor chip 1
A plurality of metal bumps 7 that are not melted even when the protruding electrode 2 is heated and melted are provided on the surface of the semiconductor chip 1. By forming a fixed gap between the circuit board 3 and the semiconductor chip 1, the thermosetting resin 5 can be injected in a short time by utilizing the capillary phenomenon, and can be uniformly injected because of the fixed gap. Has advantages.

【0017】第2に、金属のバンプ7はボールボンディ
ングの際に形成される一定の太さのボンディングワイヤ
ーから形成するので、均一の高さに形成でき、しかも既
存のボンディング装置を活用でき、新規な設備投資も不
要である。
Second, since the metal bumps 7 are formed from bonding wires having a constant thickness formed during ball bonding, they can be formed at a uniform height, and the existing bonding apparatus can be used, and a new method can be used. No capital investment is required.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の実装方法を説明する平面
図である。
FIG. 1 is a plan view illustrating a method for mounting a semiconductor device of the present invention.

【図2】本発明の半導体装置の実装方法を説明する断面
図であり、図1のA−A線の断面図である。
FIG. 2 is a cross-sectional view illustrating a method for mounting the semiconductor device of the present invention, and is a cross-sectional view taken along line AA of FIG.

【図3】本発明の半導体装置の実装方法を説明する断面
図である。
FIG. 3 is a sectional view illustrating a method for mounting a semiconductor device of the present invention.

【図4】従来の半導体装置の実装方法を説明する断面図
である。
FIG. 4 is a cross-sectional view illustrating a conventional method for mounting a semiconductor device.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 表面に多数の突起電極を形成したチップ
を準備し、前記チップの表面に前記突起電極を加熱溶融
しても溶融されない複数個の金属のバンプを設け、回路
基板に前記チップの突起電極を加熱溶融して固着される
際に前記金属のバンプで前記回路基板と前記チップの間
に一定の隙間を形成することを特徴とする半導体装置の
実装方法。
1. A chip having a large number of protruding electrodes formed on a surface thereof is provided, and a plurality of metal bumps which are not melted by heating and melting the protruding electrodes are provided on a surface of the chip, and the chip of the chip is mounted on a circuit board. A method of mounting a semiconductor device, wherein a fixed gap is formed between the circuit board and the chip with the metal bump when the protruding electrode is fixed by heating and melting.
【請求項2】 前記突起電極は半田で形成されることを
特徴とする請求項1記載の半導体装置の実装方法。
2. The method according to claim 1, wherein the protruding electrodes are formed of solder.
【請求項3】 前記金属のバンプは金線のボンディング
ワイヤーを溶融して形成したボールを固着して形成され
ることを特徴とする請求項1記載の半導体装置の実装方
法。
3. The method according to claim 1, wherein the metal bump is formed by fixing a ball formed by melting a bonding wire of a gold wire.
【請求項4】 前記金属のバンプは前記チップ表面の2
カ所以上に設けられることを特徴とすることを特徴とす
る請求項1記載の半導体装置の実装方法。
4. The method according to claim 1, wherein the metal bumps are formed on the chip surface.
2. The method according to claim 1, wherein the semiconductor device is provided at a plurality of locations.
JP2000091050A 2000-03-29 2000-03-29 Semiconductor device mounting method Pending JP2001284380A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000091050A JP2001284380A (en) 2000-03-29 2000-03-29 Semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000091050A JP2001284380A (en) 2000-03-29 2000-03-29 Semiconductor device mounting method

Publications (1)

Publication Number Publication Date
JP2001284380A true JP2001284380A (en) 2001-10-12

Family

ID=18606565

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000091050A Pending JP2001284380A (en) 2000-03-29 2000-03-29 Semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JP2001284380A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018195664A (en) * 2017-05-16 2018-12-06 富士通株式会社 Semiconductor device and manufacturing method thereof
JP2024083357A (en) * 2017-09-19 2024-06-21 グーグル エルエルシー Pillars as stoppers for precise chip-to-chip isolation

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018195664A (en) * 2017-05-16 2018-12-06 富士通株式会社 Semiconductor device and manufacturing method thereof
JP2024083357A (en) * 2017-09-19 2024-06-21 グーグル エルエルシー Pillars as stoppers for precise chip-to-chip isolation
US12142590B2 (en) 2017-09-19 2024-11-12 Google Llc Pillars as stops for precise chip-to-chip separation
JP7608655B2 (en) 2017-09-19 2025-01-06 グーグル エルエルシー Pillars as stoppers for precise chip-to-chip isolation

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