JP2001282714A - Multi-camera data transfer system and data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable power-saved serial communication with a simple configuration without requiring a USB interface, for which the control by means of a host computer is required. SOLUTION: Image data simultaneously or successively provided by plural electronic cameras 2B-NB for storing respectively picked-up image signals are successively read out at a prescribed timing and serially outputted and while the image data stored in the electronic camera are beind read out or transmitted, the other electronic camera is turned into standby mode state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system for image data, and more particularly to a data transfer system suitable for transferring image data obtained by a terminal device to another terminal. The present invention also relates to optimization of a wiring problem of a digital output imaging unit using a CMOS sensor and simplification of system design.

[0002]

2. Description of the Related Art A data transfer system for serially communicating data is frequently used in a field where a simple configuration is required since a communication medium is a single bus line.

As an example in which such a data transfer system is used, a single camera (TV camera or electronic camera) or a plurality of cameras, that is, a multi-camera is provided at a predetermined position, and an image signal obtained by these cameras is converted into an A / D signal. 2. Description of the Related Art An image data transfer method of converting image data as digital data by a converter or the like, temporarily storing the converted image data in a frame memory or a line buffer, and transmitting the image data to a bus via a serial interface has been put to practical use.

The method of transmitting the output of a camera through a serial line is effective in greatly reducing the number of physical wires and reducing the system construction cost. For example, when a camera is installed in a car. In such an application, an analog image signal having a small number of wires has been conventionally used. However, it is more convenient for the device that receives or utilizes an image to be digital image data. However, 8-bit or 16-bit digital parallel signals are not suitable for long-distance wiring. Because of the cost of wiring and the difficulty in managing data delays,
Not suitable for long distance transmission.

As another example, Cellular telephones
In such a small mobile device as described above, there is a problem that a digital parallel signal requiring a large number of pins for a connector increases the size of the device.

Even when a plurality of image data are obtained by using a multi-camera, a parallel image signal requiring a large number of signal lines makes wiring and a system complicated and expensive. For example, a surveillance camera system using a plurality of cameras is an example.

[0007] In a vehicle-mounted safety confirmation camera, etc., it is necessary to monitor a plurality of cameras directed in a plurality of directions with one terminal. In-house wiring may extend to about 8m,
Conventional digital wiring is expensive. In the medical field, the contours and heat distribution of the human body are acquired by ordinary cameras and infrared cameras, and the images acquired by these cameras are superimposed and displayed as a base for diagnosis, or the imaging target is acquired using an ultraviolet camera. In some cases, an image having a clear outline is acquired, and in the field of industrial scope, an image in a forward direction or a lateral direction is simultaneously acquired. Also in these examples, there is a demand for reduction of the system cost including wiring and simplification of the system itself.

On the other hand, digitization of an image output signal in an image pickup means is progressing. In other words, the output of the photoelectric conversion means is A / D converted, a digital color process circuit is formed using circuit means suitable for IC implementation such as DSP, and image output is performed.
Imaging means for digital output in RGB or YUV format is increasing. With such an imaging means, there are 24 output signal lines in the case of 8-bit digital output in RGB format.

[0009] In a CMOS sensor suitable for IC integration, the digital color process described above is formed on the same semiconductor chip as the photoelectric conversion means to constitute a so-called one-chip camera. Is possible. Such CMOS imaging means has been incorporated in mobile phones, PDAs, and many battery-driven information devices because of their small size and low power consumption.

[0010] The problem of wiring of digital image signals and the problem of data transfer, which generate many output lines, have become major issues in reducing costs and miniaturization of terminals and systems.

As an example of a communication system for serially communicating data, there is an example using a USB in a personal computer.

FIG. 7 shows a configuration of a multi-camera data transfer system as an example of this type of communication system. A plurality of terminals (for example, a multi-camera) are connected to a plurality of U.S.A.
It is connected to the B interface (I / F). USB
The interface 102A includes the CPU 102B and the RAM 1
02C, which is built into (attached to) the personal computer 102 having a hard disk 103B and functions as a master USB interface.
SB interface 104A is for keyboard 104B,
USB interface 105A for mouse 105B, U
SB interface 106A is for monitor 106B, U
The SB interface 108A is used for the modem 108B, and the USB interface 107A is connected to a bus which is a communication medium for image data transmitted from the multi camera on the image transmission side. These US
The B interface is connected to various devices via the USB hub 101.

According to the configuration shown in FIG. 7, image data obtained by each of the multi-cameras can be transmitted by serial communication using the USB interface 107A.

Japanese Patent Application Laid-Open No. H11-122636 discloses a video signal transmission device which has PLL circuits in both devices and can transmit digital video signals serially and accurately.

[0015]

On the other hand, the above-described communication system using the USB interface has the advantage of a simple bus (cable) because serial communication can be performed, but the USB interface is a host such as a personal computer. Computer control is required, and not only a host computer is indispensable, but also the protocol is complicated.

As shown in FIG. 7, the USB interface is standardized on the premise that a plurality of terminals of different purposes are connected. Not suitable for connection.

Further, the video signal transmission device disclosed in Japanese Patent Application Laid-Open No. H11-122636 does not consider accurate digital image signal transmission in both directions, and can perform serial communication of data obtained in a terminal with minimum power consumption. Not considered.

The image signals obtained by the multi-camera are temporarily stored in memories provided in a one-to-one correspondence with each camera, and the image signals read from the memories are sequentially transmitted to the bus. Therefore, since the memory is provided for the camera, the configuration is complicated, and there is a problem of cost.

It is therefore an object of the present invention to provide a highly reliable camera data transfer system and a data transfer system which can perform serial communication with a simple configuration without requiring a USB interface which requires control by a host computer. It is in.

It is another object of the present invention to provide a multi-camera data transfer system and a data transfer system capable of serially communicating data obtained by a terminal such as a camera with minimum power consumption.

It is still another object of the present invention to provide a highly reliable camera data transfer method and data transfer method which ensure data synchronization confirmation and data transmission confirmation.

Another object of the present invention is to provide a data transfer system which solves the wiring problem of digital image signals and simplifies an image system.

[0023]

In order to solve the above-mentioned problems, a camera data transfer system and a data transfer system according to the present invention employ the following characteristic configurations.

(1) A plurality of image pickup means each outputting an image signal picked up, and a digital image of a parallel output which is provided for each of the plurality of image pickup means and is simultaneously or sequentially outputted from the image pickup means. Means for converting data to a serial signal, output means for sequentially outputting the serial signal at a predetermined timing, and a serial interface for transmitting the output serial data signal to a communication destination and performing serial transfer, A multi-camera data transfer method in which the other imaging means are in a standby mode while reading or transmitting image data from the imaging means.

(2) The multi-camera data transfer system according to the above (1), wherein the plurality of imaging means are imaging means for imaging in mutually different imaging wavelength regions or in mutually different directions.

(3) The multi-camera data transfer method according to (1), wherein the predetermined timing is determined by a vertical synchronization signal.

(4) In a data transfer system for transferring data between a first device and a second device, the first device includes an image pickup means for outputting an image signal in a parallel signal format, and the image pickup means A P / S converter that performs parallel / serial conversion of an image signal, which is a parallel signal obtained by imaging in the first PLL circuit, based on a clock output from the first PLL circuit, and converts the serial-converted signal into an LVDS ( Low Vo
LVDS for converting into a signal according to a signal differential transmission method and transferring the converted LVDS signal to a receiving side via a transmission line at high speed LVDS data.
A driver circuit; and a serial / parallel conversion circuit that converts an image signal received via the transmission line into parallel data based on a clock from the first PLL circuit. An LVDS receiving circuit for receiving an image signal transferred via the transmission line,
A serial / parallel conversion circuit for converting the received image signal into parallel data based on a clock from the second PLL circuit, a P / S converter for performing parallel / serial conversion on image data to be transmitted, The converted signal is converted into a signal in accordance with the LVDS signal transmission system, and the high-speed signal is transmitted to the first device via the transmission line.
And a LVDS driver circuit for transferring VDS data.

(5) In a data transfer method for transferring data between a first device and a second device, the first device includes an image pickup means for outputting an image signal in a parallel signal format, and the image pickup means A P / S converter that performs parallel / serial conversion of an image signal, which is a parallel signal obtained by imaging in the first PLL circuit, based on a clock output from the first PLL circuit, and converts the serial-converted signal into an LVDS ( Low Vo
LVDS for converting into a signal according to a signal differential transmission method and transferring the converted LVDS signal to a receiving side via a transmission line at high speed LVDS data.
A driver circuit, wherein the second device side receives an image signal transferred via the transmission line, based on an LVDS receiving circuit, and a clock from the second PLL circuit.
A serial / parallel conversion circuit for converting the received image signal into parallel data, and converting the serially converted signal to L
A data transfer method comprising VDS.

(6) First PL in the first device
The lock signal generated from the L circuit is sent to the second device, and the second device inverts the received clock signal when it determines that the received lock signal is not a correct synchronization clock, and locks the received clock signal. The received clock signal is sent to the first device side as a response signal, and when it is determined that the received lock signal is the correct synchronous clock, the received clock signal is not inverted, and is directly sent to the first device side as a lock response signal. The first device determines whether the lock is accurate based on the received lock response signal and the lock signal. If the lock is not accurate, the first device transmits the previously transmitted data to the first device. (4) The data transfer method of (4) or (5), wherein the data is retransmitted to the device side.

(7) The first device outputs a lock detection signal indicating whether or not the lock is accurate by a differential amplifier to which the lock response signal and the lock signal are input. ) Data transfer method.

(8) The first device sends out a PLL lock signal together with the transmission data, and the second device
The second PLL based on the received PLL lock signal;
If it is determined that the circuit is locked, the lock signal is inverted and returned to the first device as a lock response signal, and the first device receives the transmitted lock signal and the returned lock signal. When it is determined based on the response signal that the previously transmitted data is not transmitted correctly,
A data transfer method for retransmitting the previously transmitted data to the first device.

(9) The data transfer method according to the above (8), wherein the retransmission is performed when the image of one frame is transmitted, from the beginning of the image.

(10) The data transfer method according to (7), wherein the retransmission is performed from the first horizontal synchronizing signal portion of the image in which the error has occurred.

(11) The data transfer method according to the above (8), wherein the retransmission is performed by retransmitting from a data portion where an error has occurred.

(12) The data transfer method according to the above (8), wherein the retransmission is to retransmit only the data in which an error has occurred.

(13) The data transfer method according to the above (8), wherein when the error occurs, the lock frequency is changed in a direction to lower the lock frequency of the PLL to improve the reliability of data transfer.

(14) The data transfer method according to any one of (1) to (13), wherein the data has a unit data string of 2 ⁿ bits.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a multi-camera data transfer system and a data transfer system according to the present invention will be described below in detail with reference to the accompanying drawings.

In FIG. 1, a serial interface (I / F) 2A provided for a plurality of cameras 2B to NB
Image data transmitted from each of the .NA is transmitted to the transmission destination by serial communication via the high-speed serial interface (I / F) converter 1.

In the embodiment of the present invention, each of the plurality of cameras simultaneously or sequentially captures an image of an object to be photographed by an image sensor and then accumulates image signals. I /
F) Transmitted via serial communication via 1. And
While reading and transmitting the image data stored in one camera, the other cameras are in the standby mode, and the data is stored. Therefore, the power consumption of the entire system is substantially the power consumption of one camera.

In this way, images can be simultaneously captured by a plurality of cameras and switched on a frame basis, that is, images can be taken in response to a vertical synchronizing signal, and reading can be performed on a camera basis. At this time, images obtained by a plurality of cameras can be sequentially transmitted by changing the imaging wavelength of the cameras or by imaging from different directions.

FIG. 2 shows the relationship between the imaging timing of a plurality of cameras (N units), the vertical synchronization signal, and the image data transfer timing in the embodiment shown in FIG.

In response to the fall of the imaging timing T, imaging by a plurality of cameras is performed simultaneously. At this time, after each camera of the plurality of cameras captures an image, the obtained image signal is accumulated. The vertical synchronization signal V is generated in response to the imaging timing, and the image data stored in the plurality of cameras is sequentially transferred in response to each vertical synchronization signal.
That is, the first falling timing V of the vertical synchronization signal
In step 1, the image signal stored in the first camera is transferred.
The image signal stored in the second camera is transferred at the second falling timing V2, and the image signal stored in the third camera is transferred at the third falling timing V3. The image signals stored in the fourth camera are transferred at the downstream timing V4, and the image signals stored in the Nth camera are sequentially transferred at the Nth falling timing VN.

According to the above-described embodiment, data obtained by each of a plurality of terminals (cameras) can be sequentially transferred as serial data without using a USB which requires control of a host computer.

FIG. 3 shows the high-speed serial I / O in FIG.
An example of the configuration of the F converter 1 is shown. The high-speed serial I / F converter 1 is provided on each of a transmitting side (camera side) and a receiving side (image signal receiving side). In the following description, it is assumed that bidirectional communication is performed, and the functions are reversed between transmission and reception. Therefore, it is assumed that bidirectional communication is performed between the first device and the second device.

At the time of transmission, the first device converts the image signal obtained by the P / S converter 12 by the camera into a parallel /
Serial-converted and converted the serial-converted signal into LVDS
The driver circuit (code circuit) 13 provides a so-called LV
The signal is converted into a signal according to a DS (Low Voltage Differential Signaling) signal transmission system. LV thus obtained
The DS signal is transferred at a high speed LVDS data via a relatively thin and easy-to-handle transmission line (bus) 10 such as a twisted cable. The signal transmission by the LVDS signal is a serial transmission standard: TIA / EIA-64.
It is performed according to four standards.

The serial image data output via the bus 10 is configured as an LVDS signal corresponding to each bit at the image data clock cycle.

The image signal transferred via the bus 10 is
The data is received by the LVDS receiving circuit (decoding circuit) 21 of the second device as the receiving side, and is transmitted to the above-described USB interface or the like as parallel data by the serial / parallel conversion circuit 23 based on the clock from the PLL circuit 22.

On the other hand, image data to be transmitted at the time of transmission by the second device is subjected to parallel / serial conversion by a P / S converter 25 similar to the P / S converter 12, and a signal obtained by serial conversion is converted into an LVDS signal. Driver circuit (code circuit)
At 24, the signal is converted into a signal in accordance with the LVDS signal transmission method, and the high-speed LVD signal is transmitted to the first device via the bus 10.
S data is transferred.

At the time of reception by the first device, the image signal received via the bus 10 is received by the LVDS receiving circuit 14 similar to the LVDS receiving circuit (decoding circuit) 21,
Based on the clock from the PLL circuit 11, the serial / parallel converter 15 sends the data as parallel data to the USB interface or the like.

In the embodiment of the present invention, the following two-way communication system is employed in order to more reliably confirm the synchronization of the image data and the confirmation of the data transmission.

Referring to FIG. 3, after the lock signal output from the PLL circuit 11 of the first device is amplified by the transmission amplifier 16, the lock signal is relatively thin and easy to handle such as a twisted cable. The lock signal received by the receiving amplifier 26 via the bus 20 is sent to the PLL circuit 22 to generate the clock while transmitting the lock signal to the second device via the bus 20. This lock signal is input to the inverter 27. The inversion operation by the inverter 27 is performed by the PLL circuit 22.
Is performed in accordance with the lock enable / disable signal output from
When it is determined that the lock signal received by the L circuit 22 is not a correct synchronization clock, the received clock signal is inverted and sent to the first device via the transmission amplifier 28 and the bus 20 as a lock response signal.

When it is determined that the lock signal received by the PLL circuit 22 is the correct synchronous clock, the inverter 27 does not invert the received clock signal, and as the lock response signal as it is via the transmission amplifier 28 and the bus 20. 1 device side.

On the first device side, the lock response signal received via the bus 20 is received by the receiving amplifier 17 and is input to the differential amplifier 18. A lock signal from the PLL circuit 11 is also input to the differential amplifier 18, and an output signal thereof is obtained as a lock detection signal. Based on the lock detection signal, it can be determined whether or not the lock is accurate.

In FIG. 3, the transmission data transmitted from the first device and the transmission data transmitted from the second device are transmitted and received with the same polarity. For example, as shown in FIG. When the first device is a master and the second and unshown devices are slaves, the LV of the master device is
The output from the DS driver circuit (code circuit) 30 may be an inverted output, and the output may be inverted again by the LVDS receiving circuit (decoding circuit) 31 of the slave device. In this case, since the polarity of the data can be determined as transmission data from the master or transmission data from the slave, processing, circuits, and the like for separately determining whether transmission data from another slave or transmission data from the master are required. I can omit it.

FIG. 5 shows an example of the structure of transmitted / received data. This data configuration is roughly divided into a data string start bit and a stop bit as a PLL lock detection signal, a control data portion surrounded by these bits, and an actual image data portion. The control data part is
For example, vertical and horizontal synchronization signals as image synchronization signals, signals for error checking of data strings, for example,
A parity check signal as a data check signal, a C / D (command / data) signal indicating whether a data string is equivalent to a command or data, an R / W signal indicating whether a signal is transmitted from a transmission side to a reception side or vice versa, data There is a signal (not shown) indicating whether or not is valid. The data check signal is
It is an error check signal such as a parity check, and is a signal for checking the state of a set of signals from start to stop. It is possible to check the data state more reliably than when there is no signal.

Next, a description will be given, with reference to FIG. 6, of the processing in the above-described embodiment when the PLL is unlocked during data transmission / reception or when it is determined by an error check or the like that the transmitted data has an error. FIG.
FIG. 6 is a timing chart for explaining an error detection method at the time of data transmission / reception.

First, an error detection method in data transmission / reception will be described with reference to FIG. As mentioned above,
From the transmitting (first device) side, a PLL lock signal is transmitted in accordance with the data start and stop signals of the transmission data sequence. If the receiving (second device) side determines that the PLL is locked, it inverts the lock signal and sends it back to the transmitting side as a lock response signal.

On the transmission side, the transmitted lock signal and the returned lock response signal are received by, for example, a differential amplifier, and the output is generated as a lock detection signal. Determine the status of the transmitted signal. In the illustrated example, if the lock detection signal is “H” during the determination period, it is normal (determination: OK), and if “L”, it is N.
G (determination: NG) is determined. If this determination is "NG", the data is retransmitted to the receiving side.

As the retransmission sequence, depending on the system configuration on the receiving side, (1) when transmitting an image of one frame, the image is retransmitted from the beginning, (2) the first horizontal synchronization signal of the image in which an error has occurred There are methods such as retransmitting from a part, (3) retransmitting from a data part where an error has occurred, and (4) retransmitting only data where an error has occurred.

In the system of the present embodiment, when an error occurs, the frequency can be changed in a direction to lower the lock frequency of the PLL and improve the reliability of data transfer. This is similar to a conventional method of searching for a desired communication rate while lowering the communication frequency at a constant interval by RS232C serial communication or the like. However, in the method of the present embodiment, the PLL lock basic frequency (PLL lock signal) is changed. , The lock can be confirmed at the start and stop portions of the data, and the transmission data rate can be easily increased or decreased by increasing or decreasing the lock fundamental frequency. In this regard, in the conventional RS232C or the like, the reliability of data transfer is determined by judging the correctness of data transfer based on parity bits and the transfer rate is determined, which is advantageous in that the transfer rate can be set more finely.

Further, in a conventional error check in data (for example, parity check), even if a data error occurs, it is determined that an error occurs accidentally in two places of a parity bit and data. Data error may not be detected. However, if the PLL is locked as in the above-described embodiment, the PLL is unlocked in a situation where an error occurs in a plurality of bits, so that the error detection capability can be improved. Further, according to the present embodiment, a special circuit such as a parity checker is not required, and the system can be constructed with a simple circuit configuration.

If the data sequence from the start bit to the stop bit shown in FIG. 5 is a basic data sequence, and the number of bits of this basic data sequence is 2 ⁿ bits, for example, 16 bits, transmission from the PLL basic frequency is performed. The n-multiplier circuit for reconfiguring the clock is simple and the accuracy can be improved.

The preferred embodiments of the multi-camera data transfer system and the data transfer system of the present invention have been described above.
This is merely an example, and it goes without saying that various modifications can be made in accordance with the specific application.

[0065]

As described above, according to the camera data transfer method and the data transfer method of the present invention, serial communication can be performed with a simple configuration without the need for a USB interface that requires control by a host computer. It is possible not only to serially communicate data obtained by a plurality of terminals with minimum power consumption, but also to ensure data synchronization confirmation and data transmission confirmation.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a transmission method of image data obtained by imaging with a plurality of cameras in an embodiment of a data transfer method according to the present invention.

FIG. 2 is a timing chart of image transmission in the embodiment shown in FIG.

FIG. 3 is a diagram showing a configuration example of a high-speed serial interface converter 1 in an embodiment of a data transfer method according to the present invention.

FIG. 4 is a diagram showing another configuration example of the high-speed serial interface converter 1 in the embodiment of the data transfer method according to the present invention.

FIG. 5 is a diagram showing a configuration example of transmission / reception data in an embodiment of a data transfer method according to the present invention.

FIG. 6 is a timing chart for explaining an error detection method in data transmission / reception in the data transfer system according to the embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional data transfer method.

[Explanation of symbols]

Reference Signs List 1 high-speed serial interface converter 2A to NA serial interface (I / F) 2B to NB camera 10, 20 bus 11, 22 PLL circuit 12, 25 P / S converter 13, 24, 30 LVDS driver circuit (code circuit) 14 , 21, 31 LVDS receiving circuit (decoding circuit) 15, 23 serial / parallel conversion circuit 16, 28 transmitting amplifier 17, 26 receiving amplifier 18 differential amplifier

Claims (14)

[Claims] 1. A plurality of image pickup means each outputting an image signal picked up, and digital image data of a parallel output provided for each of the plurality of image pickup means and outputted simultaneously or sequentially from the image pickup means. Means for converting the serial data into a serial signal, output means for sequentially outputting the serial signal at a predetermined timing, and a serial interface for transmitting the output serial data signal to a communication destination and serially transferring the serial signal. A multi-camera data transfer method, wherein the other imaging means are in a standby mode while reading or transmitting image data from the means. 2. The multi-camera data transfer system according to claim 1, wherein said plurality of imaging means are imaging means for imaging in mutually different imaging wavelength regions or mutually different directions. 3. The multi-camera data transfer method according to claim 1, wherein said predetermined timing is determined by a vertical synchronization signal. 4. A data transfer method for transferring data between a first device and a second device, wherein the first device comprises an image pickup means for outputting an image signal in a parallel signal format. A P / S converter for performing parallel / serial conversion of an image signal, which is a parallel signal obtained by imaging, based on a clock output from the first PLL circuit;
LVDS (Low Voltage Differential Signaling) is converted into a signal in accordance with a signal transmission system, and the converted LVDS
An LVDS driver circuit for transferring a signal to a receiving side via a transmission line at high speed LVDS data; and converting an image signal received via the transmission line into parallel data based on a clock from the first PLL circuit. A serial / parallel conversion circuit, wherein the second device side receives the received image signal based on a clock from an LVDS receiving circuit that receives the image signal transferred via the transmission line and a second PLL circuit. A serial / parallel conversion circuit for converting an image signal into parallel data, a P / S converter for parallel / serial conversion of image data to be transmitted, and an LV
An LVDS driver circuit, which is converted into a signal in accordance with the DS signal transmission system and transfers high-speed LVDS data to the first device via the transmission line. 5. A data transfer method for transferring data between a first device and a second device, wherein the first device comprises an image pickup means for outputting an image signal in a parallel signal format. A P / S converter for performing parallel / serial conversion of an image signal, which is a parallel signal obtained by imaging, based on a clock output from the first PLL circuit;
LVDS (Low Voltage Differential Signaling) is converted into a signal in accordance with a signal transmission system, and the converted LVDS
An LVDS driver circuit that transfers high-speed LVDS data to a receiving side via a transmission line; a second device side receives an image signal transferred via the transmission line; A serial / parallel conversion circuit for converting the received image signal into parallel data based on a clock from the PLL circuit, and an LVDS for the serially converted signal. 6. A lock signal generated from a first PLL circuit in the first device is sent to the second device, and the received lock signal is not a correct synchronous clock on the second device. When it is determined that the received clock signal is inverted and sent to the first device as a lock response signal, and when it is determined that the received lock signal is a correct synchronous clock, the received clock signal is not inverted. To
The lock is transmitted as it is to the first device as a lock response signal. The first device determines whether or not the lock is accurate based on the received lock response signal and the lock signal, and determines whether the lock is correct. 6. The data transfer method according to claim 4, wherein when the data is not accurate, the previously transmitted data is retransmitted to the first device. 7. The device according to claim 1, wherein the first device outputs a lock detection signal indicating whether or not the lock is accurate by a differential amplifier that receives the lock response signal and the lock signal. The data transfer method according to claim 6, wherein 8. A PLL lock signal is transmitted from the first device side.
When the second device side determines that the second PLL circuit is locked based on the received PLL lock signal, the second device inverts the lock signal to generate a lock response signal. When the first device determines that the previously transmitted data is not correctly transmitted based on the transmitted lock signal and the returned lock response signal, A data transfer method for retransmitting previously transmitted data to the first device. 9. The data transfer method according to claim 8, wherein, when transmitting one frame of image, the retransmission is performed from the beginning of the image. 10. The data transfer method according to claim 8, wherein the retransmission is performed from the first horizontal synchronization signal portion of the image in which the error has occurred. 11. The data transfer method according to claim 8, wherein the retransmission is performed by retransmitting a data portion in which an error has occurred. 12. The data transfer method according to claim 8, wherein the retransmission is to retransmit only data in which an error has occurred. 13. When the error occurs, the PL
9. The data transfer method according to claim 8, wherein the lock frequency is changed in a direction in which the lock frequency of L is lowered to improve the reliability of data transfer. 14. A data transfer method according to claim 1, wherein said data has a unit data string of 2 ⁿ bits.