JP2001282381A - Clock phase adjustment circuit - Google Patents

Abstract

(57) [Problem] To provide a circuit in which an accurate duty ratio is maintained even when a large number of delay elements are connected in multiple stages and a signal is not lost. In a clock phase adjustment circuit in which delay elements are connected in multiple stages, wherein a delay is adjusted by switching the number of stages of a clock signal passing through the delay elements, a selector is used as a delay element. This selector has two inputs and one output and is of a logical inversion type. An inverse clock signal is applied to an odd-numbered stage selector, a positive clock signal is applied to an even-numbered stage selector, and a stage number control is applied to each selector. For the selector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal processing circuit, wherein a selector circuit is used as a delay circuit,
The present invention relates to a clock phase adjustment circuit configured to reduce a change in duty ratio caused by a clock signal passing through multiple stages.

[0002]

2. Description of the Related Art For example, when sampling an analog signal, it is necessary to adjust the phases of the original signal and the sampling clock in order to obtain a digital signal close to the original signal. In such a phase adjustment, a variable delay circuit is inserted into the sampling clock.

As shown in FIG. 6, a conventional delay circuit of this type includes first, second, third, fourth, and fifth delay elements 11, 12, 13 such as buffers provided at a clock input terminal 10. , 1
4 and 15 in series, and these first delay elements 11 to 11
One of the outputs of the fifth delay element 15 is selected by the selector circuit 16 in accordance with the select signal of the select signal input terminal 18 and output to the output terminal 17.

[0004]

In the above-described conventional circuit, signals are transmitted from the first delay element 11 to the fifth delay element 15.
In addition to the delay caused by the above, the delay is also caused by the selector circuit 16. Therefore, in order to make the number of delay elements and the delay amount proportional, it is necessary to reduce the delay difference between each input and output of the selector circuit 16. However, when a large number of delay elements are used, the number of input signals of the selector circuit 16 increases, and the circuit becomes complicated and the number of signal lines input to the selector circuit 16 increases. Therefore, in particular, a circuit such as a PLD (programmable logic device) is used. Is difficult to make the amount of delay generated in the selector circuit 16 uniform for all inputs.

The first to fifth delay elements 11 to 5
When the propagation delay time of T5 is different between t1 at the time of rising (L → H) and t2 at the time of falling (H → L), for example, as shown in FIG. The clock passing through one first delay element 11 has a delay of t1 at the rise and a delay of t2 at the fall, as shown in FIG. Similarly, the clocks that have passed through the two, three, and four first to fourth delay elements 11 to t1 × n at the time of successive rising as shown in (c), (d), and (e). And a delay of t2 × n occurs at the time of falling. However, when the signal passes through a plurality of delay elements, the ON / OFF duty ratio of the signal gradually deteriorates, and, as shown in FIG. The clock that has passed through the 5-delay element 15 has a problem that a rising operation occurs before the clock falls and the signal disappears.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit in which an accurate duty ratio is maintained even when a large number of delay elements are connected in multiple stages and a signal is not lost. is there.

[0007]

According to the present invention, there is provided a circuit in which delay elements are connected in multiple stages, wherein a clock signal is switched by the number of stages through which the clock signal passes through the delay elements to adjust a delay amount. , A selector is used as the delay element.
The output is of a logical inversion type. The reverse clock signal is applied to the odd-numbered selectors from the output stage, the positive clock signal is applied to the even-numbered selectors from the output stage, and the number of stages is added to each selector. A clock phase adjustment circuit characterized by adding a select signal for control.

With such a configuration, a desired delay signal can be obtained without requiring a large selector circuit on the output side as in the related art, and the delay amount due to the selector circuit does not vary. In addition, since the signal is inverted between adjacent delay elements by using the logic inversion type selector, even if the propagation delay time differs between the rising and falling edges, the adjacent delay elements cancel each other. Thus, the duty ratio of the clock signal is maintained.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a clock phase adjusting circuit according to the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In the present invention, a 2-input / 1-output logical inversion type selector is used as a delay element.
This eliminates the need for a conventional output-side selector circuit. More specifically, FIG.
, The second selector 22, the second selector 22, the third selector 23,..., The sixth selector 26 are arranged in multiple stages as a delay element from the output terminal 17 side to the clock input terminal 10 in order. It is connected to the.
A non-inverting buffer circuit 19 is connected to the clock input terminal 10.
And an inversion buffer circuit 20 are connected in parallel.

The output side of the inversion buffer circuit 20 is applied as one input of the first selector 21, the third selector 23 and the fifth selector 25 of the odd-numbered stages. The output side of the non-inverting buffer circuit 19 is applied as one input of the second selector 22, fourth selector 24, and sixth selector 26 of the even-numbered stages. Further, a first selector 21, a second selector 22,... A sixth selector 2
The other input side of 6 is sequentially connected with the second selector 22,..., The sixth selector 26 of the preceding stage and the non-inverting buffer circuit 19. These first selector 21 and second selector 2
The select signal input terminal 18 is also connected to the second, third,..., Sixth selectors 26.

In the clock phase adjusting circuit configured as described above, the clock signal input to the clock input terminal 10 is supplied to the non-inverting buffer circuit 19 and the inverting buffer circuit 2.
From 0, a positive clock and a negative clock are output as shown in FIGS. The clock that has passed through the first selector 21 as one delay element as shown in (c) will be described. At the time T1 of the rising edge of the positive clock and the falling edge of the negative clock, or just before that, the signal is selected from the select signal input terminal 18. It is assumed that an H signal is input to the first selector 21 as a signal. The first selector 21
The clock signal from the inversion buffer circuit 20 is selected. At this time, the select signal to the second selector 22 to the sixth selector 26 may be either H or L. T
At 1 o'clock, when the clock passing through the first selector 21 rises, the first selector 21 changes from L to H with a delay of t1 of the rising characteristic due to the fall of the clock from the inversion buffer circuit 20. At T2,
When the clock that has passed through the first selector 21 falls, the first selector 21 changes from H to L with a delay of t2 of the falling characteristic due to the rising of the clock from the inversion buffer circuit 20. Hereinafter, a clock signal obtained by repeating this is output from the output terminal 17.

The clock passed through the first selector 21 and the second selector 22 as the two delay elements as shown in FIG. 1D will be described. , H is input to the second selector 22. Second selector 22
Selects the clock signal from the non-inverting buffer circuit 19, and the first selector 21 selects the clock signal from the second selector 22. At this time, the third selector 2
The select signal to the third to sixth selectors 26 may be either H or L. At time T1, the second selector 2
2 and the rising edge of the clock that has passed through the first selector 21, the rising edge of the clock from the non-inverting buffer circuit 19 causes t2 when the second selector 22 goes from H to L and t1 when the first selector 21 goes from L to H. Becomes L → H with a delay of t3 in which At time T2, when the clock that has passed through the second selector 22 and the first selector 21 falls, the fall of the clock from the non-inverting buffer circuit 19 causes the second selector 22 to set t1 when L → H and the first selector. T which is obtained by adding t2 at the time of H → L by 21
H → L with a delay of 3. Hereinafter, a clock signal obtained by repeating this is output from the output terminal 17.

Similarly, the first selector 21, the second selector 22, and the three delay elements as shown in FIG.
In the clock that has passed through the third selector 23, t4 = t1
A clock signal is obtained with a delay of + t2 × 2,
First selector 2 as four delay elements as shown in FIG.
1, the clock that has passed through the second selector 22, the third selector 23, and the fourth selector 24 has t5 = t1 + t2 × 3
A clock signal is obtained with the following delay, and the clock passed through the first selector 21, the second selector 22, the third selector 23, the fourth selector 24, and the fifth selector 25 as five delay elements as shown in (g). , T6 = t1 + t2
A clock signal is obtained with a delay of × 4, and the first selector 21, the second selector 22, the third selector 23, the fourth selector 24, the fifth selector 25, and the sixth selector as six delay elements as shown in FIG. With the clock that has passed through the selector 26, a clock signal is obtained with a delay of t7 = t1 + t2 × 5. The same applies to seven or more delay elements.

As described above, a desired delay signal can be obtained without the need for a large selector circuit on the output side as in the prior art, and the delay amount due to the selector circuit does not vary. In addition, since the signal is inverted between adjacent delay elements by using the logic inversion type selector, even if the propagation delay time differs between the rising and falling edges, the adjacent delay elements cancel each other. Thus, the duty ratio of the clock signal is maintained.

In the embodiment shown in FIG. 1, all of the first selector 21 to the sixth selector 26 as delay elements are of two inputs and one output and are of logical inversion type, and the output side of the inversion buffer circuit 20 is an odd number. The output of the non-inverting buffer circuit 19 is supplied to one of the inputs of the first selector 21, the third selector 23, and the fifth selector 25 of the stage. , The sixth selector 26, but is not limited to this. In the embodiment shown in FIG. 3, the first selector 21 as a delay element is of a two-input, one-output type and a logically inverting type, and the second selector 22 to the sixth selector 26 are of a two-input, one-output type and a logically inverted type. , Forward rotation buffer circuit 19
Is applied as one input of the first selector 21, the third selector 23, and the fifth selector 25 of the odd-numbered stages, and the output side of the inversion buffer circuit 20 is connected to the second selector 22 of the even-numbered stages. , The fourth selector 24 and the sixth selector 26.

The first selector 21 to the sixth selector 26 in FIG. 1 and the second selector 22 to the sixth selector 26 in FIG. 3 are of a two-input, one-output type and a logical inversion type, but are not limited thereto. Instead, as shown in FIG.
An inverter 27 may be inserted at a stage subsequent to the first selector 21 to the sixth selector 26 of the two-input one-output and logically forward type.

In FIGS. 1 and 3, the clock input from the clock input terminal 10 is used as the normal and inverted clocks by the non-inverting buffer circuit 19 and the inverting buffer circuit 20, however, the present invention is not limited to this. As shown in FIG.
The first selector 21, the third selector 23, and the fifth selector 25 of the inverting input type and the second selector 22, the fourth selector 24, and the sixth selector 26 of the non-inverting input type are alternately arranged. You may make it input a clock directly.

[0018]

According to the present invention, there is provided a clock phase adjusting circuit in which a delay element is connected in multiple stages and the amount of delay is adjusted by switching the number of stages of a clock signal passing through the delay element. As an element, it is composed of a selector whose polarity on the input side and the output side is inverted.
The desired delay signal can be obtained without the need for a large selector circuit on the output side as in the related art, and the delay amount due to the selector circuit does not vary.

Also, by using a two-input, one-output, logic inversion type selector, the signal is inverted between adjacent delay elements, so that, for example, the propagation delay time differs between the rising edge and the falling edge. Are also canceled between adjacent delay elements, and the duty ratio of the clock signal is maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a clock phase adjusting circuit according to the present invention.

FIG. 2 is an operation waveform diagram of the clock phase adjustment circuit shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the clock phase adjusting circuit according to the present invention.

FIG. 4 is a block diagram showing a third embodiment of the clock phase adjusting circuit according to the present invention.

FIG. 5 is a block diagram showing a fourth embodiment of the clock phase adjusting circuit according to the present invention.

FIG. 6 is a block diagram of a conventional clock phase adjustment circuit.

7 is an operation waveform diagram of the clock phase adjustment circuit shown in FIG.

[Explanation of symbols]

10 clock input terminal, 11 first delay element, 12
Second delay element, 13: third delay element, 14: fourth delay element, 15: fifth delay element, 16: selector circuit, 17 ...
Output terminal, 18 ... Select signal input terminal, 19 ... Normal buffer circuit, 20 ... Inverting buffer circuit, 21 ... First selector, 22 ... Second selector, 23 ... Third selector, 24
... 4th selector, 25 ... 5th selector, 26 ... Sixth selector, 27 ... Inverter.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B079 BA20 BB04 BC03 CC02 CC13 DD05 DD06 DD20 5J001 AA11 BB00 BB12 DD09 5J106 CC59 DD09 DD26 HH02 KK17

Claims (5)

[Claims] 1. A clock phase adjusting circuit in which delay elements are connected in multiple stages, wherein a clock signal is switched according to the number of stages through which the clock signals pass through the delay elements to adjust a delay amount. A clock phase adjusting circuit comprising a selector whose polarity on the output side and the output side is inverted. 2. The selector has two inputs and one output and is of a logical inversion type, applies an inverted clock signal to an odd-numbered selector from the output stage, and supplies a positive clock to an even-numbered selector from the output stage. 2. The clock phase adjusting circuit according to claim 1, wherein a signal is added and a select signal for controlling the number of stages is added to each selector. 3. The selector has two inputs and one output and is of a logical forward type. An inverter is connected to the output side of these selectors, and an inverse clock signal is applied to the odd-numbered selectors from the output side. 2. The circuit according to claim 1, wherein a positive clock signal is applied to an even-numbered selector from the output stage side, and a select signal for controlling the number of stages is applied to each selector.
A clock phase adjustment circuit as described. 4. The selector of the first stage from the output stage is of a logical inversion type with two inputs and one output, and the second and subsequent stages of the selector is of a two-input and one output type with a logic inversion type. A positive clock signal is applied to the odd-numbered stage selector from the stage side, a reverse clock signal is applied to the even-numbered stage selector from the output stage side, and a select signal for controlling the number of stages is applied to each selector. The clock phase adjusting circuit according to claim 1, wherein 5. A selector having two inputs and one output and of a logical inversion type, and among these selectors, an odd-numbered selector from the output stage is an inverting input type and an even-numbered stage is selected from the output stage. The first selector is a non-inverting input type, in which a positive clock signal is added to all selectors, and
2. The clock phase adjusting circuit according to claim 1, wherein a select signal for controlling the number of stages is added.