JP2001281298A - Inspection probe board and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To provide an inspection probe board capable of inspecting a semiconductor device having external terminals with a narrow pitch. The inspection probe substrate has an insulating substrate, a plurality of lands formed on the substrate according to the positions of external terminals of a semiconductor device or an electronic device to be inspected, and a plurality of lands formed on each of the lands. A metal plating protrusion formed so as to be electrically connected and in contact with an external terminal of the semiconductor device or the electronic device; a lead lead connected to an inspection device on a substrate opposite to the land forming surface; And a conductive via for conducting the land and the lead-out lead.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe board for testing a semiconductor device or an electronic device by being electrically connected to an external terminal, and a method of manufacturing the same.
The present invention relates to an inspection probe substrate for inspecting the quality of a semiconductor integrated circuit chip / CSP package as a single unit and a technique effective when applied to a method for manufacturing the same.

[0002]

2. Description of the Related Art A printed circuit board having a plurality of unpackaged bare chips mounted thereon is mounted on an MCM (Multi Chip Modul).
e). With the development of electronic devices, the MCM has come to be positioned as an important technology for device development as an effective means for responding to essential needs such as light and thin.

[0003] Further, even in the case of packaging, a CSP (Chip Siz) miniaturized so as to minimize the amount of package base material and to have a package area (volume) substantially equal to a chip.
e / Scale Package) is being actively developed, and device manufacturers have announced small packages of various shapes. Many of the CSP packages have a BGA structure in which external terminals are arranged with solder balls on the back surface of the package.

[0004] However, the biggest barrier to these bare chips and CSPs is the quality-assured chip / package (KG).
D: Known Good Die) This is a non-destructive inspection method for selection. For this purpose, an inspection is provided in which a projection is provided to ensure electrical continuity by contacting with an electrode pad of a chip or a solder ball for an external terminal of a package. The key point is the development of a probe board for use.

Conventionally, a probe substrate provided with tungsten microneedles in accordance with the position of the aluminum pad of the chip has been used.

However, the number of pads and the number of terminals are increasing with the miniaturization of chips and the increase in the number of pins, and the pitch of pads and terminals is becoming increasingly narrower. There is a great restriction on the manufacture of the.

[0007] For this reason, at present, a socket incorporating a probe for KGD discrimination, which is a combination of a tape carrier and a micro bump manufacturing technique, has been developed.

In these structures, a projection is provided on a substrate provided with fine wiring at a position corresponding to a solder ball of an electrode pad of a chip or an external terminal of a package, and a chip is sandwiched between the probe substrate and an upper die. It has become.

[0009]

The pitch of the solder balls to be reflow-connected to the back surface as external terminals of the package is currently narrowed to 0.5 mm. Therefore, in the above-described prior art, there is a problem that it is difficult to form a fine contact projection corresponding to the narrow pitch.

Further, when lands forming projections at a pitch of 0.5 mm are arranged on the probe substrate, there is a problem that it is difficult to form lead leads. In particular, in the case of a full grid arrangement in which the external terminals are all arranged on the back surface of the package at a narrow pitch, the above-mentioned probe substrate cannot cope with the problem.

An object of the present invention is to solve the above problems, and an object of the present invention is to provide an inspection probe board capable of inspecting a semiconductor device having external terminals with a narrow pitch. .

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present invention, typical ones will be briefly described as follows.

(1) An inspection probe substrate includes an insulating substrate, a plurality of lands formed on the substrate corresponding to the positions of external terminals of a semiconductor device or an electronic device to be inspected, and the lands. A metal plating protrusion formed in such a manner as to be electrically connected to an external terminal of a semiconductor device or an electronic device, and a lead lead connected to an inspection device on a substrate opposite to the land forming surface, It is provided in the substrate, and includes a conductive via that connects the land and the lead-out lead.

(2) In the inspection probe board according to (1), the metal plating projection is composed of a plurality of small plating projections.

(3) In the inspection probe substrate according to (1) or (2), the metal plating protrusion forms an antioxidant metal film at least at a portion in contact with the external terminal.

(4) In the inspection probe substrate of (1) or (2), the lands and the metal plating protrusions formed thereon are collectively covered with an antioxidant metal film.

(5) In the inspection probe substrate of (3) or (4), the antioxidant metal film is a noble metal plating.

(6) In the inspection probe substrate according to any one of (1) to (5), the metal plating projection is a metal plating projection formed by an electroless plating method.

(7) A plurality of lands are formed on a substrate in accordance with the positions of external terminals of a semiconductor device or an electronic device to be inspected, and a metal plating projection is formed on each of the lands to contact the external terminals. A method of manufacturing a probe substrate, comprising preparing a 2-metal tape carrier in which conductive thin films are provided on both surfaces of an insulating substrate,
One of the conductive thin films is opened at a predetermined position, and a via hole reaching the conductive thin film on the other surface is formed in the substrate at the opening position, and a predetermined via hole is formed on the opened conductive thin film and in the via hole. Copper plating of a thickness, etching of the conductive thin film on the unopened surface to form a lead lead, etching of the conductive thin film coated with copper to form a land, and forming a land on the land forming surface. A resist film is formed on the land, an opening of the resist film is formed on a land corresponding to an external terminal of the semiconductor device or the electronic device, and the tape carrier having the opening of the resist film is immersed in a metal plating solution. Performing electroless plating, electroplating, or a combination thereof, forming a metal plating layer to a thickness that fills the opening, removing the resist film, and forming a metal plating on the wiring pattern. To form a cause.

(8) In the method of manufacturing an inspection probe substrate according to (7), after the metal plating protrusion is formed,
A noble metal plating of a predetermined thickness is formed on the land, the lead, the conductive via, and the metal plating protrusion.

(9) A plurality of lands are formed on a substrate in accordance with the positions of external terminals of a semiconductor device or an electronic device to be inspected, and a metal plating projection is formed on each of the lands to contact the external terminals. A method of manufacturing a probe substrate, comprising preparing a 2-metal tape carrier in which conductive thin films are provided on both surfaces of an insulating substrate,
One of the conductive thin films is opened at a predetermined position, a via hole is formed in the substrate at the opening position to reach the conductive thin film on the other surface, and a via hole is formed on the opened conductive thin film and in the via hole. Metal plating is applied to a thickness that embeds the metal plating, the metal plating and the conductive thin film other than the land formation location are removed, a resist film is formed at the metal plating projection formation location, and metal plating is performed by half-etching the metal plating with this resist film. The protrusions are formed, the resist film is removed, the conductive thin film on the surface opposite to the land formation surface is etched to form lead leads, and metal plating protrusions are formed on the lands.

(10) In the method of manufacturing an inspection probe substrate according to (9), after the metal plating projection is formed, the land, the lead-out lead, the conductive via,
And forming a noble metal plating of a predetermined thickness on the metal plating protrusion.

As described above, by using the metal plating protrusion, it is possible to provide an inexpensive probe board for inspection capable of inspecting a miniaturized and multi-pin semiconductor device.

Further, by forming a lead lead connected to the inspection device on the back surface of the substrate via a conductive via and not forming the plating protrusion and the lead lead on the same surface of the insulating tape (polyimide tape), Even if plating protrusions are formed at a narrow pitch, it is not difficult to form lead lines of the lead leads. Therefore, it is possible to provide an inspection probe substrate that can inspect a semiconductor device having external terminals with a narrow pitch. Will be possible.

Further, since the hardness of the metal plating projection is increased by forming the metal plating projection by electroless metal plating, it is possible to provide an inspection probe board having excellent durability.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An inspection probe board according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view for explaining the configuration of the inspection probe substrate of the present embodiment. FIG. 2 is a sectional view taken along line AA shown in FIG. 1 and 2
Are shown for easy explanation of the configuration of the main part.

As shown in FIGS. 1 and 2, an inspection probe 100 of the present embodiment comprises an insulating tape 10 made of polyimide or the like.
A land 11 provided on the insulating tape 10 in accordance with the position of the external terminal of the semiconductor device to be inspected and formed of a conductive thin film such as a copper foil; and a land 11 formed on the surface of the insulating tape 10 opposite to the land 11 forming surface. Lead 111 connected to the inspection device (not shown), a conductive via 112 electrically connecting the land 11 and the lead 111, and provided on the land 11 in accordance with the connection position with the external terminal. And the plated projections 12 provided.

The insulating tape 10 is made of a flexible material which has an insulating property of a semiconductor device to be inspected and is easily deformed to absorb irregularities (for example, errors in the height of ball terminals) of external terminals of the semiconductor device. . For example, polyimide, liquid crystal polymer, and the like.

The land 11 and the lead 111 are
It is formed by etching a thin film metal which is easy to process with a conductive material. The land 11 is electrically connected to an inspection device (not shown here) via the conductive via 112 and the lead 111.

The conductive via 112 is a via conductive plating for electrically connecting the land 11 and the lead lead through the via hole. Here, it is formed by electroless or metal plating formed by electroplating. As this metal plating, for example, copper is used.

As shown in FIG. 2, the present embodiment shows the conductive via 112 covering only the surface of the via hole. However, the present invention is not limited to this, and the entire via hole is filled. Metal plating may be used.

The plating protrusions 12 are formed by electroplating or electroless plating a material (metal) having high conductivity. In addition, since the semiconductor device is in pressure contact with an external terminal of the semiconductor device, the semiconductor device is preferably formed to be hard to enhance durability. For this reason, it is particularly preferable to form by metal plating by an electroless plating method. This is because the electroless metal plating is laminated harder than the electric metal plating. here,
Taking nickel as an example, the Pickers hardness of the protrusions formed by electroless nickel plating is Hv450 to 600, and the Pickers hardness of the protrusions formed by electronickel plating is about Hv180. The difference in hardness between the projections formed by the method and the method is apparent.

Among the electroless metal platings, the electroless nickel plating is particularly suitable for the plating projection 12 because it has high conductivity and is hard. Alternatively, electroless copper plating may be used.

As shown in FIG. 3, metal plating (for example, gold plating) 13 for preventing oxidation of a contact portion with an external terminal is applied on the plating protrusion 12 formed by the electroless metal plating. Sometimes.

The gold plating 13 is formed so as to cover the lands 11 and the plating protrusions 12 in a collective manner in order to further increase the bonding strength. Further, since the gold plating 13 does not need to be applied to the entire land 11, the gold plating 13 may be formed only on the plating protrusion 12 and the land 11 around the plating protrusion 12.

As a result, the joints are supported so that the plating protrusions 12 are supported by the entire surface of the land 11, so that the bonding strength is increased, the plating protrusions 12 can be prevented from falling off due to repeated use, and the inspection probe board is more durable. Can be provided.

The plating layer that covers the lands 11 and the plating projections 12 is not limited to the gold plating 13, but is preferably a noble metal plating such as rhodium, palladium, platinum, and silver which is hardly oxidized. In addition, since these noble metal platings reduce the contact resistance of the plating protrusions 12,
Quality inspection can be performed more accurately.

In this embodiment, the plating protrusion 12 is formed from one protrusion. However, if the plating protrusion 12 can be formed on the land 11, the plating protrusion 12 may be formed by a plurality of small protrusions. You may. At this time, the finer the pitch, the more contact points with the external terminal, and the more the oxide film of the external terminal can be wiped at the edge of the small projection when in contact with the external terminal, lowering the contact resistance Can be performed, so that more accurate inspection can be performed.

Next, the inspection probe substrate 1 of the present embodiment
00 will be described with reference to the drawings. FIG.
FIG. 5 is a diagram for explaining a method of manufacturing the inspection probe substrate 100 according to the present embodiment.

Inspection probe substrate 100 of the present embodiment
First, as shown in FIG. 4A, the copper foil 21 (18 μm)
m) / Polyimide tape 10 (25 μm) / copper foil 21
A tape carrier material (2 metal tape material) with a two-layer copper foil made of (18 μm) is prepared.

Next, as shown in FIG. 4B, the copper foil 21 where the conductive via 112 is to be formed is opened by a photo-etching step, and a via hole (blind via) is formed in the polyimide tape 10 with a carbon dioxide gas laser or the like. 22 is opened.

Next, as shown in FIG. 4 (c), after the wall surface of the via hole 22 of the polyimide tape 10 is subjected to a conduction treatment, the back surface is shielded and the conduction is formed on the copper foil 21 and in the via hole 22. Form copper oxide plating. The plating method at this time may be an electroless plating method, an electroplating method, or a combination thereof.

Next, as shown in FIG. 4 (d), the plating surface is shielded to cover the copper foil 21 on the back surface of the tape carrier material.
, A positive photoresist 23 (for example, PMER: Tokyo Ohkasha Co., Ltd.) is applied, and a series of photofabrications such as exposure, development, etching, and resist film peeling are performed on the photoresist-coated surface to form a lead 111. .

Next, as shown in FIG. 5E, similarly to the formation of the lead-out lead 111, the surface on which the lead-out lead 111 is formed is shielded to form the land 11 on the plating formation surface.

Next, a dry film resist 26 for thickening is applied on the surface on which the lands 11 are formed to form a resist film. The resist film is exposed and developed as shown in FIG. A resist opening 24 is formed on the land 11 at a position corresponding to an aluminum pad or a ball terminal (not shown) of the apparatus. When there are a plurality of plating protrusions 12, a plurality of openings 24 are formed.

Next, the substrate (polyimide tape 10, land 11, via hole 2) on which the resist opening 24 is formed is formed.
2 and a tape carrier material including the lead-out lead 111) are immersed in a nickel plating solution to perform electroless plating, and as shown in FIG. 5 (g), to a thickness (about 20 μm) that almost completely fills the resist opening 24. A nickel plating layer (plating protrusion) 12 is formed in the resist opening.

Next, as shown in FIG. 5 (h), the substrate on which the plating protrusions 12 are formed is immersed in a gold plating solution to perform electrolytic plating, and the surface of the electroless nickel plating protrusions 12 is formed. Gold plating 13 (thickness: about 0.5 μm) is formed on the lands 11, the resist 26 is dissolved and removed using a dedicated stripping solution, and the nickel plating protrusions 12 on which the gold plating 13 is applied are formed on the lands 11. In this way, the prepared substrate is cut into a desired size, and as shown in FIG. 6, a test terminal is mounted on the probe socket 30 so that the ball terminals 32 of the semiconductor device 31 to be tested come into contact with the nickel plating protrusions 12. The probe substrate 100 is formed.

When the plating protrusion 12 is formed by a plurality of protrusions, as shown in an enlarged view of the connection portion in FIG.
Plating protrusion 1 is applied to ball terminal 32 of semiconductor device 31.
2 are pressed and contacted at a plurality of locations to be electrically connected, so that a large contact area can be obtained, and the edge portion of the plating protrusion 12 wipes the oxide film of the ball terminal 32, so that the contact resistance can be reduced. , More accurate inspection can be performed.

The formation of the plating protrusions 12 is not limited to the above-described combination of gold plating / nickel plating, but may be a composite plating film containing a hard powder such as palladium, rhodium, a nickel alloy, diamond, or silica. Various combinations can be used.

As described above, the insulating tape, the predetermined wiring pattern formed on the substrate and the wiring pattern are formed so as to be electrically connected to each other. Providing the plating protrusions 12 formed by the electroless plating method in contact with the terminals makes it possible to provide an inexpensive inspection probe substrate that can inspect a miniaturized and multi-pin semiconductor device.

Further, a lead 111 connected to the inspection device is formed on the back surface of the substrate via the conductive via 112,
Since the plating protrusions 12 and the lead-out leads 111 are not formed on the same surface of the insulating tape (polyimide tape), it is difficult to form lead-out lines of the lead-out leads 111 even if the plating protrusions 12 are formed at a narrow pitch. Therefore, it is possible to provide an inspection probe board capable of inspecting a semiconductor device having external terminals with a narrow pitch.

Further, by forming the plating protrusions 12 by electroless metal plating, the hardness of the plating protrusions 12 is increased, so that it is possible to provide an inspection probe substrate having excellent durability.

In the present embodiment, the case where the semiconductor device 31 is inspected has been described. However, the present invention is not limited to this, and can be applied to, for example, the inspection of an electronic device.

(Embodiment 1): Conductive vias buried in via holes FIG. 8 is a cross-sectional view for explaining the configuration of the inspection probe substrate of the present embodiment 1. Note that the overall view of the inspection probe board of the first embodiment is omitted because it is almost the same as the plan view shown in FIG.

As shown in FIG. 8, an inspection probe 100a according to the first embodiment includes an insulating tape 10 made of polyimide or the like.
A land 11 provided on the insulating tape 10 in accordance with the position of the external terminal of the semiconductor device to be inspected and formed of a conductive thin film such as a copper foil, and a land 11 formed on the surface of the insulating tape 10 opposite to the surface on which the land 11 is formed. Leader 111 connected to a device (not shown), land 11 and leader 1
The conductive vias 112a electrically connect the conductive vias 11 to each other, and the plating protrusions 12 provided on the lands 11 in accordance with the connection positions with the external terminals.

The conductive vias 112a fill the via holes with metal (here, copper) plating, and electrically connect the lands 11 and the lead leads through the via holes. Similar to the above-described embodiment, the metal plating is formed by electroless or electroplating. This metal plating is not limited to copper, but may be any material having conductivity, for example, nickel or the like. In particular,
When the electroless nickel plating is used, the durability of the protrusion is improved for the same reason as in the embodiment.

In order to prevent oxidation and reduce contact resistance, lands 11, plating protrusions 12, lead leads 11
1 and the conductive via 112 a may be covered with gold plating 13.

Next, the inspection probe substrate 1 of the first embodiment
00a will be described with reference to the drawings. FIG.
FIG. 11 to FIG. 11 show the inspection probe substrate 100a of the first embodiment.
FIG. 7 is a diagram for explaining the manufacturing method of the first embodiment.

Inspection probe substrate 100a of the first embodiment
Is, as shown in FIG. 9A, a copper foil 21 (18 μm) /
Polyimide tape 10 (25 μm) / copper foil 21 (18 μm)
m), a tape carrier material with a two-layer copper foil (so-called 2-metal tape material) is prepared.

Next, as shown in FIG. 9B, the copper foil 21 where the conductive via 112 is to be formed is opened by a photo-etching process, and a via hole (blind via) is formed in the polyimide tape 10 using a carbon dioxide gas laser or the like. 22 is opened.

Next, the via hole 22 of the polyimide tape 10
After conducting the conductive treatment on the wall surface of the above, the back surface is shielded, and copper plating 25 is applied with a copper plating solution for via filling (for example, using a product of Meltex). As a result, FIG. 9 (c)
As shown in (2), the inside of the via hole 22 is embedded with copper plating 25 (formation of the conductive via 112a) to electrically connect the upper and lower copper foils, and the copper foil 21 on the opening side of the via hole 22 is Copper plating 25 is plated by about 20 μm.

Next, as shown in FIG. 9D, a photoresist 23 is applied to the entire surface of the copper foil 21 on the copper-plated surface and the entire surface of the back-surface copper foil 21, and then exposed and developed to form a film on the copper-plated surface. The photoresist 23 is left in a desired shape.

Then, as shown in FIG. 10 (e), an aqueous solution of ferric chloride is sprayed to form the copper-plated surface by etching, and as shown in FIG. 10 (f), the photoresist 23 is removed and the land is removed. Copper plating 25 is formed on 11.

Next, a photoresist 23 is applied again to a predetermined position on the copper plating (the position where the plating protrusion 12 is formed).
After exposure and development steps, a photoresist 23 having the shape shown in FIG. 10G is formed.

Next, an aqueous solution of ferric chloride is sprayed again, and the pattern is half-etched while leaving the copper plating 25 under the photoresist 23 coating portion, as shown in FIG. As shown in (i), the resist is stripped to form copper plating protrusions 12.

Next, as shown in FIG. 11 (j), a photoresist 23 is applied to the lands 11 and the plating protrusions 12 and the copper foil 25 on the back surface, and is exposed, developed and etched. As shown in FIG. 7, a lead 111 on the back surface is formed.

Next, the photoresist 23 is removed, and a probe substrate is formed as shown in FIG.

Further, in order to prevent oxidation of the lands 11 and the plating protrusions 12 and to reduce the resistance at the time of contact, nickel may be electroplated by about 1 μm, and then gold may be electroplated by about 0.5 μm.

Incidentally, the plating protrusion 12 may be formed by a plurality of protrusions. In this case, the size of each projection is preferably about 100 μm or less.

The shape of the projection is not limited to a column, but may be a triangle, a square, or a polygon. Also, various patterns can be considered for the arrangement shape of the plurality of devices, but it is necessary to arrange the plurality of devices at a pitch at least smaller than the diameter of the external terminals of the device.

Thus, it is possible to prevent the contact position of the external terminal from being shifted due to the misalignment of the semiconductor device, thereby reducing the contact force with the external terminal of the semiconductor device and preventing the oxide film from being destroyed.

As the resist 23, a dry film resist may be used instead of the above-described photoresist.

As described above, the lead 111 to be connected to the inspection device is formed on the back surface of the substrate via the conductive via 112a, and the plating protrusion 12 and the lead 111 are not formed on the same surface of the insulating tape (polyimide tape). By adopting the structure, even if the plating protrusions 12 are formed at a narrow pitch, it is not difficult to form the lead lines of the lead leads 111. Therefore, an inspection that can inspect a semiconductor device having an external terminal with a narrow pitch can be performed. It is possible to provide a probe substrate for use.

Further, the inspection probe substrate 1 of the first embodiment
In the case of 00a, the conductive via 112a and the plating protrusion 12 are formed simultaneously in one plating step without being formed in separate steps, so that an inexpensive inspection probe substrate can be provided.

Furthermore, since the plating step requires a particularly long processing time, the number of plating steps can be reduced, and the manufacturing time can be reduced.

As described above, the invention made by the present inventor
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0078]

The effects obtained by the representative inventions among the inventions disclosed in the present invention will be briefly described.
It is as follows.

By forming a structure in which the plating protrusion and the lead are not formed on the same surface of the insulating tape (polyimide tape), even if the plating protrusion is formed at a narrow pitch, it is difficult to form the lead of the lead. Therefore, it is possible to provide an inspection probe board that can inspect a semiconductor device having external terminals with a narrow pitch.

Further, by forming the plating protrusions by electroless metal plating, the hardness of the plating protrusions is increased, so that it is possible to provide an inspection probe substrate having excellent durability.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a configuration of an inspection probe substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA shown in FIG.

FIG. 3 is a plan view for explaining the configuration of a gold-plated inspection probe substrate.

FIG. 4 is a diagram for explaining a method of manufacturing the inspection probe substrate 100 according to the embodiment.

FIG. 5 is a diagram illustrating a method for manufacturing the inspection probe substrate 100 according to the embodiment.

FIG. 6 is a view for explaining a configuration of a probe socket using the inspection probe board.

FIG. 7 is an enlarged view for explaining a connection portion between a plating protrusion and an external terminal.

FIG. 8 is a cross-sectional view for explaining the configuration of the inspection probe substrate of the first embodiment.

FIG. 9 is a diagram for explaining the method for manufacturing the inspection probe substrate according to the first embodiment.

FIG. 10 is a diagram for explaining the method of manufacturing the inspection probe substrate according to the first embodiment.

FIG. 11 is a diagram for explaining the method for manufacturing the inspection probe substrate according to the first embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Insulation tape 11 Land 12 Plating projection 13 Gold plating 21 Copper foil 22 Via hole 23 Resist film 24 Opening 30 Probe socket 31 Semiconductor device 32 Ball terminal 100, 100a Inspection probe board 111 Lead wire 112, 112a Conducting via

Claims (10)

[Claims] 1. An electrically insulating substrate, a plurality of lands formed on the substrate according to the positions of external terminals of a semiconductor device or an electronic device to be inspected, and electrically connected to each of the lands. Metal plating protrusions that are formed so as to be in contact with external terminals of a semiconductor device or an electronic device, and lead leads that are connected to an inspection device on a substrate on a surface opposite to the land forming surface, and are provided in the substrate, An inspection probe substrate, comprising: a conductive via that connects the land and the lead. 2. The inspection probe board according to claim 1, wherein the metal plating projection comprises a plurality of small plating projections. 3. The inspection probe board according to claim 1, wherein the metal plating projection has an antioxidant metal film formed at least in a contact portion with the external terminal. Probe board. 4. The inspection probe substrate according to claim 1, wherein the lands and the metal plating projections formed thereon are collectively covered with an antioxidant metal film. Probe board. 5. The inspection probe board according to claim 3, wherein the oxidation preventing metal film is a noble metal plating. 6. The inspection probe board according to claim 1, wherein the metal plating projection is a metal plating projection formed by an electroless plating method. Inspection probe substrate. 7. An inspection probe in which a plurality of lands are formed on a substrate in accordance with the positions of external terminals of a semiconductor device or an electronic device to be inspected, and a metal plating protrusion is formed on each of the lands to contact the external terminals. A method for manufacturing a substrate, comprising preparing a 2-metal tape carrier in which conductive thin films are provided on both surfaces of an insulating substrate, and opening the conductive thin film on any one surface at a predetermined position; A via hole reaching the conductive thin film on the other surface is formed in the substrate, a predetermined thickness of copper plating is applied on the opened conductive thin film and in the via hole, and the conductive thin film on the unopened surface is removed. Forming a lead by etching, forming a land by etching the copper-plated conductive thin film, forming a resist film on the land forming surface, and forming a semiconductor device or an electronic device. An opening of a resist film is formed on a land at a position corresponding to the external terminal of the above, and the tape carrier having the opening of the resist film formed thereon is immersed in a metal plating solution to perform electroless plating, electroplating, or A method for manufacturing a probe board for inspection, comprising: combining, forming a metal plating layer so as to fill the opening, removing the resist film, and forming a metal plating protrusion on the wiring pattern. 8. The method of manufacturing a probe board for inspection according to claim 7, wherein after the metal plating protrusion is formed, a predetermined number is applied to the land, the lead-out lead, the conductive via, and the metal plating protrusion. A method of manufacturing a probe board for inspection, wherein a noble metal plating having a thickness is formed. 9. An inspection probe in which a plurality of lands are formed on a substrate in accordance with the positions of external terminals of a semiconductor device or an electronic device to be inspected, and a metal plating projection is formed on each of the lands to contact the external terminals. A method for manufacturing a substrate, comprising preparing a 2-metal tape carrier in which conductive thin films are provided on both surfaces of an insulating substrate, and opening the conductive thin film on any one surface at a predetermined position; A via hole reaching the conductive thin film on the other surface is formed in the substrate, a metal plating having a thickness to bury the via hole in the opened conductive thin film and in the via hole is applied, and a metal plating other than a land forming portion and The conductive thin film is removed, a resist film is formed at the position where the metal plating protrusion is to be formed, and the metal film is half-etched with the resist film to form the metal plating protrusion. A method for manufacturing an inspection probe substrate, comprising: removing a strike film, etching a conductive thin film on a surface opposite to a land formation surface, forming a lead, and forming a metal plating protrusion on the land. 10. The method of manufacturing a probe board for inspection according to claim 9, wherein after the metal plating projection is formed, a predetermined number is applied to the land, the lead-out lead, the conductive via, and the metal plating projection. A method of manufacturing a probe board for inspection, wherein a noble metal plating having a thickness is formed.