JP2001275085A - Recording device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reliably record a scene desired by a user. A recording device includes a first type of memory and a first type of memory.
And a second type of memory having a larger capacity than the type of memory can be used. When the second type of memory is used, the address of the second type of memory is circulated in the recording pause mode. A configuration is adopted in which an image signal coded by designating the image is written.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a recording apparatus, and more particularly, to an apparatus for encoding and recording an image signal using a memory.

[0002]

2. Description of the Related Art A video camera-integrated VTR is conventionally known as this type of apparatus.

[0003]

In such a video camera-integrated VTR, there are limitations on the operation of mechanisms including a tape cassette, a magnetic head, etc., human delay in operation, and limitations on the memory capacity. In addition, there is a problem that a delay occurs between the time when the recording start switch is operated and the time when the actually photographed image signal is recorded on the tape, and the scene intended by the user cannot be recorded.

[0004] It is an object of the present invention to solve the above-mentioned problems.

Another object of the present invention is to ensure that a scene desired by a user can be recorded.

[0006]

In order to solve the above-mentioned problems and achieve the above object, a recording apparatus of the present invention has a first storage capacity, a first address space, and a second address space. A first type of memory in which an address space is set, and a second storage capacity larger than the first storage capacity, wherein the first, second and third address spaces are set; Input means for inputting an image signal and writing the image signal into a first address space in the first type memory or the second type memory; and Encoding means for encoding the image signal written in the first address space and writing the image signal in the second address space in the first type memory or the second type memory; and Recording image signals Recording means, a recording mode in which the recording means records the image signal and the additional signal, and a recording pause mode in which the recording means stops recording the image signal and the additional signal. Mode setting means for setting, and when the second type of memory is used, the encoded image signal by cyclically specifying addresses in the second and third address spaces in the recording pause mode And the control means for controlling the memory of the second type so as to write the data.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, the present invention is applied to an HD digital VCR
A case in which the present invention is applied to a digital VTR compatible with the DV format, which is a standard of a consumer digital VTR determined by the council, will be described.

FIG. 1 is a block diagram showing the configuration of a video camera-integrated VTR 100 according to this embodiment.

In FIG. 1, reference numeral 101 denotes a camera unit;
A captured image signal including a known optical system and a CCD is output to the signal processing circuit 17. An EVF 103 displays an image related to an image signal captured by the camera unit 101, an image signal from the line input / output circuit 105, and a reproduced image signal. 105 is a line input / output circuit, and VT
The image signal is input / output to / from an external device of the R100.
Reference numeral 107 denotes a signal processing circuit which mainly performs encoding / decoding of image and audio signals. A memory unit 109 uses an SDRAM (Synchronous-DRAM) in this embodiment. 111
Reference numeral denotes an operation switch, which has a large number of operation keys such as a recording / reproduction switch and a mode switching switch, and outputs a control signal to the signal processing circuit 107 in accordance with a user operation. A recording circuit 113 includes a magnetic head, a tape transport mechanism, and the like, and records and reproduces signals on and from the tape T.

Next, the operation of the signal processing circuit 107 and the memory section 109 in FIG. 1 will be described.

FIG. 2 shows a configuration of a main part of the signal processing circuit 107.

As shown in FIG. 2, the signal processing circuit 107 accesses the memory unit 109 at desired timing while various processing blocks are controlled by the CPU, and arbitrates those access requests by the memory control unit. Is configured to guarantee the operation of each processing block.

Each processing block in FIG.
It is possible to perform real-time processing of format-compatible image signals and audio signals. In the present embodiment, such processing units are arranged in parallel, and each processing circuit is supplied with an image signal and an audio signal in a time-division manner to process the signals.
The amount of data per frame is 2 of the SD format.
It is possible to process image data and audio data corresponding to the HD format, which is twice as large, in real time.

The signal processing circuit shown in FIG. 2 corresponds to the camera unit 1 shown in FIG.
01, an image signal output to the EVF 103, a data I / O block 201 for processing input / output data to and from the line input / output circuit 105, and processing such as YC separation for input data. A data input / output block (hereinafter referred to as VB) 203 for performing processing such as multiplexing and interpolation on output data, an audio processing block 205 for performing audio signal encoding / decoding processing, a well-known DCT for image signals, and a variable length. An encoding / decoding (hereinafter, COMP) block 207 that performs encoding / decoding processing using encoding, and an error using parity data for each of image, audio, and subcode data stored in the memory unit 109. An error correction block (hereinafter referred to as EC) for performing correction encoding / decoding processing
C) 209, an encoded data input / output block (hereinafter referred to as RP) 21 which converts each encoded data into a specified tape format at the time of recording and performs an output format process at the time of reproduction.
1. An electromagnetic conversion processing block 213 for performing an electromagnetic conversion process at the time of recording / reproduction is generally constituted, and each of these blocks exchanges data with the memory unit 109 via an address conversion circuit 215 and a memory interface 217.

The CPU 219 generates system data, which is an additional signal related to image data to be recorded, according to a control signal from an operation switch or the like, and writes the generated system data to the memory 109.

The operation of each of these processing blocks includes a predetermined command supplied from the system control CPU 219 via the CPU bus 223, and a servo CPU 233.
From the CPU bus 231 and the interface 221, C
A predetermined command supplied via the PU bus 223 controls the time division processing.

The memory section 109 in this embodiment is an SDRAM capable of performing burst transfer of data in synchronization with the rise of the clock. The memory section 109 uses a multiplying circuit 227 to convert a 27.5 MHz clock generated from the oscillator 225 without jitter. A 67.5 MHz clock obtained by the multiplication is supplied as a reference clock 227a. Here, the frequency of the reference clock 227a is
13.5 MHz synchronized with Hsync generated at 29
Is set to 5 times.

In FIG. 2, VB 203, audio processing block 205, COMP 207, ECC 20
9, RP 211, address conversion circuit 215, memory I / O
F217, system control CPU 219, I / F
The respective circuit blocks of the 221, the CPU bus 223, the multiplying circuit 227 and the oscillator 229 are configured on one IC chip 200.

Next, a conceptual diagram of the memory space of the memory section 109 is shown in FIG.

As shown in FIG. 2, the memory space of the memory unit 109 includes a video memory (hereinafter, VM) area for storing uncoded signals, and a track memory (hereinafter, TM) area for storing coded signals. Having. The memory cells in each area can be set to a write mode or a read mode for each frame, and each processing block can transfer data between the VM area and the TM area via the sense amplifier 109a according to the processing mode. To give and receive.

That is, as shown in FIG. 3, the VB block 203 exclusively exchanges data with the VM area 109b. Further, the COMP block 207 stores the VM area 109.
b, by exchanging data between the TM area 109c, the data is read from the VM area 109b at the time of encoding, the encoding process is performed, the encoded data is written to the TM area 109c, and the The encoded data is read out and decoded, and the decoded data is written to the VM area 109b.

Similarly, the audio processing block 205,
ECC block 209 and RP block 211 are exclusively T
Data is exchanged with the M area.

As shown in the figure, uncoded image data (Y, Cr, Cb) is written into the VM area 109b on a pixel basis. This image data (SD in the NTSC system)
In the case of the format, horizontal 720 pixels × vertical 480 pixels per frame) is composed of 50 super macroblocks (hereinafter referred to as SMB) of 5 horizontal × 10 vertical.
Each SMB is composed of 27 blocks of macroblocks (hereinafter referred to as MB) composed of 4 DCT blocks of luminance data and 2 blocks (1 block each of Cr and Cb) of chrominance DCT data. Each DCT block is composed of 8 vertical pixels × 8 horizontal pixels.

One frame of image data is NTSC
In the case of the system, the data is recorded on 10 tracks (12 tracks in the case of the PAL system) of the magnetic tape after the encoding process, and at this time, 5 SMB data aligned in the horizontal direction is recorded in each track. You.

Therefore, when accessing the VM area 109c, addresses corresponding to h and v of each pixel in the horizontal and vertical directions, the track number Tr, the SMB number in each track, the MB number in each SMB, It is convenient to use the DCT block number in each macroblock.

On the other hand, in the TM area 109c, coded additional data such as image data, audio data, and subcode data are stored in correspondence with the ten tracks, and in the area corresponding to each track, Formatted one
Data of 49 sync blocks are stored.

The audio data is also stored in an area independent of the image data storage area in correspondence with 10 tracks, and in the area corresponding to each track, data of 14 sync blocks is stored.

Each image and audio data is divided into a plurality of blocks by a predetermined amount.
A sync block is formed by adding ID data, and parity data is further added by the ECC 209 for each track to form an error correction block having a product code structure.

As described above, it is convenient to use the track number Tr, the sync block number in each track, and the symbol number in each sync block as addresses when accessing the TM area 109c.

The access of each processing block to the memory unit 109 is controlled by the address conversion circuit 215.

That is, the address conversion circuit 215 is
A command designating each operation mode such as a reproduction mode, a recording mode, and a recording pause mode is transmitted from the bus 19 or 233 via the bus 223, or a command of each mode is transmitted directly by a predetermined bit of an address of each block. Then, the scheduling regarding the data transfer priority is performed according to the information, and each processing block is stored in the memory unit 10 according to the access request from each block.
9 is arbitrated for data transfer.

These commands correspond to a control signal generated by operating the operation switch 111 of FIG.
9, 233 are determined by detection. These various modes include recording, playback, and recording pause modes,
For example, various modes such as dubbing and editing, dubbing and the like are included.

The address conversion circuit 215 generates a predetermined address, which will be described later, for each processing block so that addressing can be performed in an optimum data unit according to the processing mode in each processing block and the address space of the memory unit 109.

The address generation operation in the address generation circuit 215 is configured to be variably set based on a parameter corresponding to an image type transmitted from each of the CPUs 219 and 233. For example, if the recording mode is S
Different addresses are generated according to the image type such as DSDL, NTSC or PAL, and the type of the memory unit 109 (memory capacity described later). Where SD
L is a mode in which the data amount of the image signal to be recorded in the SD mode is reduced to half and the recording time can be doubled. In the SDL mode, one frame of image data is composed of five lines. Recorded on the track.

On the other hand, each processing block is supplied with a required clock, and operates in synchronization with the clock.

These clocks are supplied to the audio processing block 205 by the first clock (13.5 MHz in this embodiment) supplied to the VB 203 based on the synchronization signals Vsync and Hsync extracted from the input signal and the internal reference clock. The supplied second clock (4 in this embodiment)
8 MHz), COMP block 207, ECC block 209, address conversion circuit 215, memory I / F 217
And a third clock (67.5 MHz in this embodiment) supplied to the memory unit 109 and a fourth clock (41.85 MHz in this embodiment) for performing recording and reproduction on a tape.

Next, the division of the VM area 109b and the TM area 109c and the
The extended use of the M area will be described.

FIG. 4 shows an SDRA having a capacity of 16 Mbits.
M, 1024 bytes in column (hereinafter col) direction,
It has a memory space of 2048 bytes in the row direction. When the memory of FIG. 4 is used, the memory is divided into a VM area 109b for storing uncoded data and a TM area 109c for storing coded data. In the memory of FIG. 4, the MV area 109b can store two frames of uncoded image data and audio data, and the TM area 109c can store three frames of coded image, audio data and other additional data. Data can be stored. The configuration in FIG. 4 is a minimum configuration for recording and reproducing a moving image in real time in the VTR 100 of the present embodiment, and is mapped as shown in FIG.

FIG. 5 shows an S having a capacity of 64 Mbits.
This is a DRAM having a memory space of 1024 bytes in the col direction and 8192 bytes in the row direction. In the present embodiment, when the memory of FIG. 5 is used, the memory space is divided into a VM area for two frames and a TM area for three frames as a minimum area for processing the above-described moving image. At the same time, the remaining area 109d, that is, the area after the 2047th byte at the col address is allocated as a storage area of the encoded image data. The TM area is mapped in the same manner as in FIG.

In this embodiment, the CPU 219 controls the IC 2
The type of the memory unit 109 connected to 00 is 16M in FIG.
A bit memory or a 64-Mbit memory in FIG. 5 is identified, and mapping by the address conversion circuit 215 is controlled according to the identification result. Address conversion circuit 215
Changes the allocation of the memory space to each memory based on the information of the identified memory type, generates an address, and controls writing and reading of data between each processing block and the VM area and the TM area.

In the present embodiment, a memory area of 30 rows × 440 col is required to store the compressed data for one track in the memory. For a 64 Mbit SDRAM,
Excluding the voice data and subcode data areas, an area of about 6120 rows × 1024 colors can be secured as the TM area.

Accordingly, a memory area for 408 tracks can be secured in the TM area for moving image processing. When converted into the number of frames, the following is obtained depending on each mode.

In the SD mode of NTSC: 40 frames In the SDL mode of NTSC: 80 frames In the SD mode of PAL: 34 frames In the SDL mode of PAL: 68 frames

Next, the processing associated with the recording mode and the recording pause mode in this embodiment will be described with reference to FIG.

Each processing block in FIG. 2 accesses the memory 109 at the same time. By appropriately controlling the bank / track accessed by each block, a processing flow at the time of recording and reproduction can be created.

In this embodiment, the TM area is treated as a linear absolute track address, and the track address accessed by each processing block is calculated from the reference track address with an offset required for each processing. FIG.
FIG. 3 is a diagram showing a processing flow of image signals in a recording mode and a recording pause mode in the NTSC SD format when a 64-Mbit SDRAM is used as the memory 109. The same numbers are used for the same components as those in FIGS. A description is given below.

When a recording pause mode is instructed by operating the operation switch 111, the image signal from the camera unit 101 is processed by the VB block 203, and then the memory 10 is processed in a 4: 1: 1 signal format according to the SD format.
9 is written to Bank1 of the VM area 109b. The VB block 203 converts the sub-elevation signal to B over one frame time.
While writing to ank1, the COMP block 207
Reads an image signal from Bank0 of the TM area 109b in units of video segments, which are units of compression encoding,
Perform encoding processing. Reference numerals 601 and 602 denote write and read addresses generated for the TM area, respectively. At this time, the COMP block 207
Reads an image signal to perform shuffling according to a predetermined rule.

The COMP block 207 converts the coded image data into TM
Writing is performed in each of the areas Tr0 to Tr9 in the area 109c.
At this time, image data is written in the TM area along the line on the recording track. The ECC block 209 reads the image data written in the TM area one track at a time, performs an error correction encoding process using the parity data, and writes the data in the TM area again.

In the recording pause mode, the processing of FIG. 6 is continuously performed. And, as a TM area, 10 in FIG.
Using 9c and 109d, a write address is cyclically designated among the areas Trk0 to Trk407 of the TM area as shown in FIG. 6, and the error-correction-encoded coded image data is sequentially written in the TM area.

Next, the operation when the recording switch is operated by the operation switch 111 in the recording pause mode to enter the recording mode will be described.

In this embodiment, reading from the memory 109 is started from the image data written in the TM area a predetermined period before the recording start instruction is issued, and recording is performed.

That is, the CPU 213 stores in advance a period for reading back from the recording start instruction. For example, if the set time is 1 second, the area where the COMP block 207 is writing the image data at the time of the recording start instruction is Trk300, and the track is the head of the frame, the RP block 211 Reading is started from the image data stored in Trk0 corresponding to one second before that point (1 second = 30 frames × 10 tracks = 300 tracks).

If the set time is 0.5 seconds, the RP block 211 is stored in the Trk 150 corresponding to 0.5 seconds before (0.5 seconds = 15 frames × 10 tracks = 150 tracks). The reading is started from the image data which is being read.

If the current write position of the image data by the COMP 207 is the Trk 300 and that track is the last track of the frame, the RP block 21
1 starts reading from an image stored in the Trk 399 corresponding to one second before that point.

Thereafter, as shown in FIG. 6, the mode shifts to a recording mode in which image data read from the TM area is sequentially recorded on the tape T while processing the input data and cyclically writing the TM areas 109c and 109d.

In the recording mode, an offset corresponding to the time set in the CPU 213 is provided between the write address and the read address for the TM area as described above. When the set time is one second, an offset for one second is provided.

In the recording mode in which recording is performed as described above, when a recording pause is instructed by the operation switch 111, the writing of the encoded image data to the TM areas 109c and 109d is continuously performed, and the RP block 211 After one frame of image data is read from the recording pause instruction, the reading is stopped, the recording is stopped, and the mode shifts to the recording pause mode.

Here, T is generated by the CPU 213, and T
The system data stored in the M area includes 1-bit data indicating a recording start position. CPU 21
When the recording start is instructed by the switch 111, 3 rewrites the 1-bit data code indicating the recording start position in the system data of the recording start position among the system data already written in the TM area, and Accordingly, the ECC block 209 is controlled to perform replacement of parity data.

In this embodiment, sync blocks for various system data are prepared for three sync blocks in one track, and have a configuration shown in FIG. 7, for example.

As described above, one sync block includes a sync, ID, ID parity, system data or coded image / audio data, and parity for error correction.
It is composed of 0 bytes of data, of which system data is set at byte positions 5 to 9 as shown in FIG. Here, the data that needs to be rewritten along with the start of recording is the system data PC2 at the seventh byte, and among them, the RECST bit of bit 8 is
This indicates that this is the first frame after the start of recording.

The CPU 213 rewrites the RECST bit indicating the recording start position for all the system data of the 10 tracks related to the first frame after the recording starts.

For the audio data, an area capable of storing the same number of tracks of audio data as the image data is secured in the TM area, and the audio data is processed in synchronization with the processing of the image data.

When a 16-Mbit memory is used as the memory 109, there are only the VM area 109c and the VM area 109c, and there is no extended area 109d as shown in FIG. 5 as a TM area. The writing using only the TM area 109c is performed during the recording pause mode without performing the processing using the extended TM area 109d.

As described above, according to the present embodiment, a 16-Mbit SDRAM and a 64-Mbit SDRA are used as memories.
The use of the memory space is automatically changed when M is used, and when the 64 Mbit SDRAM is used, the code is repeatedly used in the recording pause mode by using an area other than the minimum area necessary for recording and reproducing moving images. Writing coded image data.

For this reason, even when the recording operation is started from the recording instruction and the actual recording operation is started, or when the recording start instruction is delayed from the desired scene due to the user's own factor, the user's operation is not required. An image signal of a desired scene can be reliably read from the memory and recorded.

In the above embodiment, the case where the 16 Mbit SDRAM and the 64 Mbit SDRAM are selectively used has been described. However, the memory capacity may be other than this, and the minimum required for recording / reproducing a moving image. When a memory having a capacity exceeding the limited capacity is used, the memory space can be appropriately allocated and used as a storage area for encoded image data in the recording pause mode.

[0068]

As described above, according to the present invention,
Since the image signal encoded in the recording pause mode is cyclically written to the second type of memory, recording can be started from the image signal obtained before the start of recording, and the image of the scene intended by the user can be started. Signals can be reliably recorded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR to which the present invention is applied.

FIG. 2 is a diagram showing a configuration of a main part of the signal processing circuit of FIG. 1;

FIG. 3 is a diagram showing a processing flow by the circuit of FIG. 2;

FIG. 4 is a diagram showing a state of a memory used in the embodiment.

FIG. 5 is a diagram showing a state of a memory used in the present embodiment.

FIG. 6 is a diagram for explaining a processing flow of an image signal by the circuit of FIG. 2;

FIG. 7 is a diagram showing a state of system data handled in the present embodiment.

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Claims (9)

[Claims] 1. A first type of memory having a first storage capacity, in which a first address space and a second address space are set, and a second storage which is larger than the first storage capacity. An apparatus having a capacity and capable of using a second type of memory in which the first, second and third address spaces are set, wherein an image signal is input to the first type of memory. Kind of memory or second
Input means for writing to a first address space in a memory of the type; encoding an image signal written to the first address space; and inputting a second signal in the memory of the first type or the second type of memory. Encoding means for writing to the address space; recording means for recording the image signal encoded by the encoding means; recording mode for recording the image signal and the additional signal by the recording means; and the image by the recording means. Mode setting means for setting a mode among a plurality of modes including a recording pause mode for stopping recording of a signal and an additional signal; and when the second type of memory is used, the mode is set in the recording pause mode. The encoding unit and the second encoding unit write the encoded image signal by cyclically designating addresses in the second and third address spaces. And a control unit for controlling the types of memories. 2. An additional signal generating means for generating an additional signal related to the image signal, wherein the control means further generates the additional signal so as to write the additional signal into the third address space in the recording pause mode. 2. The recording apparatus according to claim 1, wherein the recording apparatus controls the means and the second type of memory. 3. The additional signal generation unit further changes the code of a part of the additional signal stored in the third address space in response to a recording start instruction from the mode setting unit. 3. The recording apparatus according to claim 2, wherein the recording apparatus is controlled. 4. The second address space or the third address space.
Error correction processing means for performing error correction encoding processing on the image signal and the additional signal stored in the address space using the parity data, wherein the control means responds to the recording start instruction to execute the partial 4. The recording apparatus according to claim 3, wherein said error correction processing means is controlled to change parity data of the additional signal whose code has been changed. 5. The control means according to claim 1, wherein, when using said first type of memory, said encoded address is cyclically designated in said recording pause mode by specifying an address in said second address space. 2. The recording apparatus according to claim 1, wherein the encoding unit and the first type of memory are controlled so as to write an image signal. 6. The mode setting means has an instruction means for instructing a recording start, and the control means responds to the recording start instruction a predetermined time before the recording start instruction. 2. The recording apparatus according to claim 1, wherein the recording unit and the second type of memory are controlled to start reading from the encoded image signal written in the memory and start recording. 7. The control unit further stops reading of the encoded image signal stored in the second type memory after the predetermined period from the recording stop instruction in response to the recording stop instruction. 7. The recording apparatus according to claim 6, wherein the recording unit and the second type of memory are controlled so as to stop recording. 8. The control means detects a write address of the coded image signal in the second type of memory when the recording start instruction is issued, on a frame-by-frame basis, and determines a predetermined frame from the detected frame. 7. The recording apparatus according to claim 6, wherein said recording means and said second type of memory are controlled so as to start reading from an encoded image signal of a previous frame and to record. 9. An input unit for inputting an image signal, a memory, a generation unit for generating an additional signal related to the image signal, and an error correction encoding for the image signal and the additional signal stored in the memory. Error correction processing means for performing processing and writing again to the memory, recording means for recording the image signal and the additional signal subjected to the error correction encoding processing on a recording medium, and processing of the image signal and the additional signal by the recording means. Mode setting means for setting a mode between a plurality of modes including a recording mode for performing recording and a recording pause mode for stopping recording of the image signal and the additional signal by the recording means; Specifying a write address of the memory, writing the error-correction-encoded image signal and the additional signal to the memory, A memory control unit for controlling a storage operation; and the generating unit for converting a part of the additional signal stored in the memory into a predetermined code in accordance with a recording start instruction, and performing an error correction encoding process again. A recording device comprising: a control unit that controls the error correction processing unit.