JP2001275060A - Standard / high-definition television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a standard/high-definition television reception device which has a small circuit scale and reduced image deterioration. SOLUTION: This device is equipped with a standard TV progressive scanning conversion circuit which converts the interlaced scanning of standard television signals to progressive scanning signals, a high-definition TV-to-progressive scanning conversion circuit which converts high-definition television signals to progressive scanning signals, a selecting circuit which selects and outputs one of the two converted progressive scanning television signals, and a TV system discrimination control circuit which discriminates which of the standard television signal and high-definition television signal constitutes an arrival television signal and controls the selection circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard / high-definition television receiver capable of receiving two types of television signals, a standard television signal and a high-definition television signal.

[0002]

2. Description of the Related Art In response to demands for higher image quality of television receivers, new high-definition televisions have been developed in recent years. This high-definition television was proposed by the Japan Broadcasting Corporation (NHK) ahead of the world and has an aspect ratio of 1
6: 9 (or 5: 3), 1125 scanning lines, and the current standard television system (aspect ratio 4: 3, scanning lines 5
25).

As a service form of this high-definition television, a high-definition satellite transmission system (hereinafter abbreviated as MUSE) for transmitting a band-compressed signal using a broadcasting satellite has been developed. The principle of MUSE, the signal format, and the schematic configuration of the receiving apparatus are described in "Ninomiya et al.," Hi-Vision Satellite Transmission System-MUSE- ", Journal of the Society of Television Engineers, Vol.
7, (1988) ". When such high-definition television broadcasting starts, it is necessary for the receiving apparatus to be able to receive a conventional standard television signal and a MUSE signal. In response to such demands, several processing methods have been devised so far. For example, JP-A-59-70369 and JP-A-59-70369 show conversion methods between a high-definition television system and a standard television system. Japanese Patent Application Laid-Open Nos. 61-206380 and 61-206, each showing a method for eliminating a difference in aspect ratio.
No. 381, 63-26172, 63-263783
And Japanese Patent Application Laid-Open No. 62-206977 in which an image memory used for both types of processing is shared.

[0004]

In the above prior art, consideration is given to the point that a so-called double-speed television, which converts interlaced scanning of a standard television signal into progressive scanning and displays the MUSE signal, is processed. However, there were problems with the following points. (1) When using 16: 9 high definition display, MU
Since the SE signal is completely decoded, the scale of the processing circuit increases and the cost increases. (2) When using 4: 3 standard display, MUSE
Since the signal is converted into a standard television signal, the image is greatly reduced.

An object of the present invention is to solve the above-mentioned problems and to provide a standard / high-definition television receiver having a small circuit scale and less image deterioration.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a standard TV progressive scan conversion circuit for converting interlaced scanning of a standard television signal into a progressive scan, and a high quality TV sequential circuit for transforming a high quality television signal into a progressive scan. A scan conversion circuit, a selection circuit for selecting and outputting one of the converted two progressive scanning television signals, and a selection circuit for identifying whether the incoming television signal is a standard television signal or a high-definition television signal, and This is achieved by providing a TV system identification control circuit for controlling.

[0007]

The standard TV progressive scan conversion circuit reduces interference caused by interlaced scanning of a standard television signal and produces a higher quality video signal. The high-quality TV progressive scan conversion circuit has a simpler circuit configuration that converts, for example, 1125 scan lines into 562 progressive scan signals and completely decodes the conventional MUSE signal. Creates a high-quality video signal with improved vertical resolution compared to the standard television signal. The TV system detection control circuit detects the system of the incoming television signal, and
Since the output of one of the scan conversion circuits controls the selection circuit to which the video signal subjected to the sequential scan conversion processing that matches the incoming television signal is output, no malfunction occurs.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is an embodiment of a standard / high definition television receiver according to the present invention. In FIG. 1, an FM-modulated MUSE signal or a standard television signal (hereinafter abbreviated as NTSC signal) is input to a satellite broadcast antenna 1 and converted into a baseband signal by a tuner / detection circuit 2 for switching. It is supplied to the circuit 3. In addition, U.VH
An AM-modulated video signal is input to the F antenna 4, converted into a baseband signal by a tuner / detection circuit 5, and supplied to the switching circuit 3. The tuner / detection circuits 2 and 5 and the switching circuit 3 are controlled by a channel selection circuit 6 to select a broadcast wave or a channel desired by the user. Therefore, either the MUSE signal or the NTSC signal is present in the signal path 7, which is the output of the switching circuit 3.

First, a case where an NTSC signal arrives will be described. In this case, an interlaced scanning video signal is converted into a progressive scanning video signal by a standard TV progressive scanning conversion circuit 9 based on a synchronization signal and a clock signal generated by a standard TV sequential processing synchronization / clock generation circuit 8, The data is supplied to the display circuit 13 via the video switching circuit 10. Similarly, for the synchronization signal, the standard TV sequential processing synchronization / clock generation circuit 8 generates a horizontal synchronization signal having a frequency of 15.7 KHz.
A horizontal synchronizing signal of 31.5 KHz is generated and supplied to the deflection circuit 12 via the synchronizing switching circuit 11. Deflection circuit 12
Deflects the display circuit 13 in the horizontal and vertical directions, and reproduces a sequentially scanned image having 525 vertical scanning lines based on the video signal input to the display circuit 13.

Next, the case where the MUSE signal arrives will be described. In the case of the MUSE signal, in order to generate an accurate digital synchronization, the analog signal is converted into a digital signal, and then the synchronization signal and the clock signal are reproduced by the high-quality TV sequential processing synchronization / clock generation circuit 14. On the basis of the synchronizing signal and the clock signal, the high-quality TV progressive scan conversion circuit 15 converts an interlaced scan video signal having 1125 vertical scanning lines into a 562/563 progressive scan video signal, and performs video switching. The signal is supplied to the display circuit 13 via the circuit 10. As for the synchronizing signal, a high-quality TV sequential processing synchronizing / clock generating circuit 14 generates a vertical synchronizing signal for sequential scanning synchronized with the horizontal synchronizing signal, and supplies it to the deflection circuit 12 via a synchronizing switching circuit 11. Deflection circuit 1
In No. 2, in order to absorb the difference in aspect ratio between the standard TV progressive scanning signal and the high-quality TV progressive scanning signal, the horizontal size or vertical size to be deflected is changed by the deflection size switching circuit 16, and the aspect ratio matching the MUSE signal is obtained. Causes the display circuit 13 to reproduce an image.

The signal system identification between the NTSC signal and the MUSE signal is performed by the TV system identification control circuit 17. More specifically, the video switching circuit 10 and the synchronization switching circuit 11 are performed by using the channel selection information of the channel selection circuit 6 and the synchronization pull-in information of the high-quality TV sequential processing synchronization / clock generation circuit 14. , And the deflection size switching circuit 16. In addition, the circuit operation of one unnecessary part of the standard TV sequential scan conversion circuit 9 and the high-quality TV sequential scan conversion circuit 15 is stopped by the identification output of the TV system identification control circuit 17 to reduce power consumption. It is possible to achieve. The TV system identification control circuit 17 can be realized by a single microcomputer 18 together with the channel selection circuit 6.

The above is an explanation of one embodiment of FIG. Next, the operation of the main circuit will be described in more detail in order to clarify the circuit operation and effect of FIG.

FIG. 2 is a diagram illustrating the principle of progressive scan conversion of a standard TV signal, FIG. 3 is a diagram illustrating the principle of progressive scan conversion of a high-quality TV signal,
4 is a diagram showing an example of the standard TV progressive scan conversion circuit of FIG. 1, FIG. 5 is a diagram showing an example of a luminance signal double speed processing circuit of FIG. 4, FIG. 6 is a diagram showing an example of a high-quality TV signal processing circuit, 7 to 11 are diagrams for explaining the operation of the main circuit in FIG. 6, and FIG. 12 is a diagram showing an example of a display screen of the display.

First, an example of progressive scan conversion of an NTSC signal will be described with reference to FIGS. 2, 4 and 5. As is well known, NTSC signals use interlaced scanning, and 525 vertical scan lines are 262.5 lines in one field and the remaining 2 lines in another field.
62.5 lines are transmitted. In the progressive scan conversion, as shown in FIG. 2, a new interpolated scan line is created between scan lines transmitted in a certain field, and 52
This is a process for creating a signal for reproducing five scanning lines. FIG. 4 shows an example of a circuit that performs such processing. In the figure, a terminal 20 indicates a signal input terminal from the switching circuit 3, a terminal 21 indicates a signal input terminal from the standard TV sequential processing synchronization / clock generation circuit 8 in FIG. 1, and a terminal 22 indicates a signal input terminal in FIG.
The signal input terminal from the V system identification control circuit 17 is shown. The NTSC signal input from the terminal 20 is a luminance signal
The luminance signal Y and the color difference signal R are output by the color signal separation circuit 23.
−Y and BY are supplied to a luminance signal double speed processing circuit 24 and a color difference signal double speed processing circuit 25, respectively.
The luminance signal double-speed processing circuit 24 uses the video signal recorded and reproduced in the memory 26 to output a luminance signal Y ′ corresponding to double-speed scanning.
And outputs it to the output terminal 28. Similarly, the color difference signal double-speed processing circuit 25 also outputs a color difference signal R-
Y ′ and BY ′ are created and output to output terminals 29 and 30. The signals output to the output terminals 28, 29, 30 are supplied to the video switching circuit 10. The memory control circuit 27
The recording and reproduction of the memory 26 is controlled by using the synchronization signal and the clock signal input from the terminal 21. Terminal 22
Is input to the memory control circuit 27 from the
By stopping the operation of the memory, low power consumption can be achieved when the MUSE signal arrives.

FIG. 5 shows an example of the luminance signal double speed processing circuit 24 shown in FIG. In the figure, signal processing adapted to the motion of the image is performed, and the operation can be described in the same manner as in the principle of generating the interpolation signal shown in FIG. The terminal 31 is connected to the luminance signal Y separated by the luminance / color signal separating circuit 23.
Input terminal. Symbols a, b, c, and x mean respective signal paths and signals in order to clarify the correspondence with FIG. The ADC 32 shown in FIG. 5 converts the luminance signal Y into a digital signal and outputs the digital signal to the switching circuit 3 via the signal path b.
3, an addition circuit 34, a line memory 35, a subtraction circuit 36,
And to the field memory 37. Adder circuit 34
Then, the signal a delayed by the line memory 35 and the signal b on the signal path b are averaged, and the result is supplied to the mixing circuit 40. A signal c delayed by the field memory 37 is input to another input of the mixing circuit 40.
Further, the difference between the signal delayed by the frame in the other field memory 38 and the signal b is obtained in the subtraction circuit 36,
The motion detection circuit 39 converts the video signal into a motion signal for separating a moving image area and a still image area from each other and supplies the motion signal to the mixing circuit 40. In the mixing circuit 40, as shown in FIG. 2, when the motion signal from the motion detection circuit 39 indicates a moving image area,
The output signal (a + b) / 2 of the adder circuit 34 is selected, and the output signal c of the field memory 37 is selected to indicate a still image area and output to the signal path x. The switching circuit 33 switches and selects the signal b as an actual scanning line signal and the signal x as an interpolation scanning line signal, and supplies them to the double speed memory 41. As the double speed memory 41, a line memory HM63021 manufactured by Hitachi can be used, and the horizontal scanning cycle is converted into a half signal, and the conversion result is supplied to the DAC. The DAC 42 converts the digital signal into an analog double-speed luminance signal Y ′ and outputs it to the output terminal 28.

The above is a description of the progressive scan conversion of the standard TV signal. However, the configurations shown in FIGS. 4 and 5 are not limited to this. If possible. So-called IDTV (Impr
Such a progressive scan conversion circuit also includes a television processing method in which a luminance signal and a chrominance signal are separated using a frame memory and interpolation processing is performed using a field memory as an overdefined TV.

Next, an example of the progressive scan conversion of the MUSE signal will be described with reference to FIGS. 3 and 6 and subsequent drawings. The feature of the present invention is that, compared with the image quality of the NTSC signal obtained by sequentially scanning the MUSE signal, the MUSE signal allows deterioration to the highest image quality of the original MUSE signal to an extent that the MUSE signal is somewhat superior, and has a simple configuration. This progressive scanning conversion circuit has been realized. The MUSE signal is a signal which is band-compressed using offset sampling between fields and between frames in a still image area of an image and line offset sampling is used in a moving image area of an image. As described above, interlaced scanning is used similarly to the NTSC signal. The detailed transmission signal format is described in the aforementioned literature, Journal of the Society of Television Engineers, Vol. 42, no. 5, the number of vertical scanning lines is 1125 and the number of effective scanning lines is 1032. Therefore, the sequential scan conversion is performed by halving the number of vertical scan lines of the MUSE signal so that the number of vertical scan lines of the standard TV signal subjected to the sequential scan conversion is almost equal to 525. Therefore, the progressive scan conversion of the MUSE signal uses a transmitted scan line to create a new interpolated scan line having the same scan position between the fields, as shown in FIG. This is a process for creating a signal to be reproduced.

FIG. 6 shows an example of a processing circuit for converting a MUSE signal into a sequential scanning signal. 6, the same circuits as those in FIG. 1 are denoted by the same reference numerals. In the figure, a terminal 50 indicates a signal input terminal from the switching circuit 3,
A terminal 51 indicates a signal input terminal from the TV system identification control circuit 17. The signal input terminal from the terminal 50 is shown. The MUSE signal input from the terminal 50 is the LPF5
Unnecessary components of 8.1 MHz or higher transmitted by 2 are blocked, and are converted into digital signals by the ADC 53.
The converted signal is supplied to each of a video processing system and a synchronous processing system. In the video processing system, a signal from the TV system identification control circuit 17 input from the terminal 51 is gated by the gate circuit 54, and is supplied to the next non-linear de-emphasis circuit 55 only in the case of the MUSE signal. The nonlinear de-emphasis circuit 55 reversely corrects the non-linear processing for transmission, performs de-emphasis, and supplies a digitized MUSE signal to the progressive scanning interpolation circuit 56. Although the configuration of the progressive scanning interpolation circuit 56 will be described later, the interpolation-processed signal is subjected to line-sequential multiplexing of a chrominance signal and a luminance signal by a color-line-sequential separation circuit 57, and the LPF 5
8, output terminal 6 as a sequential scanning signal via DAC 59
0, 61 and 62 are output.

In the synchronous processing system, digitalized MUS
From the E signal, a frame pulse is detected by a frame pulse detection circuit 63, a horizontal synchronization signal is detected by a horizontal synchronization gate circuit 64 and a horizontal synchronization detection circuit 65, and the generated synchronization of an internal synchronization generation circuit 66 is synchronized with the incoming signal. Let it. The frequency divider existing in the internal synchronization generator 66, the phase comparator 67, and the VCO 68 form a PLL circuit, and are configured to reliably perform phase synchronization with an incoming horizontal synchronization signal.
The output of the phase comparison circuit 67 is also supplied to a phase lock detection circuit 69 in addition to the VCO 68, and detects a loss of synchronization.
In the case of out-of-synchronization, the switching circuit 70 is controlled, and the gate signal of the horizontal synchronization gate circuit 64 is transmitted to the internal synchronization generation circuit 66.
Is switched from the pulse that occurs to the pulse that is created directly from the incoming signal. The detection output of the phase lock detection circuit 69 is also supplied from the output terminal 71 to the TV system identification control circuit 17 and is used for automatic TV system identification. The display horizontal synchronizing signal H and the display vertical synchronizing signal V generated by the internal synchronizing circuit 66 are supplied to an output terminal 72,
The signal is supplied from 73 to the synchronization switching circuit 11.

In FIG. 6, an example of an internal synchronization generating circuit 66 and a phase lock detecting circuit 69 for generating a synchronizing signal for sequential scanning which is considered to be characteristic are shown in FIGS. 7 and 8, respectively. 7 and 8, the same circuits as those in FIG. 6 are denoted by the same reference numerals. 7, a terminal 74 is a clock input terminal to which a system clock signal is input from the VCO 68, a terminal 75 is an input terminal of a frame pulse from the frame pulse detection circuit 63, and a terminal 76 is from a horizontal synchronization detection circuit 65. Input terminal for horizontal synchronization signal. The horizontal counter 77 counts the clock signal input from the terminal 74 with reference to the horizontal synchronizing signal input from the terminal 76, counts the 16.2 MHz system clock signal to the output terminal 84, and counts to the horizontal decoder circuit 80. Supply output signal. The horizontal decoder circuit 80 feeds back the decoded value to the horizontal counter 77 so as to generate a pulse of a horizontal cycle, outputs a display horizontal synchronizing signal to an output terminal 72, and outputs a synchronizing gate signal to be supplied to the switching circuit 70 to an output terminal 82.
Then, the phase comparison pulse supplied to the phase comparison circuit 67 is output to the output terminal 83. Vertical counter circuit 78
, The horizontal period pulse generated by the horizontal decoder circuit 80 is input as a clock, and the count of 562 and the count of 563 are alternately repeated with reference to the frame pulse input from the terminal 75. This alternate count is determined by the output of the field counter 79 and the vertical decoder circuit 81 changes the decode value fed back to the load input of the vertical counter circuit 78. As shown in the figure, the display vertical synchronizing signal supplied from the output terminal 73 to the switching circuit 11 can be supplied as it is from the vertical decoder because of the sequential scanning, and the generation of the vertical synchronizing signal can be performed by the conventional interlacing. There is an advantage that it can be simplified compared to scanning. In the entire internal synchronization generation circuit 66, the conventional MUSE signal processing circuit forms a vertical counter in units of frames and decodes each field. A counter can be configured, and the circuit scale can be reduced.

Next, the phase lock detection circuit shown in FIG. 8 will be described. In the figure, the terminal 85 is an input terminal for inputting the output signal V _C of the phase comparator 67, the reference voltage value V generated respectively by the reference voltage generating circuit 86 and 87
_1, and _{V 2,} is compared with the signal _{V C,} which is the input at the comparator circuit 88. Since the MUSE signal does not fluctuate in the period of the synchronization signal, the comparison circuit 88 performs, for example, voltage comparison (V ₁ <V
_The phase lock state can be easily determined only by _C <V ₂ .
This determination result is supplied to the switching circuit 70 via the integration circuit 89 and the output terminal 91, and is used for synchronization pull-in control. The result of this determination is sent from the output terminal 71 to the TV system identification control circuit 1 through the integration circuits 90 having different integration times.
7 is output as a signal indicating the arrival of the MUSE signal.
As described above, since the MUSE signal is transmitted in an extremely accurate synchronization relationship, the arrival of the MUSE signal can be detected with a simple configuration as shown in FIG.

Next, the progressive scanning interpolation circuit 56 which is important in the progressive scanning of the video processing system will be described in detail.

FIG. 9 shows a sample transmitted by a MUSE signal.
Points and sample points interpolated by the progressive scanning interpolation circuit 56
FIG. 10 shows an example of a pixel arrangement and an interpolation ratio.
FIG. 11 shows a specific configuration of the progressive scanning interpolation circuit 56.
It is a figure showing an example. FIG. 9 shows the scanning line structure of FIG. 3 more clearly.
It is also a diagram that is clearly expressed, the position of the circle is the transmission sample
Interpolated sample points of the scan line where the positions of points and triangles are interpolated
Is shown. Here, for explanation of interlaced scanning, the second
Upper scanning line of upper and lower scanning lines adjacent to each other in yield (a)
When the lower scanning line is transmitted in the first field (b).
I do. In the second field, the transmission sample point is S₁~ S
₁₂And the notable interpolation sample point is I _M, I_NToss
Then, as an example, I_M, I_NCan be expressed by the following equation.
You.

[0024]

(Equation 1) Similarly, in the first field, the transmission sample point is set to T
_{1 to} T _12, and the interpolation sample points to be noted are I _O , I
_Assuming that _P , I _O and I _P can be represented by the following equations.

[0025]

(Equation 2) The interpolation sample points represented by the above equations (1) to (4) are selected so that the sample points after interpolation are located at the same position in space as shown in FIG. This is to prevent the center of gravity of the processing of the video signal from being shifted. An example of the pixel arrangement and the interpolation ratio at this time will be described with reference to FIG. In the MUSE signal, pixels transmitted in one frame are 748 points horizontally and 1032 points vertically.
It corresponds to a display with an aspect ratio of 16: 9. The ratio of the but connexion, the distance between lines between the distance and the pixels on the Deisupurei is generally as shown in FIG. 1: 2, and the position of the transmission sample points near Taking as an example the interpolation sample point I _P The interpolation ratio is as shown in FIG. FIG. 11 shows a specific circuit for realizing such interpolation. In the figure, the signal input from the input terminal 100, through the sample black poke three one-line memory 106, 107, and 108 driven by (hereinafter referred to as _{f S)} inputted from the input terminal 101, 4 The signal is input to the switching circuit 109 as a signal for a scanning line. In switching circuit 109, and supplies the horizontal filter circuit 110-113 for selecting and driving the zero level as the input signal every half cycle of _{f S} in 2f _S. Horizontal filter 110
113, and a half cycle unit of f _S inputted from the respective terminals 102, by changing the coefficients of the filter to the field unit using the frame pulse input from the terminal 103,
The operation is performed so as to match the expressions (1) to (4). The outputs of the horizontal filters 110 to 113 are combined by an adding circuit 114 and output to the output terminal 105 as an interpolation signal.

As described above, this embodiment has an advantage that a video signal for sequential scanning can be obtained with a very simple circuit configuration.

Finally, the operation of the deflection size switching circuit 16 of FIG. 1 will be described. The deflection size switching circuit 16 has a function of T
Upon receiving a control signal from the V-system switching control circuit 17, the deflection size of the deflection circuit 12 is switched so as to obtain a display screen as shown in FIG. Switching the deflection size is achieved by changing the amplitude of the sawtooth wave for deflection. 12A and 12B show the case where a standard TV display (aspect ratio 4: 3) is used for the display 13, and FIGS. 12C and 12D show high-quality displays (aspect ratio 16: 9). Is shown. (A) and (c) show the reception state of the standard television signal, and (b) and (d) show the reception state of the high-definition television signal. As described above, regardless of the aspect ratio of the display 13, both the standard and high-definition television signals can be displayed by switching the horizontal and vertical deflection sizes. When the broadcasting of the high-definition television signal is relatively small, the display methods (a) and (b) are more effective.

[0028]

As described above in detail, according to the present invention, it is possible to provide a standard / high-definition television receiver having a small processing circuit scale and little image quality deterioration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a standard / high definition television receiver according to the present invention.

FIG. 2 is a diagram illustrating the principle of progressive scan conversion of a standard TV signal.

FIG. 3 is a diagram illustrating the principle of progressive scan conversion of a high-quality TV signal.

FIG. 4 is a block diagram showing a specific example of a main configuration circuit of FIG. 1;

FIG. 5 is a block diagram showing a configuration example of a luminance signal double speed processing circuit of FIG. 4;

FIG. 6 is a block diagram showing a specific example of another main configuration circuit of FIG. 1;

FIG. 7 is a block diagram showing an example of a more detailed configuration of a main configuration circuit of FIG. 6;

FIG. 8 is a block diagram showing an example of a more detailed configuration of a main configuration circuit of FIG. 6;

FIG. 9 is a diagram for explaining the progressive scanning interpolation circuit shown in FIG. 11;

FIG. 10 is a diagram for explaining the progressive scanning interpolation circuit shown in FIG. 11;

FIG. 11 is a block diagram showing a specific example of the progressive scanning interpolation circuit of FIG. 6;

FIG. 12 is an explanatory diagram showing an example of a display screen of a display.

[Explanation of symbols]

1 ... satellite broadcasting antenna, 2, 5 ... tuner / detection circuit,
4: U / VHF antenna, 3, 10, 11 ... switching circuit,
8: Standard TV sequential processing synchronization / clock generation circuit, 9: Standard TV sequential scanning conversion circuit, 12: Deflection circuit, 13: Display, 14: High quality TV sequential processing synchronization / clock generation circuit, 15: High quality TV sequential scanning Conversion circuit, 17 ... T
V-system identification control circuit, 56 ... progressive scanning interpolation circuit, 66 ...
Internal synchronization generation circuit.

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[Procedure amendment]

[Submission date] April 11, 2001 (2001.4.1
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shinobu Torigoe 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (72) Inventor Toshiyuki Sakamoto 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Home Appliance Research Laboratory (72) Inventor Takumi Okamura 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. Home Appliance Research Laboratory (72) Noboru Noboru 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Japan (72) Inventor Tetsuo Mitsuhashi 1-1-10 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Research Institute, Japan Broadcasting Corporation (72) Inventor Kondo Isao, 1-110 Kinuta, Setagaya-ku, Tokyo No. Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Yuichi Ninomiya 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation (72) Inventor Koichi Yamaguchi 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Research Institute (72) Inventor Toshiro Omura 2-1-1 Jinnan, Setagaya-ku, Tokyo Japan The broadcasting association broadcasting center

Claims (4)

[Claims] When a standard television signal adopting an interlaced scanning method is inputted, a standard television signal progressive scan conversion circuit for converting the signal into a progressive scan signal and outputting the signal, and a high definition television signal are inputted. A high-definition television signal progressive-scan conversion circuit that converts this into a progressive scan signal and outputs the selected signal, and a selection circuit that selects and outputs one of the progressive scan signals output from each of the conversion circuits. And a television type identification control circuit for identifying whether the television signal input to the conversion circuit is a standard television signal or a high-definition television signal and controlling the selection operation of the selection circuit. A standard / high-definition television receiver. 2. The standard television signal progressive scan conversion circuit is characterized in that at least a field memory is used to convert to a progressive scan signal using a motion adaptive signal processing circuit using scanning line interpolation. Standard of claim 1 /
High-definition television receiver. 3. The high-definition television signal progressive scan conversion circuit includes a synchronization generation circuit for generating at least a vertical synchronization signal synchronized with a horizontal synchronization signal of the high-definition television signal, and an interpolation point of a first field. 3. The interlaced scanning signal is converted into a progressive scanning signal using a progressive scanning interpolation circuit that interpolates the interpolation point of the second field so that the interpolation point overlaps with the interpolation point of the second field. Standard /
High-definition television receiver. 4. A standard / high-definition television receiver for selectively receiving one of a standard television signal and a high-definition television signal by a tuning circuit and displaying the selected signal on a display screen. And a deflection size switching circuit for switching between the deflection size switching circuit and the deflection size switching circuit for discriminating whether the selectively received television signal is a standard television signal or a high-definition television signal. Standard / high-definition television receiving apparatus, comprising: