JP2001274705A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem where conventional receiver having an AGC circuit as measures against fading cannot have ensured a satisfactory reception state resulting from an output signal whose level cannot maintain a prescribed level because a control range of the AGC circuit is deviated, if the level of an input signal is too small. SOLUTION: In the receiver, where an analog/digital converter 4 compares an analog signal with a reference voltage, converts the analog signal into a digital signal in accordance with the output of the comparison and the converted signal is detected, the reference voltage of the analog/digital converter 4 is varied, depending on a peak-to-peak value of the digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a receiving apparatus for performing a detection operation after converting a received analog signal into a digital signal.

[0002]

2. Description of the Related Art An analog signal (R
The magnitude of the F signal varies with time due to various factors (for example, mutual interference between signals having different propagation paths). Such a phenomenon is called fading, and is one of the causes that hinders the receiving operation in the receiving device.

As a countermeasure against the above-mentioned fading, a conventional receiving apparatus includes an automatic gain control (Automatic Gain control).
Control) circuit (hereinafter, referred to as an AGC circuit). This AGC circuit has a means for detecting its own output voltage (DC component) and an output transistor capable of changing a bias in accordance with the output voltage. When the output voltage becomes higher than a predetermined level, The gain of the output transistor is controlled by lowering the bias of the output transistor and conversely increasing the bias of the output transistor when the output voltage becomes lower than a predetermined level.

[0004] With this, even if the magnitude of the analog signal input to the receiving apparatus fluctuates due to fading or the like, the magnitude of the output signal of the AGC circuit can always be maintained at a predetermined level. The reception state can be secured.

[0005]

However, the aforementioned A
When an analog signal smaller than the dynamic range of the GC circuit is input to the receiving device, the magnitude of the output signal obtained from the AGC circuit no longer reaches the predetermined level, and a good reception state is obtained. It cannot be secured.

In particular, a received analog signal is converted to an analog signal.
In a receiving apparatus that performs a detection operation after converting a digital signal into a digital signal by a digital conversion circuit (hereinafter, referred to as an A / D conversion circuit), the magnitude of the analog signal input to the A / D conversion circuit is set to a predetermined level as described above. If the number of bits is less than the number of bits, the number of effective bits in the A / D conversion circuit becomes small, which causes a quantization error.

In order to solve such a problem, it is conceivable to improve the characteristics of the AGC circuit. However, increasing the gain of the AGC circuit beyond this is disadvantageous in terms of cost, and also raises a concern that the AGC circuit may oscillate. Therefore, the improvement of the characteristics of the AGC circuit cannot be a practical measure.

The present invention has been made in view of the above problems, and in a receiving apparatus that performs a detection operation after converting a received analog signal into a digital signal, it is possible to suppress, at low cost, an adverse effect caused by a change in the magnitude of the analog signal. An object is to provide a receiving device.

[0009]

In order to achieve the above object, in a receiving apparatus according to the present invention, a received analog signal is compared with a reference voltage, and binary encoding of the analog signal is performed according to the comparison output. A receiving device having an analog / digital conversion circuit for performing the demodulation and a detection circuit for demodulating a digital signal output from the analog / digital conversion circuit, comprising a means for varying the reference voltage in the analog / digital conversion circuit. It is characterized by.

Here, it is preferable that the reference voltage in the analog / digital conversion circuit is detected by detecting a peak-to-peak value of the digital signal and is varied according to the magnitude thereof. At this time, if the peak-to-peak value is always lower than a predetermined value during a predetermined period, control is performed so as to lower the reference voltage in the analog / digital conversion circuit. Value, the analog /
Control may be performed to increase the reference voltage in the digital conversion circuit. Further, a configuration may be employed in which an automatic gain control circuit is provided in a stage preceding the analog / digital conversion circuit.

On the other hand, an output signal of the automatic gain control circuit is compared with the reference voltage by using an automatic gain control circuit for forming a received RF signal at a predetermined level and a plurality of comparators having different reference voltages. An analog / digital conversion circuit for performing binary coding of the RF signal in accordance with a comparison output, wherein a digital signal output from the analog / digital conversion circuit is detected, and the analog signal is output according to the magnitude of the digital signal. A configuration may be adopted in which the reference voltage in the / digital conversion circuit is varied.

In the receiving apparatus having the above-described configuration, the analog / digital conversion circuit is configured such that a predetermined voltage is applied to both ends of a series connection circuit including a plurality of resistors, and a voltage extracted from a connection point between the resistors is used as the reference voltage. The reference voltage may be varied by controlling the magnitude of the predetermined voltage.

[0013]

FIG. 1 is a block diagram showing a configuration example of a receiving apparatus according to the present invention. As shown in the figure, an antenna 1 for receiving an analog signal (RF signal) receives an analog / digital conversion circuit 4 (hereinafter A) through a filter 2 and an automatic gain control circuit 3 (hereinafter referred to as an AGC circuit 3). / D conversion circuit 4) (hereinafter simply referred to as terminal a). As the means for receiving the analog signal, not only the antenna 1 but also a receiving means using a wire or the like can be considered.

On the other hand, a digital signal output terminal b of the A / D conversion circuit 4 (hereinafter simply referred to as terminal b) is connected to a detection circuit 5.
And an amplifier (not shown) and a sound reproducing unit (not shown), and a peak-to-peak value detecting circuit 6 (hereinafter referred to as a
pp value detection circuit 6). The output terminal of the pp value detection circuit 6 is connected to the reference selection circuit 7.

Here, the output terminal of the reference selection circuit 7 is connected to a reference voltage control terminal c (hereinafter simply referred to as a terminal c) of the A / D conversion circuit 4, and a predetermined voltage _Vref is applied to the terminal c. Added. Note that the reference selection circuit 7 according to the present embodiment has v, v / 2, v / 4, v /
In this configuration, the magnitude of the predetermined voltage _Vref is switched by selecting only one of the voltages having a magnitude of 8, for example.

Next, the operation of the receiving apparatus having the above configuration will be described. The analog signal received by the antenna 1 is band-limited by a filter 2 including a band-pass filter or the like, and then input to an AGC circuit 3.

The AGC circuit 3 has a means for detecting its own output voltage (DC component) and an output transistor capable of changing a bias according to the output voltage. When the output voltage is higher than a predetermined level, the bias of the output transistor is lowered, and when the output voltage is lower than the predetermined level, the bias of the output transistor is raised to control the gain. And keep the output voltage constant. Thus, the AGC circuit 3
The analog signal subjected to the gain control within the dynamic range is input to the terminal a of the A / D conversion circuit 4 in the next stage.

Here, the circuit configuration and operation of the A / D conversion circuit 4 for converting the analog signal into a corresponding digital signal will be described. As a general A / D conversion method, there are a feedback comparison method, a parallel comparison method, an integration method, and the like. Here, the circuit configuration of the A / D conversion circuit 4 is a parallel comparison method having an n-bit resolution. An explanation will be given using an example.

In the n-bit parallel comparison method, the input analog signal is simultaneously compared with a reference voltage having 2 ⁿ -1 levels, and the analog signal is binary-coded according to the comparison output. To obtain a digital signal, and the circuit scale becomes relatively large.
A / D conversion can be performed in a shorter time than other methods.

FIG. 2 is a circuit diagram showing an example of the configuration of the A / D conversion circuit 4. A predetermined voltage V from the reference selection circuit 7
_The terminal c to which _ref is added is grounded via _x (x = 2 ⁿ ) resistors R _{1 to} R _x connected in series as shown in the figure. Further, the voltages V _{1 to} V _x−1 taken out from the connection points of the respective resistors are respectively x−1 comparators Co
mp ₁ ~Comp _x-1 of the reference voltage V ₁ ~V _x-1 as the inverting input terminal (-) is inputted to.

On the other hand, the AGC circuit 3 outputs the analog signal
Are input to each of the comparators Comp.
₁~ Comp_x-1Connected to each non-inverting input terminal (+)
I have. In addition, the comparator Comp₁~ Comp_x-1Each of
The comparison output is line L ₁~ L_x-1Via prio
Is input to the power encoder circuit 40.

The priority encoder circuit 40 has an output level of "H", that is, the highest level of the lines L _{1 to} L _{x -1} in which the voltage value of the analog signal is higher than the reference voltages V _{1 to} V _{x -1.} Line numbers (1-x-
1) is binary encoded. As a result, the analog signal is converted into a corresponding digital signal. Thus, the input range of the A / D conversion circuit 4 is determined by the magnitude of the reference voltage V ₁ ~V _x-1. The digital signal obtained by the priority encoder circuit 40 is output from a terminal b.

If the A / D conversion circuit 4 has the above configuration, the reference voltages V _{1 to} V _x− of the comparators Comp _{1 to} Comp _x−1 can be changed only by changing the magnitude of the predetermined voltage V _ref applied to the terminal c. _Since all ₁ can be changed,
Switching of the input range of the A / D conversion circuit 4 can be realized very easily.

The digital signal output from the A / D conversion circuit 4 described above is demodulated by the detection circuit 5 and sent to the next-stage amplifier circuit section, audio reproduction section, and the like. The digital signal is also sent to a pp value detection circuit 6.

Here, the circuit configuration and operation of the pp value detection circuit 6 will be described. FIG. 3 is a block diagram showing a configuration example of the pp value detection circuit 6. FIG. 4 is a waveform diagram showing an example of an analog signal input to the receiving apparatus according to the present invention. As shown in FIG. 3, the digital signal from the A / D conversion circuit 4 is input to a p _max latch circuit 60 and a p _min latch circuit 61.

The above-mentioned p _max and p _min are the maximum value and the minimum value in the predetermined period t among the peak values of the digital signal obtained by A / D conversion of the analog signal. Namely, speaking in the waveform of the analog signal shown in FIG. 4, the maximum value in a predetermined period t is p _max
, And the minimum value corresponds to p _min , respectively. As described above, the p _max latch circuit 60 is a circuit that updates the peak value of the digital signal to a higher value.
_{The min} latch circuit 61 is a circuit that updates the peak value of the digital signal in a lower direction.

The subtractor 62 includes a p _max latch circuit 60 and p
p _max and p _min latched by the _min latch circuit 61, respectively.
By taking the difference (p _max −p _min ) from the above, the pp value in the predetermined period t is derived, and the pp value is output to the reference selection circuit 7. The reference selection circuit 7 determines a predetermined voltage V _ref to be applied to the terminal c of the A / D conversion circuit 4 based on the value of the pp value input from the pp detection circuit 6.
Choose the size of

With such a configuration, the A / D
The input range of the conversion circuit 4 can be appropriately switched according to the magnitude of the pp value, and hence the magnitude of the analog signal input to the A / D conversion circuit 4.
For example, if the analog signal is small, the input range of the A / D conversion circuit 4 is narrowed to keep the magnitude of the analog signal input to the A / D conversion circuit 4 relatively at a predetermined level. Can be. As a result, even when the magnitude of the analog signal fluctuates due to fading or the like, a good reception state can be ensured. Hereinafter, such a control operation of the predetermined voltage _Vref will be specifically described.

Here, the description will be made on the assumption that the circuit configuration of the A / D conversion circuit 4 is a parallel comparison system having a resolution of 8 bits. In this case, the pp value fluctuates in the range of 0 to 255. However, when the magnitude of the received analog signal is small enough to exceed the dynamic range of the AGC circuit 3, the AGC circuit 3 alone cannot maintain the magnitude at a predetermined level. Therefore, the input level to the A / D conversion circuit 4 decreases, and the magnitude of the digital signal output from the A / D conversion circuit 4
That is, the magnitude of the pp value naturally decreases.

In particular, when the magnitude of the pp value is always smaller than 128 (= 2 ⁷ ) in the predetermined period t, the effective bit number (8 bits) of the A / D conversion circuit 4 is utilized to the maximum. This causes a quantization error. Therefore, in order to solve such a problem, it is necessary to avoid a situation where the magnitude of the pp value always falls below 128 (= 2 ⁷ ) in the predetermined period t.

In order to realize this, the pp value is always a predetermined value (here, 2 ⁷ = 128) in a predetermined period t.
Is lower than the predetermined voltage V applied to the terminal c.
Control the size of _ref to be reduced by half, and conversely,
The pp value is its maximum value (here, 2 ⁸ -1 = 255)
In this case, the magnitude of the predetermined voltage _Vref may be controlled so as to be doubled.

For example, consider the case where the reference selection circuit 7 selects the voltage v as the predetermined voltage _Vref applied to the terminal c. At this time, the pp value input to the reference selection circuit 7 always becomes 12 during a predetermined period t.
If it is less than 8, the reference selection circuit 7 switches the magnitude of the predetermined voltage _Vref from the voltage v to the voltage v / 2. As a result, the input range of the A / D conversion circuit 4 is halved.

Here, if the magnitude of the predetermined voltage V _ref is reduced by half so that the magnitude of the pp value exceeds 128, the predetermined voltage V _ref is maintained as it is at the voltage v / 2. If the value of the pp value is still smaller than 128, the predetermined voltage _Vref is further reduced by half.
(That is, voltage v / 4).

[0034] Thus, when the pp value is always less than the predetermined value in a predetermined time period t is a predetermined voltage to determine a reference voltage V ₁ ~V _x-1 of the A / D conversion circuit 4 V _{re f} By controlling to reduce the size of the
Since the number of effective bits of the A / D conversion circuit 4 can be maximized, the occurrence of a quantization error can be suppressed.

On the other hand, a predetermined voltage V applied to the terminal c_refage
Thus, the reference selection circuit 7 selects the voltage v / 4.
Consider the case where At this time, the reference selection circuit 7
The pp value input as above is 255, which is the maximum value.
When the input range of the A / D conversion circuit 4 is reached,
The pp value is too narrow for the analog signal
Is overflowing, the reference selection
The selection circuit 7 has a predetermined voltage V _refFrom the voltage v / 4
Switch to pressure v / 2. Thereby, the A / D conversion circuit 4
Is twice as wide.

Here, the predetermined voltage V_refDouble the size of
By doing so, the magnitude of the pp value could not reach 255
If the predetermined voltage V_refIs maintained at the voltage v / 2 as it is.
Good, the size of the pp value still reaches 255
If so, the predetermined voltage V _refIs doubled (ie,
The pressure may be switched to v).

As described above, when the pp value reaches the maximum value, the reference voltage V of the A / D conversion circuit 4 is
By performing the control so as to increase the magnitude of the predetermined voltage V _ref to determine the ₁ ~V _x-1, said input range of the A / D conversion circuit 4 is too narrow for the analog signal, the pp value overflow It is possible to avoid such a problem that it occurs.

In the p _max latch circuit 60 and the p _min latch circuit 61 provided in the pp value detection circuit 6, p _max
If the predetermined period t during which the values of p and p _min are latched is set too short, a portion where the magnitude of the pp value becomes normally small due to the signal component may be determined to be abnormal. In the design of the above, it is desirable to set the predetermined period t to be relatively long (for example, 1 ms).

The reference selection circuit 7 shown in FIG.
Then, the voltage value of the predetermined voltage _Vref applied to the terminal c is v,
Although a configuration in which four of v / 2, v / 4, and v / 8 can be selected has been described, this is merely an example, and can be appropriately changed according to the use of the receiving device and required performance.

The A / D conversion circuit 4 shown in FIG.
, The AGC circuit 3 is provided at a stage preceding the analog signal to maintain the magnitude of the analog signal at a predetermined level.
As an auxiliary measure when the dynamic range of the C circuit 3 is insufficient, the control of the reference voltages V _{1 to} V _{x−1 in} the A / D conversion circuit 4 is performed. Therefore, since a double countermeasure is taken against the fluctuation of the analog signal, it is possible to more reliably ensure a good reception state.

In the above description, the circuit configuration employing the n-bit parallel comparison system as the A / D conversion circuit 4 has been described as an example. However, the circuit configuration of the A / D conversion circuit 4 is not limited to this. However, the present invention can be applied to any system in which the input range of the A / D conversion circuit 4 is determined by the magnitude of the reference voltage.

[0042]

In the receiving apparatus according to the present invention, the received analog signal is compared with a reference voltage in an analog / digital conversion circuit, and the analog signal is binary-coded according to the comparison output, and then the detection operation is performed. In the receiving apparatus for performing the above, a means for varying the reference voltage in the analog / digital conversion circuit is provided, and in particular, the reference voltage is varied according to the magnitude of the peak-to-peak value of the digital signal.

With such a configuration, the input range of the analog / digital conversion circuit is set to the magnitude of the peak-to-peak value, and thus the analog signal input to the analog / digital conversion circuit. Can be changed as appropriate according to the size of. Therefore, the magnitude of the analog signal input to the analog / digital conversion circuit can be relatively maintained at a predetermined level. It is possible to secure a proper reception state.

In the receiving apparatus according to the present invention,
When varying the reference voltage, if the peak-to-peak value is always lower than a predetermined value in a predetermined period, control is performed so as to lower the reference voltage in the analog / digital conversion circuit. By performing such control, the number of effective bits of the analog / digital conversion circuit can be utilized to the maximum, so that occurrence of a quantization error can be suppressed.

On the other hand, when the peak-to-peak value in the predetermined period reaches its maximum value,
The digital conversion circuit is controlled to increase the reference voltage. By performing such control, it is possible to avoid a problem that the input range of the analog / digital conversion circuit for the analog signal is too narrow and the peak-to-peak value overflows.

Further, in addition to the above configuration, the analog /
The receiving device may have an automatic gain control circuit before the digital conversion circuit. With such a configuration, in order to maintain the magnitude of the analog signal at a predetermined level, as an auxiliary measure when the dynamic range of the automatic gain control circuit is inadequate, the analog / digital signal is used.
The control of the reference voltage in the digital conversion circuit is performed. Therefore, since a double countermeasure is taken against the fluctuation of the analog signal, it is possible to ensure a good reception state.

On the other hand, an output signal of the automatic gain control circuit is compared with the reference voltage by using an automatic gain control circuit for making the received RF signal a predetermined level and a plurality of comparators having different reference voltages. An analog / digital conversion circuit for performing binary coding of the RF signal in accordance with a comparison output, wherein a digital signal output from the analog / digital conversion circuit is detected, and the analog signal is output according to the magnitude of the digital signal. A configuration may be adopted in which the reference voltage in the / digital conversion circuit is varied.

As described above, the analog / digital conversion circuit has a circuit configuration of a so-called parallel comparison system, so that the analog / digital conversion circuit (for example, a feedback comparison system or an integration system) can be operated in a shorter time than other analog / digital conversion systems. A conversion can be performed.

In the receiving apparatus having the above-mentioned configuration, a predetermined voltage is applied to both ends of a series connection circuit composed of a plurality of resistors, and a voltage extracted from a connection point between the resistors is used as the reference voltage. A circuit may be provided, and the reference voltage may be varied by controlling the magnitude of the predetermined voltage.

With this configuration, the reference voltages of the plurality of comparators can all be varied by merely varying the magnitude of the predetermined voltage, so that the input range of the analog / digital conversion circuit conversion can be reduced. Switching can be performed very easily.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a receiving device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of an analog / digital conversion circuit 4;

FIG. 3 is a block diagram illustrating a configuration example of a peak-to-peak value detection circuit 6.

FIG. 4 is a waveform chart showing an example of an analog signal input to the receiving device according to the present invention.

[Explanation of symbols]

Reference Signs List 1 antenna 2 filter 3 automatic gain control circuit 4 analog / digital conversion circuit 40 priority encoder circuit 5 detection circuit 6 peak-to-peak value detection circuit 60 p _max latch circuit 61 p _min latch circuit 62 subtractor 7 reference selection circuit

Claims (7)

[Claims] 1. A received analog signal is compared with a reference voltage, and the analog signal is output according to the comparison output.
A receiver having an analog / digital conversion circuit for performing binary coding and a detection circuit for demodulating a digital signal output from the analog / digital conversion circuit, wherein the reference voltage in the analog / digital conversion circuit is varied. A receiving device comprising means. 2. A received analog signal is compared with a reference voltage.
A receiving device comprising: an analog / digital conversion circuit for performing hexadecimal encoding; and a detection circuit for demodulating a digital signal output from the analog / digital conversion circuit, wherein a peak-to-peak value of the digital signal is detected. A receiving device, wherein the reference voltage in the analog / digital conversion circuit is varied according to the size. 3. When the peak-to-peak value is always lower than a predetermined value in a predetermined period, the analog / peak signal is output.
The receiving device according to claim 2, wherein the reference voltage in the digital conversion circuit is reduced. 4. The receiving apparatus according to claim 2, wherein when the peak-to-peak value reaches its maximum value, the reference voltage in the analog / digital conversion circuit is increased. . 5. An apparatus according to claim 2, further comprising an automatic gain control circuit preceding said analog / digital conversion circuit.
The receiving device according to claim 4. 6. An automatic gain control circuit for converting a received RF signal to a predetermined level, and a plurality of comparators having different reference voltages, comparing an output signal of the automatic gain control circuit with the reference voltage. Analog / binary encoding of the RF signal according to the comparison output;
A digital conversion circuit, wherein a digital signal output from the analog / digital conversion circuit is detected, and the reference voltage in the analog / digital conversion circuit is varied according to the magnitude of the digital signal. Receiving device. 7. The analog / digital conversion circuit, wherein a predetermined voltage is applied to both ends of a series connection circuit composed of a plurality of resistors, and a voltage extracted from a connection point between the resistors is used as the reference voltage. The receiving device according to claim 6, wherein the reference voltage is varied by controlling a magnitude of the voltage.