[go: up one dir, main page]

JP2001274640A - Amplifier circuit - Google Patents

Amplifier circuit

Info

Publication number
JP2001274640A
JP2001274640A JP2000082462A JP2000082462A JP2001274640A JP 2001274640 A JP2001274640 A JP 2001274640A JP 2000082462 A JP2000082462 A JP 2000082462A JP 2000082462 A JP2000082462 A JP 2000082462A JP 2001274640 A JP2001274640 A JP 2001274640A
Authority
JP
Japan
Prior art keywords
transistor
current source
constant current
amplifier
amplifier circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000082462A
Other languages
Japanese (ja)
Inventor
Yuji Yamamoto
有二 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2000082462A priority Critical patent/JP2001274640A/en
Publication of JP2001274640A publication Critical patent/JP2001274640A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an amplifier circuit with a small resistance and a small capacitance, which has a small area and can reduce an offset. SOLUTION: A differential amplifier circuit consists of transistors(TRs) M2, M1 whose gate electrodes are used for positive and negative input terminals, resistive elements RN1, RP1, and a constant current source I1. An amplifier having bipolar inputs and outputs amplifies outputs of the differential amplifier circuit to provide the amplified outputs to positive and negative output terminals. An amplifier circuit consisting of a resistor RP3, TRs M3, M4 and a constant current source I2 and a capacitor CP having an equivalent capacitance multiplied by a multiple of a gain eliminates an AC component of signals from the positive and negative output terminals and an amplifier circuit consisting of a resistor RN3, TRs M8, M7 and a constant current source I4 and a capacitor CN having an equivalent capacitance multiplied by a multiple of a gain eliminates the AC component of the signals from the positive and negative output terminals. The signals whose AC component is eliminated are negatively fed back to the inputs of the amplifier with a differential amplifier circuit consisting of TRs M5, M6 and a constant current source I3. The negative feedback can reduce the offset of the amplifier. Since each equivalent capacitor is multiplied by a gain with the mirror effect, a smaller resistance and a smaller capacitance are enough to realize the same time constant.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本願発明は増幅回路に関し、
特に小型で時定数の大きな増幅回路に関する。
The present invention relates to an amplifier circuit,
In particular, it relates to an amplifier circuit having a small size and a large time constant.

【0002】[0002]

【従来の技術】先ず最初に本発明の背景を明らかにする
ために,従来用いられる増幅回路の例を図5に示す。こ
の回路は,例えば,T.H.Hu and P.R.Gr
ay,”A Monolithic 480Mb/s
Parallel AGC/Decision/Clo
ck−Recovery Circuit in 1.
2um CMOS”,IEEE J.Solid−St
ate Circuit,vol. SC−28,p
p.1314−1320,Dec.1993 等に見る
ことが出来る。
2. Description of the Related Art First, in order to clarify the background of the present invention, an example of a conventional amplifier circuit is shown in FIG. This circuit is described in, for example, TH Hu and P. R. Gr
ay, "A Monolithic 480 Mb / s
Parallel AGC / Decision / Clo
ck-Recovery Circuit in 1.
2um CMOS ", IEEE J. Solid-St
ate Circuit, vol. SC-28, p
p. 1314-1320, Dec. 1993, etc.

【0003】図5の回路は,トランジスタM1は,ゲー
ト電極を負入力端子に接続しドレイン電極を負荷抵抗要
素RN1の一端と増幅器の正入力とトランジスタM6の
ドレイン電極に共通に接続しソース電極をトランジスタ
M2のソース電極と電流源I1の一端に共通に接続す
る。トランジスタM2は,ゲート電極を正入力端子に接
続しドレイン電極を負荷抵抗要素RP1の一端と前記増
幅器の負入力とトランジスタM5のドレイン電極に共通
に接続する。定電流源I1の他端は基準電位に接続す
る。負荷抵抗RN1の他端は,電源に接続する。負荷抵
抗RP1の他端は電源に接続する。増幅器は,正負入力
の電位差を増幅して正負出力端子に出力する。抵抗RP
3は,一端を前記増幅器の負出力に接続し他端をトラン
ジスタM5のゲート電極と容量CAの一端に共通に接続
する。トランジスタM5のソース電極は,トランジスタ
M6のソース電極と定電流源I3の一端に共通に接続す
る。定電流源I3の他端は基準電位に接続する。抵抗R
N3は,一端を前記増幅器の正出力に接続し他端をトラ
ンジスタM6のゲート電極と容量CAの一端に共通に接
続する。
In the circuit shown in FIG. 5, a transistor M1 has a gate electrode connected to a negative input terminal, a drain electrode commonly connected to one end of a load resistance element RN1, a positive input of an amplifier, and a drain electrode of a transistor M6, and a source electrode connected thereto. The source electrode of the transistor M2 and one end of the current source I1 are commonly connected. The transistor M2 has a gate electrode connected to the positive input terminal and a drain electrode commonly connected to one end of the load resistance element RP1, the negative input of the amplifier, and the drain electrode of the transistor M5. The other end of the constant current source I1 is connected to a reference potential. The other end of the load resistor RN1 is connected to a power supply. The other end of the load resistor RP1 is connected to a power supply. The amplifier amplifies the potential difference between the positive and negative inputs and outputs it to the positive and negative output terminals. Resistance RP
3 has one end connected to the negative output of the amplifier and the other end commonly connected to the gate electrode of the transistor M5 and one end of the capacitor CA. The source electrode of the transistor M5 is commonly connected to the source electrode of the transistor M6 and one end of the constant current source I3. The other end of the constant current source I3 is connected to a reference potential. Resistance R
N3 has one end connected to the positive output of the amplifier and the other end commonly connected to the gate electrode of the transistor M6 and one end of the capacitor CA.

【0004】トランジスタM1,M2,抵抗RN1,R
P1,定電流源I1からなる回路は,所謂差動増幅器
で,正負入力の電圧差が増幅されて抵抗RN1,RP1
の電位差となる。増幅率は,トランジスタM1,M2の
gmと抵抗RN1,RP1の抵抗値の積で表すこことが
できる。抵抗RN1,RP1の電位差を次段の増幅器で
増幅して正負の出力を得る。
[0004] Transistors M1, M2, resistors RN1, R
The circuit composed of P1 and the constant current source I1 is a so-called differential amplifier in which the voltage difference between the positive and negative inputs is amplified and the resistors RN1 and RP1
Of the potential difference. The amplification factor can be represented by a product of gm of the transistors M1 and M2 and resistance values of the resistors RN1 and RP1. The potential difference between the resistors RN1 and RP1 is amplified by the next-stage amplifier to obtain positive and negative outputs.

【0005】一般に増幅器は,入力が0でも出力は正確
には0にはならず,直流のオフセット電圧が出力され
る。抵抗RP3,RN3,容量CA,トランジスタM
5,M6,定電流源I3から成る回路は,所謂オフセッ
トキャンセル回路と呼ばれ,前記抵抗RN1とRP1
と,トランジスタM5,M6と定電流源I3で,差動増
幅回路を構成し,正負出力の電位差から,抵抗RP3,
RN3と容量CAで交流成分を除去し,トランジスタM
5,M6を通して,直流成分のみを前記増幅器の入力に
負帰還する。正負出力に直流出力が発生しても,直流成
分を減らす方向に負帰還がかかる。従って,入力が0の
ときの直流出力即ちオフセットが低減できる。
In general, even if the input is 0, the output of the amplifier is not exactly 0, and a DC offset voltage is output. Resistance RP3, RN3, capacitance CA, transistor M
5, M6, a constant current source I3 is called a so-called offset cancel circuit, and the resistors RN1 and RP1
, Transistors M5 and M6, and a constant current source I3 to form a differential amplifier circuit.
The AC component is removed by the RN3 and the capacitor CA, and the transistor M
5 and M6, only the DC component is negatively fed back to the input of the amplifier. Even if a DC output occurs in the positive and negative outputs, negative feedback is applied in a direction to reduce the DC component. Therefore, the DC output when the input is 0, that is, the offset can be reduced.

【0006】[0006]

【発明が解決しようとする課題】オフセットは,直流成
分であり,増幅しようとする信号成分は交流である。オ
フセットキャンセル回路では,信号成分になるべく影響
を与えないように,なるべく直流だけキャンセルするこ
とが要求される。正負の出力から直流成分のみを取り出
そうとすると,抵抗RP3,RN3と容量CAの素子値
を大きくし,抵抗値と容量値の積で決まる時定数を大き
くする必要がある。抵抗値や容量値を大きくすると,特
に集積回路では,占有するチップの面積が増大するとい
う問題があった。
The offset is a DC component, and the signal component to be amplified is an AC. In the offset cancel circuit, it is required to cancel DC as much as possible so as not to affect the signal component as much as possible. In order to extract only the DC component from the positive and negative outputs, it is necessary to increase the element values of the resistors RP3, RN3 and the capacitor CA, and to increase the time constant determined by the product of the resistance value and the capacitance value. Increasing the resistance value or the capacitance value has a problem that an occupied chip area increases, especially in an integrated circuit.

【0007】[0007]

【課題を解決する為の手段】従来の技術の課題を解決す
るために,本発明では,図1に示す手段を講じた。トラ
ンジスタM4のゲート電極を入力とし,トランジスタM
4を駆動段とし,トランジスタM3を負荷段とし,トラ
ンジスタM4のドレイン電極を出力とする増幅回路の入
出力に容量CPを接続した。トランジスタM3,M4の
ドレイン電流の合計が,定電流源I2を流れる。トラン
ジスタM4のゲート電極が変化すると,トランジスタM
4のドレイン電流が変化する,トランジスタM3,M4
を流れる電流の合計は,定電流源I2の電流なので,変
化しないため,トランジスタM4のドレイン電流が減る
とすると,該電流の減少分トランジスタM3のドレイン
電流は増加する。トランジスタM3のドレイン電流が変
動すると,トランジスタM3のゲート,ソース間電圧が
変動する。即ち,トランジスタM4,M3と定電流源I
2で,トランジスタM4のゲート電極を入力,トランジ
スタM4のドレイン電極を出力とした増幅回路を構成し
ている。容量CPは,トランジスタM4のゲート電極と
ドレイン電極の間に接続しているので,増幅回路の入力
と出力の間に容量CPが接続している。増幅回路の入力
と出力の間に接続された容量は,所謂ミラー容量と呼ば
れる効果がある。ミラー容量は,入力から見た等価容量
値が,元の容量値のゲイン倍される。従って,抵抗RP
3の一端から見た時定数は,容量CPの容量値×抵抗R
P3の抵抗値×(トランジスタM4,M3の増幅回路の
ゲイン)となり,増幅回路が無い場合に比べて等価的に
ゲイン倍の時定数を得ることが出来る。従って同じ時定
数を得るためには,小さい容量値又は小さい抵抗値とす
ることができる。
Means for Solving the Problems In order to solve the problems of the prior art, the present invention employs the means shown in FIG. The gate electrode of the transistor M4 is input and the transistor M4
4 as a drive stage, a transistor M3 as a load stage, and a capacitor CP connected to an input / output of an amplifier circuit that outputs a drain electrode of the transistor M4. The sum of the drain currents of the transistors M3 and M4 flows through the constant current source I2. When the gate electrode of the transistor M4 changes, the transistor M4
Transistors M3 and M4 in which the drain current of transistor 4 changes
Is the current of the constant current source I2 and does not change. Therefore, if the drain current of the transistor M4 decreases, the drain current of the transistor M3 increases by the decrease in the current. When the drain current of the transistor M3 changes, the voltage between the gate and the source of the transistor M3 changes. That is, the transistors M4 and M3 and the constant current source I
2 constitutes an amplifier circuit in which the gate electrode of the transistor M4 is input and the drain electrode of the transistor M4 is output. Since the capacitance CP is connected between the gate electrode and the drain electrode of the transistor M4, the capacitance CP is connected between the input and the output of the amplifier circuit. The capacitance connected between the input and the output of the amplifier circuit has an effect called a so-called Miller capacitance. The Miller capacitance is obtained by multiplying the equivalent capacitance value seen from the input by the gain of the original capacitance value. Therefore, the resistance RP
The time constant viewed from one end of No. 3 is the capacitance value of the capacitance CP × the resistance R
The resistance value of P3 × (the gain of the amplifier circuit of the transistors M4 and M3) is obtained, and a time constant twice as large as the gain without the amplifier circuit can be obtained. Therefore, in order to obtain the same time constant, a small capacitance value or a small resistance value can be used.

【0008】図1は,差動増幅回路なので,抵抗RN
3,トランジスタM7,M8,定電流源I4の機能は,
各々対称になっている抵抗RP3,トランジスタM4,
M3,定電流源I2と同じ機能をする。
FIG. 1 shows a differential amplifier circuit,
3. The functions of the transistors M7 and M8 and the constant current source I4 are as follows.
The symmetrical resistors RP3, transistor M4,
M3, the same function as the constant current source I2.

【0009】[0009]

【発明の実施の形態】図1に,本発明の回路構成を示
す。
FIG. 1 shows a circuit configuration of the present invention.

【0010】ゲート電極を正負の入力端子とするトラン
ジスタM2,M1,抵抗要素RN1,RP1,定電流源
I1で差動増幅回路を構成する。該差動増幅回路の出力
を,正負の入出力を持つ増幅回路で増幅し正負の出力端
子に出力する。正負の出力端子から,抵抗RP3と,ト
ランジスタM3,M4,定電流源I2の増幅回路でゲイ
ン倍した等価容量値を持つ容量CPとで交流分を除去
し,抵抗RN3と,トランジスタM8,M7,定電流源
I4の増幅回路でゲイン倍した等価容量値を持つ容量C
Nとで交流分を除去する。交流分を除去した直流分を,
トランジスタM5,M6,定電流源I3の差動回路で,
前記増幅器の入力に負帰還し,オフセットを低減する。
A differential amplifier circuit is composed of transistors M2 and M1, whose gate electrodes are positive and negative input terminals, resistance elements RN1 and RP1, and a constant current source I1. The output of the differential amplifier circuit is amplified by an amplifier circuit having positive and negative inputs and outputs and output to positive and negative output terminals. An AC component is removed from the positive and negative output terminals by a resistor RP3 and a capacitor CP having an equivalent capacitance value multiplied by a gain in an amplifier circuit of the transistors M3, M4 and the constant current source I2, thereby removing a resistor RN3, transistors M8, M7, A capacitor C having an equivalent capacitance value multiplied by a gain in the amplifier circuit of the constant current source I4
Remove the alternating current with N. The DC component with the AC component removed is
A differential circuit of transistors M5, M6 and constant current source I3,
Negative feedback is provided to the input of the amplifier to reduce offset.

【0011】[0011]

【実施例】図1に,本発明の回路構成を示す。トランジ
スタM1は,ゲート電極を負入力端子に接続しドレイン
電極を負荷抵抗要素RN1の一端と増幅器の正入力とト
ランジスタM6のドレイン電極に共通に接続し,ソース
電極をトランジスタM2のソース電極と電流源I1の一
端に共通に接続する。トランジスタM2は,ゲート電極
を正入力端子に接続しドレイン電極を負荷抵抗要素RP
1の一端と前記増幅器の負入力とトランジスタM5のド
レイン電極に共通に接続する。定電流源I1は,他端を
基準電位に接続する。負荷抵抗要素RN1は,他端を電
源に接続する。負荷抵抗要素RP1は,他端を電源に接
続する。
FIG. 1 shows a circuit configuration of the present invention. The transistor M1 has a gate electrode connected to the negative input terminal, a drain electrode commonly connected to one end of the load resistance element RN1, the positive input of the amplifier and the drain electrode of the transistor M6, and a source electrode connected to the source electrode of the transistor M2 and the current source. Commonly connected to one end of I1. The transistor M2 has a gate electrode connected to the positive input terminal and a drain electrode connected to the load resistance element RP.
1 and the negative input of the amplifier and the drain electrode of the transistor M5. The other end of the constant current source I1 is connected to the reference potential. The other end of the load resistance element RN1 is connected to a power supply. The other end of the load resistance element RP1 is connected to a power supply.

【0012】前記増幅器は,正負入力の電位差を増幅し
て正負出力端子に出力する。抵抗RP3は,一端を前記
増幅器の負出力に接続し他端をトランジスタM5のゲー
ト電極とトランジスタM4のゲート電極と容量CPの一
端に共通に接続する。トランジスタM4は,ドレイン電
極を容量CPの他端とトランジスタM3のドレイン電極
とゲート電極と定電流源I2の他端に共通に接続しソー
ス電極を電源に接続する。トランジスタM3は,ソース
電極を電源に接続する。定電流源I2は,他端を基準電
位に接続する。トランジスタM5は,ソース電極をトラ
ンジスタM6のソース電極と定電流源I3の一端に共通
に接続する。定電流源I3は,他端を基準電位に接す
る。
The amplifier amplifies the potential difference between the positive and negative inputs and outputs it to the positive and negative output terminals. The resistor RP3 has one end connected to the negative output of the amplifier and the other end commonly connected to the gate electrode of the transistor M5, the gate electrode of the transistor M4, and one end of the capacitor CP. The transistor M4 has a drain electrode commonly connected to the other end of the capacitor CP, the drain electrode and gate electrode of the transistor M3, and the other end of the constant current source I2, and a source electrode connected to a power supply. The transistor M3 has a source electrode connected to a power supply. The other end of the constant current source I2 is connected to the reference potential. The transistor M5 has a source electrode commonly connected to the source electrode of the transistor M6 and one end of the constant current source I3. The other end of the constant current source I3 is in contact with the reference potential.

【0013】抵抗RN3は,一端を前記増幅器の正出力
に接続し他端をトランジスタM6のゲート電極とトラン
ジスタM7のゲート電極と容量CNの一端に共通に接続
する。トランジスタM7は,ドレイン電極を容量CNの
他端とトランジスタM8のドレイン電極とゲート電極と
定電流源I4の他端に共通に接続しソース電極を電源に
接続する。トランジスタM8は,ソース電極を電源に接
続する。定電流源I4は,他端を基準電位に接続する。
The resistor RN3 has one end connected to the positive output of the amplifier and the other end commonly connected to the gate electrode of the transistor M6, the gate electrode of the transistor M7, and one end of the capacitor CN. The transistor M7 has a drain electrode commonly connected to the other end of the capacitor CN, the drain electrode and gate electrode of the transistor M8, and the other end of the constant current source I4, and a source electrode connected to a power supply. The transistor M8 has a source electrode connected to a power supply. The other end of the constant current source I4 is connected to the reference potential.

【0014】トランジスタM1,M2,抵抗RN1,R
P1,定電流源I1で構成した回路は,所謂差動増幅回
路で,正負の入力電位差を,抵抗RN1,RP1の両端
の電圧の電位差としてに出力する。増幅率kは,トラン
ジスタM1,M2のgm×抵抗値RP1,RN1とな
る。同様の構成をトランジスタM5,M6,抵抗RN
1,RP1,定電流源I3でも用いている。トランジス
タM5,M6のゲート電極の電圧の電位差は,抵抗RN
1,RP1の両端の電圧の電位差として出力する。増幅
率hは,トランジスタM5,M6のgm×抵抗値RP
1,RN1となる。抵抗RN1,RP1は,共用してい
るので,抵抗RN1,RP1の両端の電圧の電位差は,
正負の入力電圧を増幅したものとトランジスタM5,6
のゲート電極の電位差を増幅したものを加算したものに
なる。
Transistors M1, M2, resistors RN1, R
The circuit constituted by P1 and the constant current source I1 is a so-called differential amplifier circuit, and outputs a positive / negative input potential difference as a potential difference between voltages across the resistors RN1 and RP1. The amplification factor k is equal to gm of the transistors M1 and M2 × resistance values RP1 and RN1. The same configuration is used for transistors M5, M6, and resistor RN.
1, RP1 and constant current source I3. The potential difference between the voltages of the gate electrodes of the transistors M5 and M6 is equal to the resistance RN.
1, and output as a potential difference between the voltages at both ends of RP1. The amplification factor h is gm × resistance value RP of the transistors M5 and M6.
1, RN1. Since the resistors RN1 and RP1 are shared, the potential difference between the voltages at both ends of the resistors RN1 and RP1 is
Amplified positive and negative input voltages and transistors M5 and M6
Are obtained by amplifying the amplified potential difference of the gate electrode.

【0015】図1の増幅器は,各々抵抗RN1,RP1
の一端に接続した正負の入力を,増幅率Gで増幅して正
負の出力としている。正負出力の電位差が大きくなると
(正出力電圧が大きくなり,負出力が小さくなる)と,
トランジスタM6のゲート電極の電圧が上がり抵抗RN
1に流れる電流が増す,トランジスタM5のゲート電極
の電圧が下がり抵抗RP1に流れる電流が減る。増幅器
の正入力に接続してる抵抗RN1の一端の電圧は下がろ
うとし,増幅器の負入力に接続している抵抗RP1の一
端の電圧は上がろうとする。即ち,増幅器の出力の電位
差が大きくなると,出力の電位差を小さくするように負
帰還が掛かる。
The amplifier shown in FIG. 1 has resistors RN1 and RP1 respectively.
The positive and negative inputs connected to one end are amplified by an amplification factor G to produce positive and negative outputs. When the potential difference between the positive and negative outputs increases (the positive output voltage increases and the negative output decreases),
The voltage of the gate electrode of the transistor M6 rises and the resistance RN
1 increases, the voltage of the gate electrode of the transistor M5 decreases, and the current flowing through the resistor RP1 decreases. The voltage at one end of the resistor RN1 connected to the positive input of the amplifier tends to decrease, and the voltage at one end of the resistor RP1 connected to the negative input of the amplifier tends to increase. That is, when the potential difference of the output of the amplifier increases, negative feedback is applied so as to reduce the potential difference of the output.

【0016】抵抗RP3,容量CP,トランジスタM
3,M4,定電流源I2からなる回路は,出力から信号
成分以外の直流成分を取り出すフィルタの機能を有して
いる。容量CPは,トランジスタM4のゲート電極を入
力とし,トランジスタM4を駆動段とし,トランジスタ
M3を負荷段とし,トランジスタM4のドレイン電極を
出力とする増幅回路の入出力に接続した。トランジスタ
M3,M4のドレイン電流の合計が,定電流源I2を流
れる。トランジスタM4のゲート電極が変化すると,ト
ランジスタM4のドレイン電流が変化する,トランジス
タM3,M4を流れる電流の合計は,定電流源I2の電
流なので,変化しない。トランジスタM4のドレイン電
流が減るとすると,該電流の減少分トランジスタM3の
ドレイン電流は増加する。トランジスタM3のドレイン
電流が変動すると,トランジスタM3のゲート,ソース
間電圧が変動する。即ち,トランジスタM4,M3と定
電流源I2で,トランジスタM4のゲート電極を入力,
トランジスタM4のドレイン電極を出力とした増幅回路
を構成している。増幅率は,トランジスタM4のgm/
トランジスタM3のgmとなる。
A resistor RP3, a capacitance CP, a transistor M
The circuit composed of 3, M4 and the constant current source I2 has a function of a filter for extracting a DC component other than a signal component from the output. The capacitor CP is connected to the input / output of an amplifier circuit that receives the gate electrode of the transistor M4 as an input, uses the transistor M4 as a driving stage, uses the transistor M3 as a load stage, and uses the drain electrode of the transistor M4 as an output. The sum of the drain currents of the transistors M3 and M4 flows through the constant current source I2. When the gate electrode of the transistor M4 changes, the drain current of the transistor M4 changes. The sum of the currents flowing through the transistors M3 and M4 does not change because the current is the constant current source I2. If the drain current of the transistor M4 decreases, the drain current of the transistor M3 increases by the decrease in the current. When the drain current of the transistor M3 changes, the voltage between the gate and the source of the transistor M3 changes. That is, the transistors M4 and M3 and the constant current source I2 input the gate electrode of the transistor M4,
An amplifier circuit using the drain electrode of the transistor M4 as an output is configured. The amplification factor is gm / g of transistor M4.
Gm of the transistor M3.

【0017】容量CPは,トランジスタM4のゲート電
極とドレイン電極の間に接続しているので,言い換える
と,増幅回路の入力と出力の間に容量CPが接続してい
る。増幅回路の入力と出力の間に接続された容量は,所
謂ミラー容量と呼ばれる効果がある。ミラー容量は,入
力から見た等価容量値が,元の容量値のゲイン倍され
る。従って,抵抗RP3の一端から見た時定数は,容量
CPの容量値×抵抗RP3の抵抗値×(トランジスタM
4,M3の増幅回路のゲイン)となり,増幅回路が無い
場合に比べて等価的にゲイン倍の時定数を得ることが出
来る。従って同じ時定数を得るためには,小さい容量値
又は小さい抵抗値とすることができる。
Since the capacitance CP is connected between the gate electrode and the drain electrode of the transistor M4, in other words, the capacitance CP is connected between the input and the output of the amplifier circuit. The capacitance connected between the input and the output of the amplifier circuit has an effect called a so-called Miller capacitance. The Miller capacitance is obtained by multiplying the equivalent capacitance value seen from the input by the gain of the original capacitance value. Therefore, the time constant viewed from one end of the resistor RP3 is the capacitance value of the capacitor CP × the resistance value of the resistor RP3 × (transistor M
4, the gain of the amplifier circuit of M3), and a time constant twice the gain can be equivalently obtained as compared with the case where there is no amplifier circuit. Therefore, in order to obtain the same time constant, a small capacitance value or a small resistance value can be used.

【0018】抵抗RN3,容量CN,トランジスタM
8,M7,定電流源I4は,抵抗RP3,容量CP,ト
ランジスタM3,M4,定電流源I2と対称で同一機能
を果たす。以下,説明は,片方のみ行う。
Resistance RN3, capacitance CN, transistor M
8, M7 and the constant current source I4 are symmetrical to the resistor RP3, the capacitance CP, the transistors M3 and M4, and the constant current source I2, and perform the same function. Hereinafter, only one of them will be described.

【0019】抵抗RP3,容量CP,トランジスタM
3,M4,定電流源I2からなる回路の時定数(1/
ω)は, (1/ω)=RP3*CP*(トランジスタM4のgm
/トランジスタM3のgm) トランジスタM1,M2,抵抗RN1,RP1,定電流
源I1で構成した回路の増幅率k,トランジスタM5,
M6,抵抗RN1,RP1,定電流源I3で構成した回
路の増幅率h,増幅器の増幅率Gとすると,図1の回路
を等価回路で表現すると図2にしめすようになる。図2
で,offは,増幅器のオフセットを表している。
Resistance RP3, capacitance CP, transistor M
3, M4, and the time constant (1 /
ω) is (1 / ω) = RP3 * CP * (gm of transistor M4
/ Gm of transistor M3) Amplification factor k of a circuit composed of transistors M1, M2, resistors RN1, RP1, and constant current source I1, transistor M5
Assuming that the amplification factor h of the circuit constituted by M6, the resistors RN1, RP1, and the constant current source I3 and the amplification factor G of the amplifier are shown in FIG. 2, the circuit of FIG. 1 is represented by an equivalent circuit. FIG.
And off represents the offset of the amplifier.

【0020】図1の等価回路の特性を図3に示す。図3
の左は,入力inと出力outの関係を示している。入
力周波数の小さいところではゲインが小さい。図3右
は,オフセットoffと出力の関係をしめしている。周
波数が高いとオフセットoffはそのまま出力される
が,周波数が低いとオフセットoffは,1/(1+G
h)に低減している。入力inには,信号成分が入力さ
れる。なるべく低い信号成分まで増幅するためには,時
定数(1/ω)を大きくする必要がある。時定数を大き
くするためには抵抗と容量を大きくすればよいが,集積
回路内では,抵抗と容量を大きくすると占有面積が増大
して好ましくない。本発明では,時定数を大きくするの
に,ミラー容量を作成する回路のゲイン(トランジスタ
M4のgm/トランジスタM3のgm)を大きくすれば
よい。
FIG. 3 shows the characteristics of the equivalent circuit of FIG. FIG.
The left of indicates the relationship between the input in and the output out. The gain is small where the input frequency is small. FIG. 3R shows the relationship between the offset off and the output. When the frequency is high, the offset off is output as it is, but when the frequency is low, the offset off is 1 / (1 + G
h). A signal component is input to the input in. In order to amplify as low a signal component as possible, it is necessary to increase the time constant (1 / ω). To increase the time constant, the resistance and capacitance may be increased. However, in an integrated circuit, increasing the resistance and capacitance is not preferable because the occupied area increases. In the present invention, in order to increase the time constant, the gain (gm of transistor M4 / gm of transistor M3) of the circuit for creating the Miller capacitance may be increased.

【0021】図4は,図1の回路で,トランジスタM
1,M2,抵抗RN1,RP1,定電流源I1で構成し
た初段の差動増幅回路を,トランジスタM1,M2,M
1A,M2A,M1B,M2B,抵抗要素RN1,RP
1,定電流源I1で構成したものである。抵抗要素RP
1,RN1は,ゲート電極とドレイン電極を共通に接続
した所謂ダイオード接続のトランジスタで構成してい
る。M2AとM2B,M1AとM1Bは,ゲート電極が
共通に接続した所謂カレントミラー回路を構成してい
る。ゲート電極が共通に接続されているので,トランジ
スタM2AとトランジスタM2B,トランジスタM1A
とトランジスタM1Bを流れる電流は,トランジスタの
サイズ比に従う。図4の回路の特性は,同様に図2,図
3で表現できる。
FIG. 4 shows the circuit of FIG.
, M2, resistors RN1, RP1, and a constant current source I1 are connected to transistors M1, M2, M
1A, M2A, M1B, M2B, resistance elements RN1, RP
1, a constant current source I1. Resistance element RP
1, RN1 is constituted by a so-called diode-connected transistor in which a gate electrode and a drain electrode are commonly connected. M2A and M2B and M1A and M1B constitute a so-called current mirror circuit in which gate electrodes are connected in common. Since the gate electrodes are commonly connected, the transistors M2A and M2B and the transistor M1A
And the current flowing through the transistor M1B depends on the size ratio of the transistors. The characteristics of the circuit in FIG. 4 can be similarly expressed in FIGS.

【0022】図4の回路では,入力トランジスタの極性
を図1逆の極性にしている。トランジスタM5,M6,
定電流源I3の差動回路を使用し,抵抗要素RP1,R
N1をダイオード接続したトランジスタで構成すると,
トランジスタM5,M6とトランジスタRN1,RP1
の極性は,逆にする必要がある。図1での構成では,ト
ランジスタRN1,RP1の極性の逆にトランジスタM
1,M2の極性をもするしかなく選択の余地がない。図
4の回路構成では,トランジスタRP1,RN1の極性
と入力トランジスタのを同じにできる。
In the circuit shown in FIG. 4, the polarity of the input transistor is reversed from that shown in FIG. Transistors M5, M6,
Using the differential circuit of the constant current source I3, the resistance elements RP1, R
If N1 is composed of a diode-connected transistor,
Transistors M5 and M6 and transistors RN1 and RP1
Must be reversed. In the configuration in FIG. 1, the polarity of the transistors RN1 and RP1
There is no choice but to have polarities of 1 and M2. In the circuit configuration of FIG. 4, the polarity of the transistors RP1 and RN1 and the input transistor can be made the same.

【0023】図6の回路は,図1,図4,図5の回路内
の増幅器の一例である。増幅器の構成方法は無数にあ
り,図1,図4の回路において,使用できる増幅器の回
路構成を特に制限はしなくても,本発明の効果を制限す
るものではない。
The circuit of FIG. 6 is an example of the amplifier in the circuits of FIGS. 1, 4 and 5. There are countless methods for configuring the amplifier, and the circuit of FIGS. 1 and 4 does not limit the effects of the present invention even if the circuit configuration of the amplifier that can be used is not particularly limited.

【0024】図6の回路は,2段縦列接続の差動増幅回
路で,増幅器を構成している。初段の差動増幅回路は,
トランジスタM10,M11,抵抗RP4,RN4,定
電流源I5で構成した一般的なものである。2段目の差
動増幅回路も,トランジスタM12,M13M14,M
15と定電流源I6で構成した一般的なものである。2
段目の差動増幅回路の負荷をトランジスタM14,M1
5で構成したことが,この増幅器の特徴である。図1,
図4の回路の増幅器として図6の回路を使用すると,図
1,図4の回路のミラー容量用トランジスタM4,M7
の極性と,図6のM15,M16の極性を等しく出来
る。極性が等しいので,すべて電源基準でゲート電圧を
印加し,トランジスタM4,M7,M15,M16のゲ
ートソース間電圧を等しくできる。従って,電源電圧が
変化しても,トランジスタM4,M7のゲートソース間
電圧は変化しない特徴がある。ゲートソース間電圧が一
定であると,トランジスタM4,M7を流れる電流も変
化しない。従って,定電流源I2,I4の電流値を電源
電圧で変える必要はないと言う効果がある。もちろん,
2段縦列接続の差動増幅回路ではなく,トランジスタM
12,M13,M14,M15,定電流源I6の一段の
差動増幅回路で増幅器を構成しても,電源電圧で定電流
源I2の電流値を変える必要が無いと言う効果は同様で
ある。
The circuit shown in FIG. 6 is a two-stage cascade-connected differential amplifier circuit, which constitutes an amplifier. The first stage differential amplifier circuit
This is a general configuration including transistors M10 and M11, resistors RP4 and RN4, and a constant current source I5. The second-stage differential amplifier circuit also includes transistors M12, M13M14, M
15 and a general current source I6. 2
The load of the differential amplifier circuit of the stage is changed by transistors M14 and M1.
5 is a characteristic of this amplifier. Figure 1
When the circuit of FIG. 6 is used as the amplifier of the circuit of FIG. 4, the transistors M4 and M7 for the mirror capacitance of the circuits of FIGS.
And the polarities of M15 and M16 in FIG. 6 can be made equal. Since the polarities are the same, a gate voltage is applied on the basis of the power source, and the gate-source voltages of the transistors M4, M7, M15 and M16 can be made equal. Therefore, even if the power supply voltage changes, the gate-source voltage of the transistors M4 and M7 does not change. When the gate-source voltage is constant, the current flowing through the transistors M4 and M7 does not change. Therefore, there is an effect that it is not necessary to change the current values of the constant current sources I2 and I4 with the power supply voltage. of course,
Instead of a two-stage cascaded differential amplifier circuit, a transistor M
Even if the amplifier is constituted by a single-stage differential amplifier circuit of 12, M13, M14, M15 and the constant current source I6, the effect that the current value of the constant current source I2 does not need to be changed by the power supply voltage is the same.

【0025】なお,図1,図4ですべてのトランジスタ
の極性を入れ替え,電源電圧の極性をいれかえても,回
路動作として等価になるのは,いうまでもない。
It is needless to say that the circuit operation is equivalent even if the polarities of all the transistors are exchanged in FIGS. 1 and 4 and the polarities of the power supply voltage are changed.

【0026】[0026]

【発明の効果】以上説明したごとく,トランジスタM
4,M3と定電流源I2で,トランジスタM4のゲート
電極を入力,トランジスタM4のドレイン電極を出力と
した増幅回路を構成している。容量CPは,トランジス
タM4のゲート電極とドレイン電極の間に接続している
ので,増幅回路の入力と出力の間に容量CPが接続して
いる。増幅回路の入力と出力の間に接続された容量は,
所謂ミラー容量と呼ばれる効果がある。ミラー容量は,
入力から見た等価容量値が,元の容量値のゲイン倍され
る。従って,抵抗RP3の一端から見た時定数は,容量
CPの容量値×抵抗RP3の抵抗値×(トランジスタM
4,M3の増幅回路のゲイン)となり,増幅回路が無い
場合に比べて等価的にゲイン倍の時定数を得ることが出
来る。従って同じ時定数を得るためには,小さい容量値
又は小さい抵抗値とすることができる。
As described above, the transistor M
4, M3 and the constant current source I2 constitute an amplifier circuit in which the gate electrode of the transistor M4 is input and the drain electrode of the transistor M4 is output. Since the capacitance CP is connected between the gate electrode and the drain electrode of the transistor M4, the capacitance CP is connected between the input and the output of the amplifier circuit. The capacitance connected between the input and output of the amplifier circuit is
There is an effect called a so-called mirror capacitance. The mirror capacity is
The equivalent capacitance value seen from the input is multiplied by the gain of the original capacitance value. Therefore, the time constant viewed from one end of the resistor RP3 is the capacitance value of the capacitor CP × the resistance value of the resistor RP3 × (transistor M
4, the gain of the amplifier circuit of M3), and a time constant twice the gain can be equivalently obtained as compared with the case where there is no amplifier circuit. Therefore, in order to obtain the same time constant, a small capacitance value or a small resistance value can be used.

【0027】トランジスタM4,トランジスタM3,定
電流源I2で構成したミラー容量用の回路のゲインは,
前述したごとく,トランジスタM4のgm/トランジス
タM3のgm,で表すことが出来る。トランジスタのg
mの比は,トランジスタのサイズと電流で容易に数倍の
比を得ることが出来るので,容量値や抵抗値を数分の1
にできる。
The gain of the circuit for the Miller capacitance constituted by the transistors M4, M3 and the constant current source I2 is:
As described above, gm of transistor M4 / gm of transistor M3 can be expressed. Transistor g
Since the ratio of m can easily be several times as large as the size and current of the transistor, the capacitance value and the resistance value can be reduced to a fraction.
Can be.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を示す回路図。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】本発明の実施例の特性図。FIG. 2 is a characteristic diagram of the embodiment of the present invention.

【図3】本発明の実施例の特性図。FIG. 3 is a characteristic diagram of the embodiment of the present invention.

【図4】本発明の実施例を示す回路図。FIG. 4 is a circuit diagram showing an embodiment of the present invention.

【図5】従来の技術による増幅回路。FIG. 5 is an amplifier circuit according to a conventional technique.

【図6】従来の技術による増幅器。FIG. 6 shows a conventional amplifier.

【符号の説明】[Explanation of symbols]

I1,I2,I3,I4,I5,I6 定電流源 M1,M2,M3,M4,M5,M6,M7,M8 ト
ランジスタ M1A,M1B,M2A,M2B トランジスタ M10,M11,M12,M13,M14,M15 ト
ランジスタ RP1,RN1,RP3,RN3,RP4,RN4 抵
抗 CP,CN,CA 容量
I1, I2, I3, I4, I5, I6 Constant current source M1, M2, M3, M4, M5, M6, M7, M8 Transistor M1A, M1B, M2A, M2B Transistor M10, M11, M12, M13, M14, M15 Transistor RP1, RN1, RP3, RN3, RP4, RN4 Resistance CP, CN, CA Capacity

フロントページの続き Fターム(参考) 5J066 AA01 AA12 CA13 CA92 FA20 HA09 HA17 HA19 HA25 HA29 KA05 KA25 MA13 MA21 ND01 ND11 ND22 ND23 PD02 TA01 TA03 5J090 AA01 AA12 CA13 CA92 DN02 FA20 HA09 HA17 HA19 HA25 HA29 HN06 KA05 KA25 MA13 MA21 MN01 NN11 TA01 TA03 5J091 AA01 AA12 CA13 CA92 FA20 HA09 HA17 HA19 HA25 HA29 KA05 KA25 MA13 MA21 TA01 TA03 Continued on the front page F term (reference) 5J066 AA01 AA12 CA13 CA92 FA20 HA09 HA17 HA19 HA25 HA29 KA05 KA25 MA13 MA21 ND01 ND11 ND22 ND23 PD02 TA01 TA03 5J090 AA01 AA12 CA13 CA92 DN02 FA20 HA09 HA17 HA19 HA25 HA29 HN06 KA05 TA01 TA03 5J091 AA01 AA12 CA13 CA92 FA20 HA09 HA17 HA19 HA25 HA29 KA05 KA25 MA13 MA21 TA01 TA03

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】ゲート電極を負入力端子に接続しドレイン
電極を負荷抵抗要素RN1の一端と増幅器の正入力とト
ランジスタM6のドレイン電極に共通に接続しソース電
極をトランジスタM2のソース電極と電流源I1の一端
に共通に接続したトランジスタM1と,ゲート電極を正
入力端子に接続しドレイン電極を負荷抵抗要素RP1の
一端と前記増幅器の負入力とトランジスタM5のドレイ
ン電極に共通に接続したトランジスタM2と,他端を基
準電位に接続した定電流源I1と,他端を電源に接続し
た負荷抵抗要素RN1と,他端を電源に接続した負荷抵
抗要素RP1と,正負入力の電位差を増幅して正負出力
端子に出力する前記増幅器と,一端を前記増幅器の負出
力に接続し他端をトランジスタM5のゲート電極とトラ
ンジスタM4のゲート電極と容量CPの一端に共通に接
続した抵抗RP3と,ドレイン電極を容量CPの他端と
トランジスタM3のドレイン電極とゲート電極と定電流
源I2の他端に共通に接続しソース電極を電源に接続し
たトランジスタM4と,ソース電極を電源に接続したト
ランジスタM3と,他端を基準電位に接続した定電流源
I2と,ソース電極をトランジスタM6のソース電極と
定電流源I3の一端に共通に接続したトランジスタM5
と,他端を基準電位に接続した定電流源I3と,一端を
前記増幅器の正出力に接続し他端をトランジスタM6の
ゲート電極とトランジスタM7のゲート電極と容量CN
の一端に共通に接続した抵抗RN3と,ドレイン電極を
容量CNの他端とトランジスタM8のドレイン電極とゲ
ート電極と定電流源I4の他端に共通に接続しソース電
極を電源に接続したトランジスタM7と,ソース電極を
電源に接続したトランジスタM8と,他端を基準電位に
接続した定電流源I4と,前記トランジスタM6とで構
成した増幅回路。
1. A gate electrode is connected to a negative input terminal, a drain electrode is commonly connected to one end of a load resistance element RN1, a positive input of an amplifier, and a drain electrode of a transistor M6, and a source electrode is connected to a source electrode of a transistor M2 and a current source. A transistor M1 commonly connected to one end of I1; a transistor M2 having a gate electrode connected to the positive input terminal and a drain electrode commonly connected to one end of the load resistance element RP1 and the negative input of the amplifier and the drain electrode of the transistor M5; , A constant current source I1 having the other end connected to the reference potential, a load resistance element RN1 having the other end connected to the power supply, and a load resistance element RP1 having the other end connected to the power supply. The amplifier for outputting to the output terminal, one end connected to the negative output of the amplifier, and the other end connected to the gate electrode of the transistor M5 and the gate of the transistor M4. A resistor RP3 commonly connected to the gate electrode and one end of the capacitor CP, and a drain electrode commonly connected to the other end of the capacitor CP, the drain electrode and the gate electrode of the transistor M3, and the other end of the constant current source I2, and the source electrode to the power supply , A transistor M3 whose source electrode is connected to a power supply, a constant current source I2 whose other end is connected to a reference potential, and a source electrode common to the source electrode of the transistor M6 and one end of the constant current source I3. Connected transistor M5
A constant current source I3 having the other end connected to the reference potential, one end connected to the positive output of the amplifier, and the other end connected to the gate electrode of the transistor M6, the gate electrode of the transistor M7, and the capacitor CN.
And a transistor M7 having a drain electrode commonly connected to the other end of the capacitor CN, the drain electrode and gate electrode of the transistor M8, and the other end of the constant current source I4, and a source electrode connected to the power supply. An amplifier circuit comprising a transistor M8 having a source electrode connected to a power supply, a constant current source I4 having the other end connected to a reference potential, and the transistor M6.
JP2000082462A 2000-03-23 2000-03-23 Amplifier circuit Withdrawn JP2001274640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000082462A JP2001274640A (en) 2000-03-23 2000-03-23 Amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000082462A JP2001274640A (en) 2000-03-23 2000-03-23 Amplifier circuit

Publications (1)

Publication Number Publication Date
JP2001274640A true JP2001274640A (en) 2001-10-05

Family

ID=18599267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000082462A Withdrawn JP2001274640A (en) 2000-03-23 2000-03-23 Amplifier circuit

Country Status (1)

Country Link
JP (1) JP2001274640A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006033200A (en) * 2004-07-13 2006-02-02 Sony Corp Amplifier circuit and semiconductor device having the amplifier circuit
JP2008278031A (en) * 2007-04-26 2008-11-13 Advantest Corp Differential output device and arbitrary waveform generating device
US7782137B2 (en) 2007-09-13 2010-08-24 Sumitomo Electric Industries, Ltd. Differential circuit providing a function to cancel input offset voltage
CN110620574A (en) * 2018-06-18 2019-12-27 英飞凌科技奥地利有限公司 System and method for driving a power switch in combination with a regulated DI/DT and/or DV/DT

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006033200A (en) * 2004-07-13 2006-02-02 Sony Corp Amplifier circuit and semiconductor device having the amplifier circuit
US7459971B2 (en) 2004-07-13 2008-12-02 Sony Corporation Amplifier circuit
JP2008278031A (en) * 2007-04-26 2008-11-13 Advantest Corp Differential output device and arbitrary waveform generating device
US7782137B2 (en) 2007-09-13 2010-08-24 Sumitomo Electric Industries, Ltd. Differential circuit providing a function to cancel input offset voltage
CN110620574A (en) * 2018-06-18 2019-12-27 英飞凌科技奥地利有限公司 System and method for driving a power switch in combination with a regulated DI/DT and/or DV/DT
CN110620574B (en) * 2018-06-18 2025-06-03 英飞凌科技奥地利有限公司 System and method for driving a power switch in combination with regulated DI/DT and/or DV/DT

Similar Documents

Publication Publication Date Title
US7298210B2 (en) Fast settling, low noise, low offset operational amplifier and method
JP2665025B2 (en) Amplifier circuit
JPH0345576B2 (en)
JP3007431B2 (en) Balanced microhorn preamplifier in CMOS technology.
JP3573849B2 (en) Amplifier circuit
JP2502057B2 (en) CMOS amplifier
CN101371435A (en) Amplifier circuit
JPH0786842A (en) Cascode circuit
US6249153B1 (en) High slew rate input differential pair with common mode input to ground
JP2001274640A (en) Amplifier circuit
JP2884896B2 (en) Differential operational amplifier
JP4456737B2 (en) Input circuit
US6496066B2 (en) Fully differential operational amplifier of the folded cascode type
EP1173923B1 (en) Differential pair provided with degeneration means for degenerating a transconductance of the differential pair
KR100681239B1 (en) Operational amplifier
JP2774120B2 (en) Amplifier circuit layout
JP2001111419A (en) Charge pump circuit
JPH07336169A (en) Amplifier circuit
KR20060136137A (en) Operational Amplifier
JPH09116349A (en) Operational amplifier
JP3250884B2 (en) Operational amplifier
JP2003124751A (en) Semiconductor integrated circuit
JPS58145206A (en) Differential amplifier
JPH09148855A (en) Differential operational amplifier
JPH05283950A (en) Operational amplifier

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20040303

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061108

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090616

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090623

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20090812