JP2001274388A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device with high performance as efficiently as possible. SOLUTION: The semiconductor device includes a diffusion layer 110 formed in a semiconductor region on the semiconductor substrate 101, an electrode 108a formed on the semiconductor substrate 101, and epitaxial semiconductor layers 103 and 103a selectively formed on the diffusion layer. In the constitution, the epitaxial semiconductor layer is connected directly to the electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the rapid progress of system-on-chip technology, miniaturization of devices has become increasingly important. Along with this, the diffusion layer becomes extremely thin, and for example, C
There has been proposed a technique of forming a shallow diffusion layer by adopting a so-called elevated source / drain structure in which an epitaxial layer is selectively grown on a source / drain diffusion layer of a MOS and then the source / drain is diffused. It has been done. On the other hand, the use of a gate electrode for wiring is generally performed, and is an effective technique for suppressing an increase in the number of wiring layers and hence an increase in manufacturing cost.

Conventionally, a polysilicon layer of a gate electrode is usually used as a wiring layer. Of course,
Since it is a wiring layer, it needs to be electrically connected to the diffusion layer. When the analog function is mixedly mounted, a BiCMOS device formed simultaneously with the bipolar element is often used. When functioning as a gate electrode, there is no need to make an electrical connection with the active layer because the gate insulating film is interposed between the active layer and the active layer. It is necessary to make a static connection.

MOSF using a gate electrode as a wiring layer
FIG. 8 shows a configuration of a conventional semiconductor device having ET.

An N-well diffusion layer 1 is formed on a p-type semiconductor substrate 101.
2 and an element isolation region 104 made of an insulating film. The N well diffusion layer 102 includes a P channel region 106, a low concentration source / drain diffusion layer 110 formed outside the P channel region,
High concentration source / drain diffusion layer 1 formed outside
15 and a connection region 160 formed of a P-type diffusion layer outside one of these diffusion layers 115. P
On the channel region 106, a gate electrode 108 made of polycrystalline silicon is formed via a gate insulating film 107.

Further, an insulating film 107 is formed on the connection region 160.
A gate electrode wiring 108a made of polycrystalline silicon is formed via a contact 150 provided at a.
These gate electrode 108 and gate electrode wiring 108
Side walls 111 and 112 made of an insulating film are provided on the side of “a”.

Further, a polycrystalline silicon layer 113a formed by epitaxial growth is provided on the upper surfaces of gate electrode 108 and gate electrode wiring 108a, and a silicide layer 116 is provided on polycrystalline silicon layer 113a. . Note that a silicide layer 116 is also formed on the high concentration diffusion layer 115.

Next, the configuration of another conventional semiconductor device is shown in FIG. This semiconductor device is a lateral NPN bipolar transistor and has a buried oxide film 2
02 having a single crystal silicon layer thereon.
It has a configuration formed on an OI (Silicon On Insulator) substrate.

In the single crystal silicon layer, a base layer 305 made of a P-type diffusion layer, and an emitter layer 308 and a collector layer 309 made of an N-type diffusion layer on both sides of the base layer 305 are formed. Further, an N ⁺ collector layer 310 is formed on the single crystal silicon layer outside the collector layer 309 so as to be in contact with the collector layer 309.

Then, the insulating film 30 is formed on the base layer 305.
The base electrode 307 is formed via the contact provided on the base 6. A side wall insulating film 311 made of an insulating film is provided on the side of the base electrode 307.

[0011]

In the conventional semiconductor device shown in FIG. 8, the gate electrode wiring 108a has the diffusion layer 1
It is electrically connected to the source / drain diffusion layer 115 via 60. In this case, the contact portion between the gate electrode wiring 108a and the diffusion layer 106 has the interface oxide film 107a having a thickness of about several nm, and thus has a disadvantage that the contact resistance increases. The minimum size of the manufacturing process is C
Contact size and _D is a necessary C _D at a minimum, also considering the alignment accuracy between the diffusion layer 160 and 8
As shown in FIG.
Size of 115,160 is forced to not give not exceed twice the minimum dimension C _D, increase in this region causes an increase in junction capacitance. The increase in the parasitic resistance described above hinders high-speed operation.

In the conventional semiconductor device shown in FIG. 9, a base electrode 307 is electrically connected to a base diffusion layer 305 through a contact hole. Since it is necessary to consider the alignment accuracy of the base diffusion layer 305, the width of the base diffusion layer 305 becomes large, which causes a problem that high-speed operation cannot be performed.

The present invention has been made in view of the above circumstances, and has as its object to obtain a semiconductor device having as high a performance as possible.

[0014]

A semiconductor device according to the present invention comprises: a diffusion layer formed in a semiconductor region of a semiconductor substrate; an electrode formed on the semiconductor substrate;
And a selectively formed epitaxial semiconductor layer, wherein the epitaxial semiconductor layer is directly connected to the electrode.

Preferably, the epitaxial semiconductor layer is formed so as to be in contact with one of the side surfaces of the electrode.

The semiconductor device includes a FET element having a gate electrode formed on a semiconductor region of the semiconductor substrate, and a source region and a drain region formed in the semiconductor region on both sides of the gate electrode. May be one of the source region and the drain region, and the electrode may be configured to be the same layer as the gate electrode.

The semiconductor substrate may be an SOI substrate.

The semiconductor substrate is an SOI substrate and has a second semiconductor region separated from the semiconductor region by an element. An FET element is formed in the second semiconductor region.
Bipolar having a base diffusion layer formed in the semiconductor region, an emitter diffusion layer and a collector diffusion layer formed in the semiconductor region on both sides of the base diffusion layer, and a base electrode formed on the semiconductor substrate The device may further include an element, wherein the diffusion layer is a base diffusion layer, and the electrode is a base electrode.

According to a first aspect of the method of manufacturing a semiconductor device according to the present invention, a first electrode is formed on a semiconductor region of a semiconductor substrate, and a second electrode is formed on the semiconductor substrate simultaneously with the formation of the first electrode. Forming the first electrode;
Forming a sidewall insulating film made of an insulating film on a side portion of the second electrode; forming first and second diffusion layers in the semiconductor regions on both sides of the first electrode; Selectively removing the sidewall insulating film on one side of the sidewall insulating films on both sides of the second electrode, and removing the sidewall insulating film on the first and second diffusion layers and the sidewall insulating film of the second electrode. An epitaxial semiconductor layer is selectively formed on the removed side portion and the second electrode by using an epitaxial growth method, and the epitaxial semiconductor layer, the first and second epitaxial layers are formed.
Electrically connecting a part of one of the diffusion layers to the second electrode.

According to a second aspect of the method of manufacturing a semiconductor device according to the present invention, there is provided a semiconductor device having a first semiconductor region and a second semiconductor region which is separated from the first semiconductor region by an element. Simultaneously forming a base electrode in one semiconductor region and a gate electrode in the second semiconductor region;
Forming a base diffusion layer in the first semiconductor region on one side of the base electrode; a part of an upper surface of the base electrode; and a side surface of the base electrode on the side where the base diffusion layer is formed And forming an epitaxial semiconductor layer on the base diffusion layer by using a selective epitaxial growth method, and electrically connecting the base electrode and the base diffusion layer with the epitaxial semiconductor layer. It is characterized by.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) A first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 1 to 3 are cross-sectional views illustrating a manufacturing process according to the first embodiment. The semiconductor device manufactured according to this embodiment includes a MOSFET having an elevated source / drain structure.

First, as shown in FIG. 1A, an element isolation region 104 is formed by selectively burying an insulating film such as an oxide film in a P-type semiconductor substrate 101, and then N-type such as phosphorus is implanted by ion implantation or the like. By adding an impurity and a P-type impurity such as boron to a desired region, an N-well diffusion layer 102 and a P-well diffusion layer 103 are formed.

Next, as shown in FIG. 1B, an impurity for controlling the threshold voltage of each FET element is added to a desired region by an ion implantation method or the like, and the P channel region 106 and the N region are added.
A channel region 105 is formed. Further, a gate oxide film 107 is formed by a thermal oxidation method. As a matter of course, the gate oxide film 107 may be made of a material other than the silicon oxide film, such as a silicon nitride film, in order to obtain desired characteristics. Thereafter, a gate electrode material, for example, a polycrystalline silicon film is grown on the entire surface by a low-pressure CVD method or the like, and subjected to a photolithography process to form gate electrodes 108 and 108a. At this time, of the gate electrodes 108 and 108a, the gate electrode 108a which needs to be electrically connected to the source / drain diffusion layers is formed so as to extend from the edge of the element region to the element isolation region 104.

Next, as shown in FIG.
The gate insulating film 107 in a region that is not covered with the gate electrodes 108 and 108a is removed using an etching solution such as a buffered hydrofluoric acid solution using the masks 08 and 108a as masks. This etching solution is effective when the gate insulating film 107 is a silicon oxide film. When the gate insulating film is a silicon nitride film, an etching solution in which a phosphoric acid aqueous solution is heated to 170 ° C. to 180 ° C. is effective. After the removal, the substrate is placed in an oxidizing atmosphere to form an oxide film 111 on the exposed substrate surface and the upper and side surfaces of the gate electrodes 108 and 108a. By adding an impurity to be a low-concentration source / drain diffusion layer to a desired region by ion implantation or the like, a low-concentration source / drain
A drain diffusion layer 109 and a low concentration source / drain diffusion layer 110 for a P-channel FET are formed. At this time, the low concentration source / drain diffusion layers are not formed immediately below the gate electrode because the gate electrode 108 serves as a mask when the impurity is added. Further, an insulating film such as a silicon nitride film is grown on the entire surface by a low pressure CVD method or the like, and thereafter, anisotropic etching such as reactive ion etching is performed on the entire surface, so that the side wall insulating film is selectively formed on the side surface of the gate electrode. Leave 112.

Next, as shown in FIG. 2A, after a resist 130 is applied to the entire surface, the side wall insulating film 112a on the side of the gate electrode 108a that is electrically connected to the source / drain diffusion layers is opened. The resist is patterned.

Next, as shown in FIG. 2B, after removing the sidewall insulating film 112a by an isotropic etching method, the resist pattern 130 is removed. Subsequently, the substrate is immersed in a buffered hydrofluoric acid solution to remove the oxide film 111 in a region not protected by the sidewall insulating film 112. At this time, the gate insulating film 1
The oxide film 111 on the top surface of the substrate 08 is also removed.

Next, as shown in FIG. 2C, when the silicon film is grown by the selective epitaxial growth method, the oxide film 1 is formed.
A single crystal film 113 is formed on the surface of the silicon layer from which 11 has been removed.
A polycrystalline silicon film 113a is selectively grown on a part of the top and side surfaces of the gate electrode.

Next, as shown in FIG. 3, a desired impurity is added to a desired region by ion implantation or the like to form a high concentration source / drain diffusion layer, and the high concentration source / drain diffusion layers 114 and 115 are formed. Form. Subsequently, a metal such as Co or Ti is grown on the entire surface by a sputtering method or the like, a desired thermal reaction is caused, a metal silicide film is formed only on silicon, and the unreacted metal is converted into an aqueous solution such as sulfuric acid and hydrogen peroxide. Then, the metal silicide film 116 is selectively formed (see FIG. 3).

In this manner, the wiring gate electrode 108 is formed.
a is connected to a desired source / drain diffusion layer 110 via a selective epitaxial layer 113 (see FIG. 2C). The source / drain diffusion layer 110 is different from the conventional case in that the gate electrode 1 serving as a wiring layer without the presence of an interface oxide film is provided.
The connection region between the diffusion layer 110 and the wiring layer can be reduced in resistance. Unlike the conventional case, there is no need to form a contact hole for forming a connection region between the gate electrode 108a and the diffusion layer 110, and the dimensions of the connection regions 110 and 115 are changed as shown in FIG. generally it is possible to realize by dimension C _D. As a result, the parasitic capacitance and the parasitic resistance of the connection region can be kept very low, and high-speed operation can be realized. Thus, a high-performance semiconductor device can be obtained.

The same effect can be obtained by using an SOI substrate instead of the semiconductor substrate 101 in the above embodiment.

(Second Embodiment) Next, a second embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.
This will be described with reference to FIG. 4 to 7 are cross-sectional views showing the manufacturing steps of the second embodiment. The semiconductor device manufactured by the manufacturing method of this embodiment is an N-channel MOSFET having an elevated source / drain structure.
And a lateral NPN bipolar transistor using SOI (Sili
con On Insulator) It is formed on a substrate.

As shown in FIG. 4A, an element isolation region 204 is formed by embedding an oxide film in a SOI substrate having a buried oxide film 202 on a support base 201 and a single crystal silicon layer 203 thereon. To form

Next, as shown in FIG. 4B, a region 203 of the single crystal silicon layer 203 for forming the lateral bipolar element is formed.
An n-type impurity such as phosphorus or arsenic is added to b by ion implantation or the like so as to function as a collector region. Subsequently, a single-crystal silicon layer 20 for forming an N-channel FET element
A channel diffusion layer 203c for adjusting the threshold voltage is formed in the third region 203a. Then, a gate insulating film 205 and an insulating film 206 are formed by using, for example, a CVD method.
The insulating film on the bipolar element forming region is a gate insulating film 20.
Thicker than 5 is desirable. This is because the base electrode of the bipolar element is formed on the insulating film 206, and it is necessary to make the influence of this potential less likely to affect the bipolar operation.

Next, as shown in FIG. 4C, after a polycrystalline silicon film is grown on the entire surface by using a low pressure CVD method or the like, the polycrystalline silicon film is patterned by a photolithography process to form electrodes 207a and 207b. I do. These electrodes 207a and 207b function as gate electrodes on the FET and as base electrodes on the bipolar transistor.

Next, as shown in FIG. 4 (d), after a silicon nitride film is formed on the entire surface by a low pressure CVD method or the like, this silicon nitride film is subjected to an anisotropic etching method to form a polycrystalline silicon electrode 207.
a, 207b are left only. Further, an oxide film deposited by a resist or a CVD method or the like is formed so as to cover one side surface of the base electrode, and then the sidewall insulating film formed on the remaining side surface of the base electrode 207b is removed. Thereby, the side wall insulating film 209 is formed only on one side surface of the base electrode 207b (see FIG. 4D). The entire surface is immersed in a buffered hydrofluoric acid aqueous solution to form a sidewall insulating film 209 and a polycrystalline silicon
Oxide films 206 and 205 in areas not protected by 7
Is removed (see FIG. 4D).

Next, as shown in FIG. 5A, by immersing in an oxidizing atmosphere, a region where single crystal silicon is exposed, a region of the base electrode 207b which is not protected by the side wall insulating film 209, and a gate electrode An oxide film 208 grows on the top and side surfaces of 207a.

Next, as shown in FIG. 5B, a high concentration collector layer 211 is formed by ion implantation or the like. Further, the low concentration source / drain diffusion layer 210 is formed by an ion implantation method or the like (see FIG. 5B).

Next, as shown in FIG. 5C, a silicon nitride film is deposited on the entire surface by a low-pressure CVD method or the like, and this silicon nitride film is subjected to an anisotropic etching method to form a polycrystalline silicon electrode 207.
Only the side surfaces of a and 207b are left on the silicon nitride film 212.

Next, as shown in FIG.
Only the side wall insulating films 209 and 212 of 07b are selectively removed.

Subsequently, after a photoresist is applied to the entire surface, the base electrode 207 is formed by using a photolithography technique.
The resist 230 is left on a part of the upper surface b, the side surface on the side of the high concentration collector layer 211 and the high concentration collector layer 211.
Thereafter, the insulating film 208 in a region not protected by the resist 230 and the oxide film 208 not covered by the side wall film 212 on the MOSFET side are removed by immersion in a buffered hydrofluoric acid aqueous solution.

Next, as shown in FIG.
After removing 0, a pattern made of photoresist is formed again, and using this pattern as a mask, a base impurity is added by ion implantation or the like to form a base diffusion layer 213.

Subsequently, after removing the pattern made of the resist, a silicon layer is selectively grown by using a selective epitaxial growth method as shown in FIG.
A silicon epitaxial layer 214 is formed on the base diffusion layer 213, a part of the base electrode 207, a part where the silicon layer of the FET is exposed, and the gate electrode. Further, a side wall insulating film 215 is formed on side surfaces of the base electrode and the gate electrode.

Next, as shown in FIG. 7B, after the emitter diffusion layer 216 is formed by an ion implantation method or the like, the emitter diffusion layer 216 is immersed in a buffered hydrofluoric acid solution to form a part of the base electrode upper surface and the high concentration collector layer 211 side. The oxide film 208 on the side surface of and the high concentration collector diffusion layer is removed.

Subsequently, by performing a selective silicide process, a silicide film 218 is formed on the emitter diffusion layer, the base electrode, the high concentration collector diffusion layer, the source / drain diffusion layer, and the gate electrode.

In the semiconductor device manufactured by the manufacturing method of the present embodiment as described above, since the base diffusion layer and the base electrode are connected by a very narrow selective epitaxial layer, the width of base diffusion layer 213 is reduced. It can be formed to be narrow, and a high-performance bipolar transistor can be mixedly mounted.

[0047]

As described above, according to the present invention, a semiconductor device having as high a performance as possible can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing process according to the second embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process according to the second embodiment of the present invention.

FIG. 7 is a sectional view showing a manufacturing process according to the second embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

FIG. 9 is a cross-sectional view illustrating a configuration of another conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 N well 103 P well 104 Element isolation region 105 N channel region 106 P channel region 107 Gate insulating film 108 Gate electrode 108 a Gate electrode (wiring layer) 109 Low concentration source / drain diffusion layer 110 Low concentration source / drain diffusion Layer 111 Oxide film 112 Side wall insulating film 113 Single crystal layer 113a Polycrystalline silicon layer 114 High concentration source / drain diffusion layer 115 High concentration source / drain diffusion layer 116 Silicide layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8249 H01L 27/06 321B 5F110 21/8238 27/08 321F 27/092 321N 21/331 29/72 29/73 29/78 301S 29/786 616K 616U 617J 617L F term (reference) 4M104 AA01 AA09 BB01 BB20 BB25 CC01 CC05 DD04 DD37 DD43 DD46 DD64 DD78 DD84 EE09 EE12 EE14 EE17 FF14 FF15 GG09 GG15H14 GG09 GG10H14 GG09 GG10H14 BB08 BC01 BH07 BJ15 BN01 BP33 BP34 BS05 BS06 BS08 5F040 DA01 DB03 DB07 DC01 EB12 EC07 ED04 EF02 EH02 EK01 EK05 FA07 FB02 FC06 FC10 FC19 5F048 AC03 AC07 BA01 BA16 BB05 BB11 BC06 BD04 DA03 BG06 CA14 DA03 BG06 CA13 DA04 AA06 BA05 BA29 BC01 BC09 DA03 DA09 EA07 EA15 EA24 5F110 AA02 BB04 CC02 DD05 DD13 EE05 EE09 EE15 EE 32 EE33 EE42 FF02 FF03 FF23 GG02 GG12 GG32 GG52 HJ01 HJ13 HK05 HK09 HK21 HK32 HK40 HM15 NN62 NN71 QQ08 QQ11 QQ17

Claims (7)

[Claims] 1. A semiconductor device comprising: a diffusion layer formed in a semiconductor region of a semiconductor substrate; an electrode formed on the semiconductor substrate; and an epitaxial semiconductor layer selectively formed on the diffusion layer. A semiconductor device, wherein an epitaxial semiconductor layer is configured to be directly connected to the electrode. 2. The semiconductor device according to claim 1, wherein said epitaxial semiconductor layer is formed so as to be in contact with one of side surfaces of said electrode. 3. An FET device having a gate electrode formed on a semiconductor region of the semiconductor substrate and a source region and a drain region formed in the semiconductor region on both sides of the gate electrode. 3. The semiconductor device according to claim 1, wherein: is one of the source region and the drain region, and the electrode is configured to be the same layer as the gate electrode. 4. . 4. The semiconductor device according to claim 1, wherein said semiconductor substrate is an SOI substrate. 5. The semiconductor substrate is an SOI substrate and has a second semiconductor region separated from the semiconductor region by an element. An FET element is formed in the second semiconductor region, and the semiconductor substrate is formed in the semiconductor region. A bipolar element having a base diffusion layer, an emitter diffusion layer and a collector diffusion layer formed in the semiconductor region on both sides of the base diffusion layer, and a base electrode formed on the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein the diffusion layer is a base diffusion layer, and the electrode is a base electrode. 6. A step of forming a first electrode on a semiconductor region of a semiconductor substrate and forming a second electrode on the semiconductor substrate simultaneously with the formation of the first electrode; Forming a sidewall insulating film made of an insulating film on a side portion of the first electrode, forming first and second diffusion layers in the semiconductor region on both sides of the first electrode, and forming the second electrode Selectively removing the sidewall insulating film on one side of the sidewall insulating films on both sides of the substrate; and removing the sidewall insulating film on the first and second diffusion layers and on the second electrode. Forming an epitaxial semiconductor layer on the side portion and the second electrode selectively using an epitaxial growth method;
Electrically connecting a part of one of the first and second diffusion layers to the second electrode. A method for manufacturing a semiconductor device, comprising: 7. A semiconductor substrate having a first semiconductor region and a second semiconductor region separated from the first semiconductor region by a base electrode in the first semiconductor region.
Forming a gate electrode in the semiconductor region at the same time; forming a base diffusion layer in the first semiconductor region on one side of the base electrode; a part of the upper surface of the base electrode; and the base electrode Forming an epitaxial semiconductor layer on the side surface on which the base diffusion layer is formed, and on the base diffusion layer by using a selective epitaxial growth method, and by using the epitaxial semiconductor layer, the base electrode and the base diffusion layer Electrically connecting the semiconductor device to the semiconductor device.