[go: up one dir, main page]

JP2001274069A - Resist pattern forming method and semiconductor manufacturing system - Google Patents

Resist pattern forming method and semiconductor manufacturing system

Info

Publication number
JP2001274069A
JP2001274069A JP2000087399A JP2000087399A JP2001274069A JP 2001274069 A JP2001274069 A JP 2001274069A JP 2000087399 A JP2000087399 A JP 2000087399A JP 2000087399 A JP2000087399 A JP 2000087399A JP 2001274069 A JP2001274069 A JP 2001274069A
Authority
JP
Japan
Prior art keywords
substrate
amount
hot plate
processed
warpage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000087399A
Other languages
Japanese (ja)
Other versions
JP3708786B2 (en
JP2001274069A5 (en
Inventor
Kenji Kawano
健二 川野
Shinichi Ito
信一 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000087399A priority Critical patent/JP3708786B2/en
Publication of JP2001274069A publication Critical patent/JP2001274069A/en
Publication of JP2001274069A5 publication Critical patent/JP2001274069A5/ja
Application granted granted Critical
Publication of JP3708786B2 publication Critical patent/JP3708786B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

(57)【要約】 【課題】 反りを有するウェハに対してもウェハ面内で
優れた均一性を持った加熱処理を行うことができ、レジ
ストパターンの加工精度向上をはかる。 【解決手段】 露光装置10内でウェハ上のレジスト膜
にLSIパターンを露光したのち、ウェハをPEBユニ
ット26内の熱板上に載置して加熱処理し、しかるのち
現像装置27内でレジスト膜に現像処理を施すレジスト
パターン形成方法において、加熱処理する工程よりも前
に露光装置10内でウェハの反り量を計測し、ウェハを
加熱処理する工程で、計測した反り量に基づいて、熱板
の基板載置面における基板と熱板との距離が長いほど供
給熱量が多くなるように、熱板の温度を面内方向で変え
る。
(57) [Summary] [PROBLEMS] To perform a heat treatment with excellent uniformity on a wafer surface even for a warped wafer, thereby improving the processing accuracy of a resist pattern. SOLUTION: After exposing an LSI pattern to a resist film on a wafer in an exposure apparatus 10, the wafer is placed on a hot plate in a PEB unit 26 and subjected to a heat treatment. In the method of forming a resist pattern for developing the wafer, the amount of warpage of the wafer is measured in the exposure apparatus 10 before the step of heating, and the hot plate is heated based on the measured amount of warpage in the step of heating the wafer. The temperature of the hot plate is changed in the in-plane direction such that the longer the distance between the substrate and the hot plate on the substrate mounting surface becomes, the larger the amount of supplied heat becomes.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、被加工基板上に形
成されたレジストに所望パターンを形成するためのリソ
グラフィ技術に係わり、特に被加工基板の反りの影響を
考慮したレジストパターン形成方法及び半導体製造シス
テムに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lithography technique for forming a desired pattern on a resist formed on a substrate to be processed, and more particularly to a method of forming a resist pattern and a semiconductor in which the influence of warpage of the substrate to be processed is taken into consideration. Related to manufacturing system.

【0002】[0002]

【従来の技術】半導体装置のリソグラフィ工程では、半
導体素子の微細化に伴って化学増幅型レジストの適用が
必須となっている。この種のレジストを用いたプロセス
では、露光で生じた酸を拡散させるために、露光後にP
EB(Post Exposure Bake)と呼ばれる加熱処理工程が
必要になる。そして、レジストのパターン寸法は、PE
Bの処理温度に大きく依存するために、基板面内及び基
板間での温度均一性が必要とされている。
2. Description of the Related Art In a lithography process of a semiconductor device, application of a chemically amplified resist has become indispensable with miniaturization of a semiconductor element. In a process using this type of resist, P is applied after exposure to diffuse the acid generated by exposure.
A heat treatment step called EB (Post Exposure Bake) is required. And the resist pattern size is PE
Since the temperature greatly depends on the processing temperature of B, temperature uniformity within the substrate surface and between the substrates is required.

【0003】PEB処理は、半導体基板を温調された熱
板と微少な隙間(プロキシミティギャップ)を設けた状
態で載置するか、或いは基板と熱板を密着して行う方法
が一般に用いられている。そして、PEB処理を行うた
めの加熱装置では通常、平坦な熱板が使用されている。
In the PEB process, a method is generally used in which a semiconductor substrate is placed in a state where a small gap (proximity gap) is provided between a temperature-controlled hot plate and a substrate and a hot plate are in close contact with each other. ing. A heating device for performing the PEB process usually uses a flat hot plate.

【0004】ところで、リングラフィ工程を行う半導体
基板上には、トランジスタのキャパシタ材である誘電体
膜、配線に用いる金属膜、層間絶縁膜などが既に形成さ
れているため、半導体基板には反りが生じている場合が
多い。このような半導体基板を加熱装置内の熱板を用い
て加熱処理すると、基板面内において熱板と基板との距
離に差が生じるため、基板表面での温度ばらつきが大き
くなってしまうという問題点が生じていた。
Incidentally, since a dielectric film as a capacitor material of a transistor, a metal film used for wiring, an interlayer insulating film, and the like are already formed on a semiconductor substrate on which a lithography process is performed, the semiconductor substrate is warped. It often occurs. When such a semiconductor substrate is subjected to heat treatment using a hot plate in a heating device, a difference occurs in the distance between the hot plate and the substrate in the substrate surface, so that the temperature variation on the substrate surface increases. Had occurred.

【0005】これらの問題点に対して、熱板上面部に複
数の温度センサを設け、半導体基板を熱板上に載置する
前後の温度変化を検出することで基板の反り量を間接的
に求め、反り量が許容範囲以上の場合は熱板の設定温度
を変更する熱処理装置が既に提案されている(特開平1
1−329941号公報)。しかし、この種の装置で
は、基板反り量を加熱処理温度ヘフィードバックするま
での間に加熱処理が進行してしまうため、温度精度の優
れた加熱処理を行うことは困難であった。また、複数の
温度センサが別途必要となるために、コストが高くなる
という新たな問題点も生じていた。
In order to solve these problems, a plurality of temperature sensors are provided on the upper surface of the hot plate, and the amount of warpage of the substrate is indirectly detected by detecting a temperature change before and after placing the semiconductor substrate on the hot plate. A heat treatment apparatus that changes the set temperature of the hot plate when the amount of warpage is equal to or larger than the allowable range has already been proposed (Japanese Patent Laid-Open No. Hei 1 (1994)).
No. 1-329941). However, in this type of apparatus, it is difficult to perform heat treatment with excellent temperature accuracy because the heat treatment proceeds before the amount of substrate warpage is fed back to the heat treatment temperature. Further, since a plurality of temperature sensors are separately required, a new problem that the cost is increased has occurred.

【0006】[0006]

【発明が解決しようとする課題】このように従来、パタ
ーン露光に供される半導体基板が反った形状を持ってい
ると、露光後のPEB処理等において熱板で加熱処理す
る際に基板面内で温度のばらつきが生じ、最終的に得ら
れるレジストパターンの加工精度が低下する問題があっ
た。
As described above, conventionally, when a semiconductor substrate subjected to pattern exposure has a warped shape, heat treatment with a hot plate in a PEB process or the like after exposure may cause a problem in the substrate surface. In this case, there is a problem that temperature variations occur and the processing accuracy of a finally obtained resist pattern is reduced.

【0007】本発明は、上記事情を考慮して成されたも
ので、その目的とするところは、被加工基板が反った形
状を持ち、その反り量が基板毎に異なっていても基板面
内で優れた均一性を持った加熱処理を行うことができ、
レジストパターンの加工精度向上に寄与し得るレジスト
パターン形成方法及び半導体製造システムを提供するこ
とにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a substrate to be processed having a warped shape, and even if the amount of warpage differs for each substrate, the in-plane surface of the substrate can be obtained. Heat treatment with excellent uniformity
An object of the present invention is to provide a method of forming a resist pattern and a semiconductor manufacturing system that can contribute to improvement in processing accuracy of a resist pattern.

【0008】[0008]

【課題を解決するための手段】(構成)上記課題を解決
するために本発明は、次のような構成を採用している。
(Structure) In order to solve the above-mentioned problem, the present invention employs the following structure.

【0009】即ち本発明は、被加工基板上にレジスト膜
を形成する工程と、前記レジスト膜に所望パターンを露
光する工程と、前記レジスト膜にパターンが露光された
基板を熱板上に載置して加熱処理する工程と、前記加熱
処理されたレジスト膜に現像処理を施す工程とを含むレ
ジストパターン形成方法において、前記加熱処理する工
程よりも前に前記被加工基板の反り量を計測し、前記被
加工基板を加熱処理する工程で、前記計測した反り量に
応じて前記熱板による供給熱量を制御することを特徴と
する。
That is, the present invention provides a step of forming a resist film on a substrate to be processed, a step of exposing a desired pattern to the resist film, and a step of placing the substrate having the pattern exposed on the resist film on a hot plate. In the resist pattern forming method including a step of performing a heat treatment and a step of performing a development treatment on the heat-treated resist film, measuring the amount of warpage of the substrate to be processed before the step of performing the heat treatment, In the step of heating the substrate to be processed, the amount of heat supplied by the hot plate is controlled according to the measured amount of warpage.

【0010】ここで、本発明の望ましい実施態様として
は次のものが挙げられる。 (1) 熱板による供給熱量を制御する手段として、熱板の
基板載置面における被加工基板と熱板との距離が長いほ
ど供給熱量が多くなるように、熱板の温度を面内方向で
変えること。
Here, preferred embodiments of the present invention include the following. (1) As means for controlling the amount of heat supplied by the hot plate, the temperature of the hot plate is adjusted in the in-plane direction so that the longer the distance between the substrate to be processed and the hot plate on the substrate mounting surface of the hot plate, the larger the amount of heat supplied. Change with.

【0011】(2) 熱板による供給熱量を制御する手段と
して、被加工基板の反り量が大きいほど熱板によるトー
タルの供給熱量を多くするように、熱板の温度を制御す
ること。
(2) As means for controlling the amount of heat supplied by the hot plate, the temperature of the hot plate is controlled so that the larger the amount of warpage of the substrate to be processed, the greater the total amount of heat supplied by the hot plate.

【0012】(3) 被加工基板の反り量を計測する手段と
して、レジスト膜に所望パターンを露光するための露光
装置内で、被加工基板をステージ上に固定するための真
空チャック圧の面内分布を求め、この分布に基づいて反
り量を算出すること。
(3) As means for measuring the amount of warpage of the substrate to be processed, an in-plane of vacuum chuck pressure for fixing the substrate to be processed on a stage in an exposure apparatus for exposing a desired pattern on a resist film. Obtaining a distribution and calculating the amount of warpage based on this distribution.

【0013】また本発明は、被加工基板上にレジスト膜
を形成するレジスト塗布装置と、前記レジスト膜が形成
された被加工基板に対して所望パターンを露光する露光
装置と、前記パターンが露光された被加工基板を熱板上
に載置して加熱処理する加熱装置と、前記加熱処理され
た被加工基板に対して現像処理を施す現像装置と、前記
被加工基板を前記各装置間で搬送する搬送機構と、前記
被加工基板の反り量を計測する手段とを備えた半導体製
造システムであって、前記加熱装置は、前記計測手段に
より計測された基板の反り量に基づいて、前記熱板の基
板載置面における前記被加工基板と前記熱板との距離が
長いほど供給熱量が多くなるように、前記熱板の面内方
向の温度分布を制御するものであることを特徴とする。
Further, the present invention provides a resist coating apparatus for forming a resist film on a substrate to be processed, an exposure apparatus for exposing a desired pattern to the substrate on which the resist film is formed, and an exposure apparatus for exposing the pattern. A heating device for placing the processed substrate on a hot plate and performing a heating process, a developing device for performing a developing process on the heated processed substrate, and transporting the processed substrate between the respective devices. And a heating mechanism for measuring the amount of warpage of the substrate to be processed, wherein the heating device is configured to control the heating plate based on the amount of warpage of the substrate measured by the measuring unit. The temperature distribution in the in-plane direction of the hot plate is controlled such that the longer the distance between the substrate to be processed and the hot plate on the substrate mounting surface, the larger the amount of heat supplied.

【0014】また本発明は、被加工基板上にレジスト膜
を形成するレジスト塗布装置と、前記レジスト膜が形成
された被加工基板に対して所望パターンを露光する露光
装置と、前記パターンが露光された被加工基板を熱板上
に載置して加熱処理する加熱装置と、前記加熱処理され
た被加工基板に対して現像処理を施す現像装置と、前記
被加工基板を前記各装置間で搬送する搬送機構と、前記
被加工基板の反り量を計測する手段とを備えた半導体製
造システムであって、前記加熱装置は、前記計測手段に
より計測された基板の反り量に基づいて、反り量が大き
いほどトータルの供給熱量が多くなるように前記熱板の
温度を制御するものであることを特徴とする。
The present invention also provides a resist coating apparatus for forming a resist film on a substrate to be processed, an exposure apparatus for exposing a desired pattern on the substrate on which the resist film has been formed, and an exposure apparatus for exposing the pattern. A heating device for placing the processed substrate on a hot plate and performing a heating process, a developing device for performing a developing process on the heated processed substrate, and transporting the processed substrate between the respective devices. A transfer mechanism, and a means for measuring the amount of warpage of the substrate to be processed, wherein the heating device has an amount of warpage based on the amount of warpage of the substrate measured by the measuring means. It is characterized in that the temperature of the hot plate is controlled so that the total amount of supplied heat increases as the temperature increases.

【0015】ここで、本発明の望ましい実施態様として
は次のものが挙げられる。 (1) 被加工基板の反り量を計測する手段は、露光装置内
で前記被加工基板をステージ上に固定するための真空チ
ャック機構に、真空チャック圧の面内分布を検出する機
能を設け、検出された面内分布に従って反り量を算出す
るものであること。
Here, preferred embodiments of the present invention include the following. (1) The means for measuring the amount of warpage of the substrate to be processed is provided in a vacuum chuck mechanism for fixing the substrate to be processed on a stage in an exposure apparatus, and a function of detecting an in-plane distribution of vacuum chuck pressure is provided. Calculate the amount of warpage according to the detected in-plane distribution.

【0016】(2) 加熱装置の熱板は、径の異なる複数の
同心環状ヒータを有し、各々のヒータが独立に温度制御
可能であること。
(2) The heating plate of the heating device has a plurality of concentric annular heaters having different diameters, and each heater can independently control the temperature.

【0017】(作用)先にも説明したように、リングラ
フィ工程でパターン転写に供される被加工基板は、下地
に様々な膜が形成されているため、一般に反った形状と
なっている。このような基板を熱板で加熱処理する場
合、熱板と基板との距離が基板面内で異なるため、供給
される熱量に基板面内でばらつきが生じる。露光後に行
うPEBと呼ばれる加熱処理工程で供給される熱量と現
像後に形成されるレジストパターンの寸法との間には密
接な関係がある。このため、PEB工程で供給される熱
量のばらつきが大きいと、寸法の均一性を劣化させてし
まう。
(Function) As described above, the substrate to be subjected to the pattern transfer in the lithography step generally has a warped shape because various films are formed on the base. When such a substrate is subjected to heat treatment with a hot plate, the distance between the hot plate and the substrate is different in the substrate surface, so that the amount of heat supplied varies in the substrate surface. There is a close relationship between the amount of heat supplied in a heat treatment step called PEB performed after exposure and the size of a resist pattern formed after development. Therefore, if there is a large variation in the amount of heat supplied in the PEB process, dimensional uniformity will be deteriorated.

【0018】本発明では、PEB工程に先立ち(例えば
露光装置内において)、基板の反り量データを取得し、
その反り量に基づきPEB時に熱板から供給する熱量の
制御を行っている。熱量制御の第1の方法として、熱板
の基板載置面における基板と熱板との距離が長いほど供
給熱量が多くなるように熱板の温度を面内方向で変える
ことにより、基板を面内で均一に加熱することができ
る。熱量制御の第2の方法として、被加工基板の反り量
が大きいほど熱板によるトータルの供給熱量を多くする
用に熱板の温度を制御することにより、反り量の異なる
基板に対して均一な加熱処理を行うことができる。
In the present invention, prior to the PEB process (for example, in an exposure apparatus), data on the amount of warpage of the substrate is obtained,
The amount of heat supplied from the hot plate at the time of PEB is controlled based on the amount of warpage. As a first method of controlling the amount of heat, the temperature of the hot plate is changed in the in-plane direction such that the longer the distance between the substrate and the hot plate on the substrate mounting surface of the hot plate, the greater the amount of heat supplied, so that the substrate is It can be heated uniformly within. As a second method of controlling the amount of heat, the temperature of the hot plate is controlled so that the total amount of heat supplied by the hot plate increases as the amount of warpage of the substrate to be processed increases, so that the substrates having different amounts of warp can be uniformly controlled. Heat treatment can be performed.

【0019】また、フィードバック制御ではなくフィー
ドフォワード制御のため、温度制御の遅れがなく、より
正確な温度制御が可能となる。さらに、加熱装置内に複
数の温度センサを設ける必要もなく、コストが高くなる
等の不都合もない。従って本発明によれば、被加工基板
が反った形状を持ち、その反り量が基板毎に異なってい
ても基板面内及び基板間で優れた均一性を持った加熱処
理を行うことができ、レジストパターンの加工精度向上
に寄与することが可能となる。
Further, since feed-forward control is used instead of feedback control, there is no delay in temperature control, and more accurate temperature control can be performed. Furthermore, there is no need to provide a plurality of temperature sensors in the heating device, and there is no disadvantage such as an increase in cost. Therefore, according to the present invention, the substrate to be processed has a warped shape, and even if the amount of warpage differs for each substrate, it is possible to perform heat treatment with excellent uniformity within the substrate surface and between the substrates, It is possible to contribute to improvement in processing accuracy of the resist pattern.

【0020】[0020]

【発明の実施の形態】以下、本発明の詳細を図示の実施
形態によって説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

【0021】(第1の実施形態)図1は、本発明の第1
の実施形態に係わる半導体製造システムを模式的に示す
構成図である。
(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 is a configuration diagram schematically showing a semiconductor manufacturing system according to an embodiment.

【0022】露光装置10とレジスト処理装置20がイ
ンターフェースユニット30を介して接続されている。
露光装置10は、ステージ上に載置されたウェハに対し
て、投影露光基板(マスク)に形成されたパターンを露
光するものであるが、この基本的機能とは別に後述する
ように、ステージ上のウェハの反り量を計測できるよう
になっている。
The exposure apparatus 10 and the resist processing apparatus 20 are connected via an interface unit 30.
The exposure apparatus 10 exposes a wafer mounted on a stage to a pattern formed on a projection exposure substrate (mask), and apart from this basic function, as will be described later, Of the wafer can be measured.

【0023】レジスト処理装置20は、複数枚のウェハ
がセットされるウェハステーション21、ウェハ上に反
射防止膜を塗布するための第1の塗布ユニット22(C
OT1)、ウェハ上にレジストを塗布するための第2の
塗布ユニット23(COT2)、反射防止膜をベークす
るための第1のベークユニット24(HP1)、レジス
トをプリベークするための第2のベークユニット25
(HP2)、レジストをポストベークするための第3の
ベークユニット26(HP3)、レジストを現像するた
めの現像ユニット27、図示しない冷却ユニット及び搬
送ユニットなどから構成されている。ここで、ベークユ
ニット26は熱板上に載置されたウェハを加熱処理する
ものであるが、後述するように熱板表面の温度を面内で
可変制御できるようになっている。
The resist processing apparatus 20 includes a wafer station 21 on which a plurality of wafers are set, and a first coating unit 22 (C) for coating an antireflection film on the wafer.
OT1), a second coating unit 23 (COT2) for coating a resist on the wafer, a first baking unit 24 (HP1) for baking the antireflection film, and a second baking for pre-baking the resist Unit 25
(HP2), a third bake unit 26 (HP3) for post-baking the resist, a developing unit 27 for developing the resist, a cooling unit and a transport unit (not shown), and the like. Here, the baking unit 26 heats the wafer placed on the hot plate, and is capable of variably controlling the temperature of the hot plate surface in a plane as described later.

【0024】次に、本実施形態におけるレジストパター
ン形成プロセスを、図2のフローチャートに従って説明
する。
Next, the process of forming a resist pattern according to this embodiment will be described with reference to the flowchart of FIG.

【0025】まず、ウェハステーション21に載置され
たウェハ(図示せず)を、搬送ユニットで第1の塗布ユ
ニット22に搬送し、ウェハ上に反射防止膜を塗布した
(ステップ1)。続いて、ウェハを搬送ユニットで第1
のベークユニット24に搬送し、190℃,60秒の条
件でベーク処理して、膜厚60nmの反射防止膜を形成
した(ステップ2)。
First, a wafer (not shown) mounted on the wafer station 21 was transferred to the first coating unit 22 by a transfer unit, and an antireflection film was coated on the wafer (step 1). Subsequently, the wafer is first transferred by the transfer unit.
Was transferred to the baking unit 24 and baked at 190 ° C. for 60 seconds to form an antireflection film having a thickness of 60 nm (step 2).

【0026】次いで、ウェハを一旦冷却ユニットに搬送
して冷却処理を行った後、該ウェハを第2の塗布ユニッ
ト23に搬送し、ポジ型化学増幅レジストを塗布した
(ステップ3)。続いて、ウェハを第2のベークユニッ
ト25に搬送し、140℃,90秒の条件でプリベーク
と呼ばれるレジスト中の溶剤を揮発させるための加熱処
理を行った(ステップ4)。これにより、反射防止膜上
に400nmのレジスト膜を形成した。
Next, the wafer was once transported to a cooling unit to perform a cooling process, and then the wafer was transported to a second coating unit 23, where a positive chemically amplified resist was applied (step 3). Subsequently, the wafer was transported to the second bake unit 25, and a heat treatment for volatilizing a solvent in the resist called prebake was performed at 140 ° C. for 90 seconds (step 4). As a result, a 400 nm resist film was formed on the antireflection film.

【0027】次いで、ウェハを冷却ユニットに搬送して
室温近傍まで冷却した後、インターフェースユニット3
0を経て露光装置10へ搬送し、投影露光用マスクを用
いて、所望の潜像をレジスト膜に転写した(ステップ
5)。
Next, after transferring the wafer to the cooling unit and cooling it to around room temperature, the interface unit 3
After that, the wafer was conveyed to the exposure apparatus 10 and a desired latent image was transferred to a resist film using a projection exposure mask (Step 5).

【0028】露光工程では、マスクパターンを縮小投影
する際にフォーカスがずれると、光学像が大きく劣化
し、所望のパターンが得られない。このため、露光装置
内にはウェハの反りに伴うフォーカスずれを低減するた
めに、ウェハを支持するステージにバキュームチャック
機能を設け、ステージ上でウェハがフラットになるよう
にしている。
In the exposure step, if the focus shifts when the mask pattern is reduced and projected, the optical image is greatly deteriorated, and a desired pattern cannot be obtained. For this reason, in the exposure apparatus, a vacuum chuck function is provided on a stage for supporting the wafer in order to reduce a focus shift due to the warpage of the wafer, so that the wafer becomes flat on the stage.

【0029】本実施形態では、このバキュームチャック
の圧力分布を基にウェハの反り量を算出した。図3を参
照して、バキュームチャックの圧力分布を求める方法を
説明する。図3(a)(b)はウェハステージの平面図
と断面図を模式的に示したものであり、図3(c)はバ
キュームチャック時の圧力変化を示している。
In the present embodiment, the amount of warpage of the wafer is calculated based on the pressure distribution of the vacuum chuck. With reference to FIG. 3, a method for obtaining the pressure distribution of the vacuum chuck will be described. FIGS. 3A and 3B schematically show a plan view and a cross-sectional view of the wafer stage, and FIG. 3C shows a pressure change at the time of the vacuum chuck.

【0030】図3(a)(b)に示すように、ウェハス
テージ40の表面側には、径の異なる4つの同心円状の
溝41が設けられ、これらの溝41は共通の真空系に接
続されている。各々の溝41には、それぞれ圧力センサ
42が設けられており、図3(c)に示すように、チャ
ッキングを開始してからの時間に対する圧力変化がモニ
タできるようになっている。
As shown in FIGS. 3A and 3B, four concentric grooves 41 having different diameters are provided on the front side of the wafer stage 40, and these grooves 41 are connected to a common vacuum system. Have been. Each groove 41 is provided with a pressure sensor 42, and as shown in FIG. 3 (c), a pressure change with respect to the time from the start of chucking can be monitored.

【0031】ここでは、時間t1において、チャッキン
グが完了したことになる。ステージと基板との距離、即
ちチャッキング位置での基板の反り量は、チャッキング
完了時間t1との間に密接な関係があり、基板の反り量
が大きいほど、チャッキング完了時間t1は大きくな
る。従って、各チャッキング位置での時間t1と基板の
反り量の関係を事前に求めておくことで、時間t1から
基板の反り量を算出することができる。
Here, the chucking is completed at time t1. The distance between the stage and the substrate, that is, the amount of substrate warpage at the chucking position is closely related to the chucking completion time t1, and the larger the amount of substrate warpage, the longer the chucking completion time t1. . Accordingly, the relationship between the time t1 at each chucking position and the amount of warpage of the substrate is obtained in advance, so that the amount of warpage of the substrate can be calculated from the time t1.

【0032】なお、溝41は必ずしも径方向に連続した
ものである必要はなく、一定間隔毎に仕切りを設けて分
離させるようにしてもよい。この場合、径方向に分離し
た溝毎に圧力センサを設けることにより、径方向に対し
ても複数箇所で圧力を検出できることになり、より分解
能の高い検出が可能となる。
The grooves 41 need not necessarily be continuous in the radial direction, but may be separated by providing partitions at regular intervals. In this case, by providing a pressure sensor for each groove separated in the radial direction, pressure can be detected at a plurality of positions also in the radial direction, and detection with higher resolution can be performed.

【0033】図4に、上記の圧力センサの検出信号を元
に得られたウェハ反り量の等高線図を示す。この図で
は、中央が窪む凹形状になっている。なお、このデータ
は、溝41を径方向に分離し、分離した各々に圧力セン
サをそれぞれ設けた例に対応している。
FIG. 4 is a contour diagram of the amount of wafer warpage obtained based on the detection signal of the pressure sensor. In this figure, the center is concave. Note that this data corresponds to an example in which the groove 41 is separated in the radial direction, and a pressure sensor is provided in each of the separated grooves.

【0034】このようにして得られたウェハ反り量デー
タは、図5に示すように露光装置10の内部に一時保存
され、露光後に行うベークユニット(PEBユニット)
26のヒータ制御部65へと送られる。そして、データ
制御部65により、ウェハ反り量データに基づいて熱板
60による加熱処理温度が設定されるようになってい
る。
The wafer warpage amount data thus obtained is temporarily stored inside the exposure apparatus 10 as shown in FIG. 5, and is baked after exposure (PEB unit).
It is sent to the heater control unit 65 of FIG. Then, the data control unit 65 sets the temperature of the heat treatment by the hot plate 60 based on the wafer warpage amount data.

【0035】ここで、ベーク処理ユニット26内に設置
された熱板60の構造及び加熱処理温度の設定方法につ
いて説明する。加熱処理温度は140℃とした。図6
(a)にPEBユニット26の熱板60の構成断面図
を、(b)に熱板60のヒータパターンの平面図を示
す。
Here, the structure of the hot plate 60 installed in the bake processing unit 26 and a method of setting the heat processing temperature will be described. The heat treatment temperature was 140 ° C. FIG.
(A) is a sectional view of the configuration of the hot plate 60 of the PEB unit 26, and (b) is a plan view of a heater pattern of the hot plate 60.

【0036】円形の熱板60の裏面側に径の異なる同心
円状の複数(例えば3つ)のヒータ61,62,63が
設けられ、各々のヒータは熱板60に埋め込まれた熱電
対(図示せず)の検出信号を基にそれぞれが独立に温度
制御されている。ウェハ50は熱板60の表面側にセッ
トされるが、熱板60との接触によるウェハ裏面の汚染
を防ぐために、外周部にプロキシミティギャップ55
(0.1mm)が配置されている。ウェハ面内で140
℃で均一な加熱処理をするために、図7に示すような相
関関係を用いた。
A plurality of (for example, three) concentric heaters 61, 62, 63 having different diameters are provided on the back side of the circular hot plate 60, and each heater is a thermocouple embedded in the hot plate 60 (see FIG. (Not shown), each of which is independently temperature-controlled. The wafer 50 is set on the front side of the hot plate 60. To prevent contamination of the back surface of the wafer due to contact with the hot plate 60, a proximity gap 55 is provided at the outer peripheral portion.
(0.1 mm). 140 in wafer plane
In order to perform a uniform heat treatment at a temperature of ° C., a correlation as shown in FIG. 7 was used.

【0037】図7は、ウェハ50と熱板60との距離が
変化したときに、ウェハ処理温度が140℃となるため
に必要な熱板設定温度の関係を示したものである。ウェ
ハ反り量dが0のとき、ウェハ50と熱板60との距離
はプロキシミティギャップ55の0.1mmとなり、熱
板設定温度は140℃となる。ウェハ50の反りが凹形
状の場合、ウェハ反り量dが大きいほどウェハ50と熱
板60との距離は狭くなるため、例えば前記図4で示す
ウェハ反り量d=20μmの領域(図6のヒータ62に
該当)では、139.75℃と従来の設定温度である1
40℃より低く設定し、またd=40μmの領域(ヒー
タ63に該当)では、139.55℃とさらに温度を低
く設定した(ステップ6)。
FIG. 7 shows the relationship between the hot plate set temperature required for the wafer processing temperature to reach 140 ° C. when the distance between the wafer 50 and the hot plate 60 changes. When the wafer warpage d is 0, the distance between the wafer 50 and the hot plate 60 is 0.1 mm of the proximity gap 55, and the hot plate set temperature is 140 ° C. When the warpage of the wafer 50 is concave, the distance between the wafer 50 and the hot plate 60 decreases as the wafer warpage d increases, so that, for example, the region where the wafer warpage d = 20 μm shown in FIG. 62 corresponds to 139.75 ° C., which is the conventional set temperature of 1
The temperature was set lower than 40 ° C., and in the region of d = 40 μm (corresponding to the heater 63), the temperature was further set to 139.55 ° C. (step 6).

【0038】露光後、ウェハ50をインターフェースユ
ニット30を介してレジスト処理装置20に戻し、さら
に搬送ユニットでPEBユニット26に搬送し、前記の
方法によって定められた加熱条件で、PEBと呼ばれる
露光後のベーク処理を140℃,90秒の条件で行った
(ステップ7)。このように、予め計測されたウェハ反
り量から、ウェハ50と熱板60との距離に応じて熱板
60の各ヒータの設定温度を決定することで、ウェハ面
内の温度均一性(3σ)は0.72℃から0.23℃に
まで改善した。
After the exposure, the wafer 50 is returned to the resist processing apparatus 20 via the interface unit 30 and is further transported to the PEB unit 26 by the transport unit. Baking treatment was performed at 140 ° C. for 90 seconds (step 7). As described above, by determining the set temperature of each heater of the hot plate 60 according to the distance between the wafer 50 and the hot plate 60 from the previously measured wafer warpage amount, the temperature uniformity (3σ) within the wafer surface is determined. Improved from 0.72 ° C. to 0.23 ° C.

【0039】次いで、ウェハ50を冷却ユニット(図示
せず)で室温近傍まで冷却した後、現像ユニット27で
90秒間のアルカリ現像処理を行った(ステップ8)。
現像処理終了後、リンス処理、スピン乾燥処理を行い、
ウェハ50をウェハステーション21にまで搬送した。
Next, the wafer 50 was cooled to near room temperature by a cooling unit (not shown), and an alkali developing process was performed for 90 seconds in the developing unit 27 (step 8).
After the development process, perform rinsing process and spin drying process,
The wafer 50 was transferred to the wafer station 21.

【0040】現像後のレジスト寸法をウェハ面内で測定
した結果、回路パターンの1つである180nmのライ
ン&スペースパターンの面内均一性は設定温度を最適化
していないPEB処理条件でレジストパターン形成を行
ったときの14.1nm(3σ)に比べ、6.4nmと
大幅に改善することができた。また、処理するウェハ毎
に反りの分布や量が異なっていても、それぞれのウェハ
に応じた加熱条件でPEB処理を行うので、ウェハ間の
寸法均一性も改善することができた。
As a result of measuring the dimension of the resist after development in the wafer surface, the in-plane uniformity of the 180 nm line & space pattern, which is one of the circuit patterns, was determined under the PEB processing conditions where the set temperature was not optimized. Was greatly improved to 6.4 nm as compared with 14.1 nm (3σ) when the above was performed. Further, even if the distribution and the amount of the warp are different for each wafer to be processed, the dimensional uniformity between the wafers can be improved because the PEB processing is performed under the heating condition according to each wafer.

【0041】(第2の実施形態)第1の実施形態ではウ
ェハ加熱における面内ばらつきを無くすようにしたが、
本実施形態はウェハ間のばらつきを無くすようにしたも
のである。
(Second Embodiment) In the first embodiment, in-plane variations in wafer heating are eliminated.
The present embodiment is designed to eliminate variations between wafers.

【0042】図8は、本実施形態に使用した熱板の構成
を示す図であり、(a)は断面図、(b)は平面図であ
る。第1の実施形態では3つの同心円ヒータ61,6
2,63からなるベークユニットを用いたが、本実施形
態では単一のヒータ61のみを用いた。
FIGS. 8A and 8B are diagrams showing the configuration of the hot plate used in the present embodiment, wherein FIG. 8A is a sectional view and FIG. 8B is a plan view. In the first embodiment, three concentric heaters 61, 6
Although a bake unit composed of 2 and 63 was used, only a single heater 61 was used in this embodiment.

【0043】本実施形態のように単一のヒータ61を熱
源に持つ加熱装置では、その構造上ウェハ面内でのヒー
タ温度補正は不可能であるが、ウェハ50と熱板60と
の距離をウェハ面内で平均化し、その距離に基づき設定
温度をウェハ毎に変更することは可能である。これによ
り、供給熱量のウェハ間ばらつきを低減することができ
る。
In the heating apparatus having a single heater 61 as a heat source as in the present embodiment, the heater temperature cannot be corrected within the wafer surface due to its structure, but the distance between the wafer 50 and the hot plate 60 must be increased. It is possible to average over the wafer surface and change the set temperature for each wafer based on the distance. This makes it possible to reduce the variation in the amount of supplied heat between wafers.

【0044】なお、本発明は上述した各実施形態に限定
されるものではない。実施形態では、3つの同心円ヒー
タ、又は単一のヒータからなるベークユニットを用いた
が、ヒータ数、ヒータ形状はこれに限定されるものでは
なく、仕様に応じて適宜変更可能である。さらに、ヒー
タは必ずしも同心円状に限るものではなく、熱板表面側
で面内方向に温度差を形成できるように複数に分離され
たものであればよい。
The present invention is not limited to the above embodiments. In the embodiment, a bake unit including three concentric heaters or a single heater is used. However, the number of heaters and the heater shape are not limited thereto, and can be appropriately changed according to specifications. Further, the heater is not necessarily limited to a concentric shape, but may be any heater that is separated into a plurality of pieces so that a temperature difference can be formed in the in-plane direction on the hot plate surface side.

【0045】また、本実施形態では、バキュームチャッ
クの圧力分布を基にウェハの反り量を算出したが、これ
に限定されるものではない。例えば、図9に示すよう
に、露光装置10内でウェハの高さ位置を検出するため
のZセンサ80を用い、このセンサ80で得られたデー
タを基にウェハの反り量を算出してもよい。また、ウェ
ハ裏面側に単色光を照射し、その干渉縞に基づきウェハ
の反り量を算出してもよい。
In the present embodiment, the amount of warpage of the wafer is calculated based on the pressure distribution of the vacuum chuck, but the present invention is not limited to this. For example, as shown in FIG. 9, even if a Z sensor 80 for detecting the height position of a wafer is used in the exposure apparatus 10 and the amount of warpage of the wafer is calculated based on data obtained by the sensor 80, Good. Alternatively, the back surface of the wafer may be irradiated with monochromatic light, and the amount of warpage of the wafer may be calculated based on the interference fringes.

【0046】また、実施形態では、凹形状に反ったウェ
ハの場合を示したが、凸形状のウェハでも前記の加熱条
件設定方法を用いることで、同様の効果が得られる。ま
た、実施形態では、ウェハの反り量をPEBの加熱条件
にフィードフォワードしたが、必ずしもこれに限定され
るものではない。PEB以外の加熱処理前にウェハの反
り量を測定し、反射防止膜やレジストの塗布後に行う加
熱処理にフィードフォワードしてもよい。
Further, in the embodiment, the case where the wafer is warped in a concave shape is shown. However, the same effect can be obtained by using the above-described heating condition setting method even in a wafer having a convex shape. Further, in the embodiment, the amount of warpage of the wafer is fed forward under the PEB heating condition, but the present invention is not limited to this. The amount of warpage of the wafer may be measured before the heat treatment other than PEB, and the wafer may be fed forward to the heat treatment performed after application of the antireflection film or the resist.

【0047】その他、本発明の要旨を逸脱しない範囲
で、種々変形して実施することができる。
In addition, various modifications can be made without departing from the spirit of the present invention.

【0048】[0048]

【発明の効果】以上詳述したように本発明によれば、被
加工基板をPEB加熱処理する工程よりも前に基板の反
り量を計測し、PEB加熱処理工程では、計測した反り
量に応じて熱板による供給熱量を制御することにより、
被加工基板が反っていても、均一性の優れた加熱処理を
行うことができる。このため、被加工基板上に形成され
るレジストパターン寸法の基板面内の寸法バラツキを低
減することができる。これにより、その後の工程を経て
作製されるデバイスの信頼性及び製造歩留まりの向上を
はかることが可能となる。
As described above in detail, according to the present invention, the amount of warpage of a substrate is measured before the step of subjecting the substrate to be subjected to the PEB heat treatment. By controlling the amount of heat supplied by the hot plate,
Even when the substrate to be processed is warped, heat treatment with excellent uniformity can be performed. For this reason, it is possible to reduce the dimensional variation in the dimension of the resist pattern formed on the substrate to be processed in the substrate surface. As a result, it is possible to improve the reliability and the manufacturing yield of devices manufactured through the subsequent steps.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1の実施形態に係わる半導体製造システムを
模式的に示す構成図。
FIG. 1 is a configuration diagram schematically showing a semiconductor manufacturing system according to a first embodiment.

【図2】第1の実施形態におけるレジストパターン形成
プロセスを説明するためのフローチャート。
FIG. 2 is a flowchart for explaining a resist pattern forming process in the first embodiment.

【図3】バキュームチャックの圧力分布を求める方法を
説明するためのもので、ステージ構成を示す平面図と断
面図、及びバキュームチャック時の圧力変化を示す図。
FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating a stage configuration, illustrating a method for obtaining a pressure distribution of a vacuum chuck, and a diagram illustrating a pressure change during the vacuum chuck.

【図4】ウェハ反り量の等高線図及びウェハが反った様
子を模式的に示した断面図。
FIG. 4 is a contour diagram of the amount of warpage of the wafer and a cross-sectional view schematically showing a state in which the wafer is warped.

【図5】露光装置内で得られたバキュームチャック圧か
らウェハ反り量を算出し、これをPEBユニットヘフィ
ードフォワードする様子を模式的に示した図。
FIG. 5 is a diagram schematically illustrating a state in which a wafer warpage amount is calculated from a vacuum chuck pressure obtained in an exposure apparatus, and the calculated amount is fed forward to a PEB unit.

【図6】ベークユニットの構成を示す断面図と平面図。FIG. 6 is a cross-sectional view and a plan view illustrating a configuration of a bake unit.

【図7】ウェハを140℃に加熱する際に必要な熱板温
度条件を示した図。
FIG. 7 is a view showing a hot plate temperature condition required when a wafer is heated to 140 ° C.

【図8】第2の実施形態を説明するためのもので、単独
ヒータを有するベークユニットの構成を示す断面図と平
面図。
FIGS. 8A and 8B are a cross-sectional view and a plan view illustrating a configuration of a bake unit having a single heater, for explaining the second embodiment.

【図9】本発明の変形例を説明するための図。FIG. 9 is a diagram illustrating a modification of the present invention.

【符号の説明】[Explanation of symbols]

10…露光装置 20…レジスト処理装置 21…ウェハステーション 22,23…塗布ユニット(COT1,2) 24,25…ベークユニット(HP1,2) 26…ベークユニット(HP3:PEBユニット) 27…現像ユニット(EDV) 30…インターフェースユニット 40…ウェハステージ 41…溝 42…圧力センサ 50…ウェハ(被加工基板) 60…熱板 61,62,63…ヒータ 65…ヒータ制御部 DESCRIPTION OF SYMBOLS 10 ... Exposure apparatus 20 ... Resist processing apparatus 21 ... Wafer station 22, 23 ... Coating unit (COT1, 2) 24, 25 ... Bake unit (HP1, 2) 26 ... Bake unit (HP3: PEB unit) 27 ... Development unit ( EDV) 30 interface unit 40 wafer stage 41 groove 42 pressure sensor 50 wafer (substrate to be processed) 60 hot plate 61, 62, 63 heater 65 heater control unit

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 2H096 AA25 BA20 CA14 FA01 FA10 GA29 GB03 JA03 LA16 LA30 5F046 AA17 CC08 CC10 CC11 CD01 CD05 DA05 DA29 DB06 DC11 KA04 LA18  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H096 AA25 BA20 CA14 FA01 FA10 GA29 GB03 JA03 LA16 LA30 5F046 AA17 CC08 CC10 CC11 CD01 CD05 DA05 DA29 DB06 DC11 KA04 LA18

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】被加工基板上にレジスト膜を形成する工程
と、前記レジスト膜に所望パターンを露光する工程と、
前記レジスト膜にパターンが露光された基板を熱板上に
載置して加熱処理する工程と、前記加熱処理されたレジ
スト膜に現像処理を施す工程とを含むレジストパターン
形成方法において、 前記加熱処理する工程よりも前に前記被加工基板の反り
量を計測し、前記被加工基板を加熱処理する工程で、前
記計測した反り量に応じて前記熱板による供給熱量を制
御することを特徴とするレジストパターン形成方法。
A step of forming a resist film on a substrate to be processed; a step of exposing a desired pattern to the resist film;
A method of forming a resist pattern, comprising: placing a substrate having a pattern exposed on the resist film on a hot plate and performing a heat treatment; and performing a development process on the heat-treated resist film. Measuring the amount of warpage of the substrate to be processed before performing the step of heating, and controlling the amount of heat supplied by the hot plate in accordance with the measured amount of warpage in the step of heating the substrate to be processed. A method for forming a resist pattern.
【請求項2】前記熱板による供給熱量を制御する手段と
して、前記熱板の基板載置面における前記被加工基板と
前記熱板との距離が長いほど供給熱量が多くなるよう
に、前記熱板の温度を面内方向で変えることを特徴とす
る請求項1記載のレジストパターン形成方法。
2. A means for controlling the amount of heat supplied by the hot plate, such that the longer the distance between the substrate to be processed and the hot plate on the substrate mounting surface of the hot plate, the larger the amount of heat supplied. 2. The method according to claim 1, wherein the temperature of the plate is changed in an in-plane direction.
【請求項3】前記熱板による供給熱量を制御する手段と
して、前記被加工基板の反り量が大きいほど前記熱板に
よるトータルの供給熱量を多くするように、前記熱板の
温度を制御することを特徴とする請求項1記載のレジス
トパターン形成方法。
3. A means for controlling the amount of heat supplied by the hot plate, wherein the temperature of the hot plate is controlled such that the larger the amount of warpage of the substrate to be processed, the greater the total amount of heat supplied by the hot plate. 2. The method for forming a resist pattern according to claim 1, wherein:
【請求項4】前記被加工基板の反り量を計測する手段と
して、前記レジスト膜に所望パターンを露光するための
露光装置内で、前記被加工基板をステージ上に固定する
ための真空チャック圧の面内分布を求め、この分布に基
づいて反り量を算出することを特徴とする請求項1〜3
の何れかに記載のパターン形成方法。
4. A vacuum chuck pressure for fixing the substrate to be processed on a stage in an exposure apparatus for exposing a desired pattern on the resist film as means for measuring the amount of warpage of the substrate to be processed. The in-plane distribution is obtained, and the amount of warpage is calculated based on the distribution.
The pattern forming method according to any one of the above.
【請求項5】被加工基板上にレジスト膜を形成するレジ
スト塗布装置と、前記レジスト膜が形成された被加工基
板に対して所望パターンを露光する露光装置と、前記パ
ターンが露光された被加工基板を熱板上に載置して加熱
処理する加熱装置と、前記加熱処理された被加工基板に
対して現像処理を施す現像装置と、前記被加工基板を前
記各装置間で搬送する搬送機構と、前記被加工基板の反
り量を計測する手段とを備えた半導体製造システムであ
って、 前記加熱装置は、前記計測手段により計測された基板の
反り量に基づいて、前記熱板の基板載置面における前記
被加工基板と前記熱板との距離が長いほど供給熱量が多
くなるように、前記熱板の面内方向の温度分布を制御す
るものであることを特徴とする半導体製造システム。
5. A resist coating apparatus for forming a resist film on a substrate to be processed, an exposure apparatus for exposing a desired pattern on the substrate on which the resist film is formed, and a processing apparatus on which the pattern is exposed. A heating device that places a substrate on a hot plate and performs a heating process; a developing device that performs a developing process on the heated processed substrate; and a transport mechanism that transports the processed substrate between the devices. And a means for measuring the amount of warpage of the substrate to be processed, wherein the heating device is configured to mount the hot plate on the substrate based on the amount of warpage of the substrate measured by the measuring means. A semiconductor manufacturing system, wherein the temperature distribution in the in-plane direction of the hot plate is controlled such that the longer the distance between the substrate to be processed and the hot plate on the mounting surface, the larger the amount of heat supplied.
【請求項6】被加工基板上にレジスト膜を形成するレジ
スト塗布装置と、前記レジスト膜が形成された被加工基
板に対して所望パターンを露光する露光装置と、前記パ
ターンが露光された被加工基板を熱板上に載置して加熱
処理する加熱装置と、前記加熱処理された被加工基板に
対して現像処理を施す現像装置と、前記被加工基板を前
記各装置間で搬送する搬送機構と、前記被加工基板の反
り量を計測する手段とを備えた半導体製造システムであ
って、 前記加熱装置は、前記計測手段により計測された基板の
反り量に基づいて、反り量が大きいほどトータルの供給
熱量が多くなるように前記熱板の温度を制御するもので
あることを特徴とする半導体製造システム。
6. A resist coating apparatus for forming a resist film on a substrate to be processed, an exposure apparatus for exposing a desired pattern on the substrate on which the resist film is formed, and a processing apparatus for exposing the pattern. A heating device that places a substrate on a hot plate and performs a heating process; a developing device that performs a developing process on the heated processed substrate; and a transport mechanism that transports the processed substrate between the devices. And a means for measuring the amount of warpage of the substrate to be processed, wherein the heating device, based on the amount of warpage of the substrate measured by the measuring means, the larger the amount of warpage, the greater the total Wherein the temperature of the hot plate is controlled so that the amount of supplied heat increases.
【請求項7】前記被加工基板の反り量を計測する手段
は、前記露光装置内で前記被加工基板をステージ上に固
定するための真空チャック機構に、真空チャック圧の面
内分布を検出する機能を設け、検出された面内分布に従
って反り量を算出するものであることを特徴とする請求
項5又は6に記載の半導体製造システム。
7. A means for measuring an amount of warpage of a substrate to be processed detects an in-plane distribution of a vacuum chuck pressure in a vacuum chuck mechanism for fixing the substrate to be processed on a stage in the exposure apparatus. 7. The semiconductor manufacturing system according to claim 5, wherein a function is provided to calculate a warpage amount according to the detected in-plane distribution.
【請求項8】前記加熱装置の熱板は、径の異なる複数の
同心環状ヒータを有し、各々のヒータが独立に温度制御
可能であることを特徴とする請求項5記載の半導体製造
システム。
8. The semiconductor manufacturing system according to claim 5, wherein the heating plate of the heating device has a plurality of concentric annular heaters having different diameters, and each heater can independently control the temperature.
JP2000087399A 2000-03-27 2000-03-27 Resist pattern forming method and semiconductor manufacturing system Expired - Fee Related JP3708786B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000087399A JP3708786B2 (en) 2000-03-27 2000-03-27 Resist pattern forming method and semiconductor manufacturing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000087399A JP3708786B2 (en) 2000-03-27 2000-03-27 Resist pattern forming method and semiconductor manufacturing system

Publications (3)

Publication Number Publication Date
JP2001274069A true JP2001274069A (en) 2001-10-05
JP2001274069A5 JP2001274069A5 (en) 2004-12-16
JP3708786B2 JP3708786B2 (en) 2005-10-19

Family

ID=18603413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000087399A Expired - Fee Related JP3708786B2 (en) 2000-03-27 2000-03-27 Resist pattern forming method and semiconductor manufacturing system

Country Status (1)

Country Link
JP (1) JP3708786B2 (en)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006135080A (en) * 2004-11-05 2006-05-25 Toshiba Corp Pattern formation method
WO2006087938A1 (en) * 2005-02-15 2006-08-24 Tokyo Electron Limited Temperature setting method for heat treating plate, temperature setting device for heat treating plate, program and computer-readable recording medium recording program
JP2007520082A (en) * 2004-01-30 2007-07-19 東京エレクトロン株式会社 Real-time control of reticle / mask system
JP2007300047A (en) * 2006-05-08 2007-11-15 Tokyo Electron Ltd Heat treatment method, program and heat treatment apparatus
JP2007317732A (en) * 2006-05-23 2007-12-06 Tokyo Electron Ltd Heat treatment plate temperature control method, program, and heat treatment plate temperature control device
WO2008023693A1 (en) * 2006-08-24 2008-02-28 Tokyo Electron Limited Coating developing machine, resist pattern forming device, coating developing method, resist pattern forming method, and storage medium
JP2008177303A (en) * 2007-01-17 2008-07-31 Tokyo Electron Ltd Substrate processing apparatus, substrate processing method, and storage medium
JP2010066852A (en) * 2008-09-09 2010-03-25 Omron Corp Method of tuning control parameter
JP2011059489A (en) * 2009-09-11 2011-03-24 Nikon Corp Substrate treatment method and substrate treatment apparatus
EP2365728A1 (en) 2010-03-11 2011-09-14 Omron Corporation Temperature control system and temperature control method
US8073316B2 (en) 2008-01-31 2011-12-06 Kabushiki Kaisha Toshiba Oven for semiconductor wafer
JP2017050349A (en) * 2015-08-31 2017-03-09 キヤノン株式会社 Imprint device, imprint method, and method for manufacturing article
JP2017069517A (en) * 2015-10-02 2017-04-06 東京エレクトロン株式会社 Substrate processing apparatus, substrate processing method and storage medium
WO2018003372A1 (en) * 2016-06-27 2018-01-04 東京エレクトロン株式会社 Substrate processing device, substrate processing method, and storage medium
WO2019244782A1 (en) * 2018-06-22 2019-12-26 東京エレクトロン株式会社 Substrate processing device, substrate processing method, and storage medium
JP2020035834A (en) * 2018-08-28 2020-03-05 キオクシア株式会社 Heat treatment apparatus and heat treatment method
CN111801772A (en) * 2018-03-12 2020-10-20 东京毅力科创株式会社 Substrate warpage correction method, computer storage medium and substrate warpage correction device
CN112420591A (en) * 2019-08-20 2021-02-26 长鑫存储技术有限公司 Heating plate and method for controlling surface temperature of wafer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09180994A (en) * 1995-10-26 1997-07-11 Mitsubishi Electric Corp X-ray mask manufacturing method and heating device
JPH10199947A (en) * 1997-01-13 1998-07-31 Tera Tec:Kk Method and apparatus for measuring warp of thin sheet
JPH118180A (en) * 1997-06-17 1999-01-12 Sony Corp Baking equipment
JPH1154398A (en) * 1997-07-30 1999-02-26 Hitachi Ltd Exposure apparatus, exposure method, and method of manufacturing semiconductor integrated circuit device using the same
JPH11274030A (en) * 1998-03-20 1999-10-08 Hitachi Ltd Resist processing method and apparatus and resist coating method
JPH11329940A (en) * 1998-05-20 1999-11-30 Tokyo Electron Ltd Heat treatment equipment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09180994A (en) * 1995-10-26 1997-07-11 Mitsubishi Electric Corp X-ray mask manufacturing method and heating device
JPH10199947A (en) * 1997-01-13 1998-07-31 Tera Tec:Kk Method and apparatus for measuring warp of thin sheet
JPH118180A (en) * 1997-06-17 1999-01-12 Sony Corp Baking equipment
JPH1154398A (en) * 1997-07-30 1999-02-26 Hitachi Ltd Exposure apparatus, exposure method, and method of manufacturing semiconductor integrated circuit device using the same
JPH11274030A (en) * 1998-03-20 1999-10-08 Hitachi Ltd Resist processing method and apparatus and resist coating method
JPH11329940A (en) * 1998-05-20 1999-11-30 Tokyo Electron Ltd Heat treatment equipment

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101129940B1 (en) 2004-01-30 2012-03-28 도쿄엘렉트론가부시키가이샤 Adaptive real time control of a reticle/mask system
JP2007520082A (en) * 2004-01-30 2007-07-19 東京エレクトロン株式会社 Real-time control of reticle / mask system
JP2006135080A (en) * 2004-11-05 2006-05-25 Toshiba Corp Pattern formation method
WO2006087938A1 (en) * 2005-02-15 2006-08-24 Tokyo Electron Limited Temperature setting method for heat treating plate, temperature setting device for heat treating plate, program and computer-readable recording medium recording program
JP2006228820A (en) * 2005-02-15 2006-08-31 Tokyo Electron Ltd Heat treatment plate temperature setting method, heat treatment plate temperature setting device, program, and computer-readable recording medium recording the program
JP2007300047A (en) * 2006-05-08 2007-11-15 Tokyo Electron Ltd Heat treatment method, program and heat treatment apparatus
JP2007317732A (en) * 2006-05-23 2007-12-06 Tokyo Electron Ltd Heat treatment plate temperature control method, program, and heat treatment plate temperature control device
US8698052B2 (en) 2006-05-23 2014-04-15 Tokyo Electron Limited Temperature control method of heat processing plate, computer storage medium, and temperature control apparatus of heat processing plate
US8242417B2 (en) 2006-05-23 2012-08-14 Tokyo Electron Limited Temperature control method of heat processing plate, computer storage medium, and temperature control apparatus of heat processing plate
WO2008023693A1 (en) * 2006-08-24 2008-02-28 Tokyo Electron Limited Coating developing machine, resist pattern forming device, coating developing method, resist pattern forming method, and storage medium
JP2008177303A (en) * 2007-01-17 2008-07-31 Tokyo Electron Ltd Substrate processing apparatus, substrate processing method, and storage medium
US8073316B2 (en) 2008-01-31 2011-12-06 Kabushiki Kaisha Toshiba Oven for semiconductor wafer
JP2010066852A (en) * 2008-09-09 2010-03-25 Omron Corp Method of tuning control parameter
JP2011059489A (en) * 2009-09-11 2011-03-24 Nikon Corp Substrate treatment method and substrate treatment apparatus
CN102193569A (en) * 2010-03-11 2011-09-21 欧姆龙株式会社 Temperature control system and temperature control method
EP2365728A1 (en) 2010-03-11 2011-09-14 Omron Corporation Temperature control system and temperature control method
JP2017050349A (en) * 2015-08-31 2017-03-09 キヤノン株式会社 Imprint device, imprint method, and method for manufacturing article
JP2017069517A (en) * 2015-10-02 2017-04-06 東京エレクトロン株式会社 Substrate processing apparatus, substrate processing method and storage medium
JPWO2018003372A1 (en) * 2016-06-27 2019-04-11 東京エレクトロン株式会社 Substrate processing apparatus, substrate processing method, and storage medium
WO2018003372A1 (en) * 2016-06-27 2018-01-04 東京エレクトロン株式会社 Substrate processing device, substrate processing method, and storage medium
CN111801772A (en) * 2018-03-12 2020-10-20 东京毅力科创株式会社 Substrate warpage correction method, computer storage medium and substrate warpage correction device
CN111801772B (en) * 2018-03-12 2024-03-22 东京毅力科创株式会社 Substrate warp correction method, computer storage medium, and substrate warp correction device
WO2019244782A1 (en) * 2018-06-22 2019-12-26 東京エレクトロン株式会社 Substrate processing device, substrate processing method, and storage medium
CN112335020A (en) * 2018-06-22 2021-02-05 东京毅力科创株式会社 Substrate processing apparatus, substrate processing method, and storage medium
CN112335020B (en) * 2018-06-22 2024-04-09 东京毅力科创株式会社 Substrate processing device, substrate processing method and storage medium
JP2020035834A (en) * 2018-08-28 2020-03-05 キオクシア株式会社 Heat treatment apparatus and heat treatment method
CN112420591A (en) * 2019-08-20 2021-02-26 长鑫存储技术有限公司 Heating plate and method for controlling surface temperature of wafer
CN112420591B (en) * 2019-08-20 2022-06-10 长鑫存储技术有限公司 Heating plate and method for controlling surface temperature of wafer

Also Published As

Publication number Publication date
JP3708786B2 (en) 2005-10-19

Similar Documents

Publication Publication Date Title
JP3708786B2 (en) Resist pattern forming method and semiconductor manufacturing system
US8138456B2 (en) Heat processing method, computer-readable storage medium, and heat processing apparatus
US7831135B2 (en) Method and system for controlling bake plate temperature in a semiconductor processing chamber
US8669497B2 (en) Apparatus and method for predictive temperature correction during thermal processing
JP5296022B2 (en) Heat treatment method, recording medium recording program for executing heat treatment method, and heat treatment apparatus
JP5610664B2 (en) Method for in-line monitoring and control of heat treatment of resist-coated wafers
US20080257495A1 (en) Temperature setting method for thermal processing plate, temperature setting apparatus for thermal processing plate, and computer-readable storage medium
US8916804B2 (en) Heat treatment method, recording medium having recorded program for executing heat treatment method, and heat treatment apparatus
JP4488867B2 (en) Pattern formation method
JP3755814B2 (en) Heat treatment method and heat treatment apparatus
TWI305932B (en)
TWI260046B (en) Temperature-sensing wafer position detection system and method
US20070166030A1 (en) Semiconductor device fabrication equipment and method of using the same
JP3619876B2 (en) Heat treatment equipment
TWI305934B (en)
US7425689B2 (en) Inline physical shape profiling for predictive temperature correction during baking of wafers in a semiconductor photolithography process
US20060154479A1 (en) Baking apparatus used in photolithography process, and method for controlling critical dimension of photoresist patterns using the same
JPH07142549A (en) Semiconductor manufacturing equipment
US8135487B2 (en) Temperature setting method and apparatus for a thermal processing plate
JP2001274078A (en) Temperature control device, device manufacturing apparatus and device manufacturing method
JP3672529B2 (en) Film quality evaluation method and apparatus, line width variation evaluation method and apparatus, and processing method and apparatus having line width variation evaluation function
JP7433468B2 (en) Warpage amount estimation device and warpage amount estimation method
TW200527494A (en) Exposure processing system, exposure processing method and method for manufacturing a semiconductor device
JPH05299333A (en) Bake processing device
TWI804574B (en) Substrate processing equipment

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040106

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040106

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050708

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050802

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050804

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090812

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090812

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100812

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100812

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110812

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110812

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120812

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120812

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130812

Year of fee payment: 8

LAPS Cancellation because of no payment of annual fees