JP2001267584A - Method of manufacturing substrate for electro-optical device, electro-optical device and electronic apparatus using this substrate - Google Patents

Abstract

(57) [PROBLEMS] To reduce off-leak current of a transistor element using a semiconductor layer separated by mesa by dry etching. SOLUTION: By oxidizing the entire surface or only the side surface of the semiconductor layer separated by mesa by dry etching,
Crystal defects due to plasma damage are separated from the transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a substrate for an electro-optical device having a semiconductor layer formed on a substrate, and to an electro-optical device and an electronic apparatus using the substrate. In particular, the present invention relates to a method for manufacturing an electro-optical device substrate that can reduce off-leakage of a transistor included in a pixel.

[0002]

2. Description of the Related Art An SOI (Silicon On Insulato) in which a semiconductor layer composed of a single crystal silicon layer is formed on an insulating substrate and a semiconductor device such as a transistor is formed on the semiconductor layer.
The technique r) has advantages such as higher speed, lower power consumption, and higher integration of elements, and thus can be applied to an electro-optical device, for example, a support substrate on which a TFT array is formed in a liquid crystal device.

[0003] In a general liquid crystal device using amorphous silicon, there is no particular problem because the off-leak current of a transistor for driving a pixel is small.

[0004]

However, when a pixel transistor is formed using polycrystalline silicon in an electro-optical device such as a liquid crystal device, there is a problem that the off-leak current of the pixel transistor becomes remarkable. If the off-leak current of the pixel transistor is large, it becomes impossible to maintain the voltage applied to the liquid crystal, which causes display defects such as flicker. Increasing the additional capacitance in consideration of the off-leak current leads to a decrease in the aperture ratio in an electro-optical device such as a transmissive liquid crystal device, resulting in a dark display. Therefore, in the conventional polycrystalline silicon TFT, the gate length is increased, or a structure in which a plurality of gate electrodes such as a double gate are connected in series is used to reduce off-leak current. In addition, TFT using single crystal silicon
Is not as remarkable as polycrystalline silicon, but there is an off-leak problem.

In particular, if a high-performance TFT can be formed by using a single-crystal silicon layer to which SOI technology or the like is applied or by using polycrystalline silicon having a higher mobility than the current state, a high-resolution liquid crystal device is required to be manufactured. It can be formed finely. Since the pixel size of a high-resolution / high-definition liquid crystal device is reduced, in an electro-optical device such as a transmissive liquid crystal panel, it is desirable that the size of the pixel transistor be small in order to secure an aperture ratio. This is because it is necessary to make the light-shielding layer as small as possible in order to increase the aperture ratio.

In such a high-resolution and high-definition liquid crystal device, since the aperture ratio is increased as described above, it is impossible to increase the gate length of the pixel transistor or use a double gate structure. Therefore, it is necessary to reduce the off-leak current of the pixel transistor.

When a pixel transistor of single crystal silicon or polycrystal silicon is used in an electro-optical device such as a transmission type liquid crystal device, it is desirable to apply a known mesa isolation technology as an element isolation technology. This is because, compared to the LOCOS isolation technique usually used for MOSFETs using a single-crystal Si substrate, the elements are separated by etching, so that the separation interval can be reduced and the process can be shortened. .

[0008] In the etching of the mesa separation technique, it is desirable to use a dry etching technique in consideration of the dimensional controllability. When the semiconductor layer is separated by wet etching,
Variations in the gate width that determine the performance of the transistor increase, and particularly when a fine pixel transistor is formed, the performance of the pixel transistor varies, which causes display unevenness.

However, in the mesa separation technique by dry etching as described above, plasma damage is introduced to the side surface of the etched semiconductor layer. It is considered that an off-leak current flows through a defect due to such plasma damage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a substrate for an electro-optical device which reduces an off-leak current of a pixel transistor manufactured by a mesa isolation technique. It is in.
It is still another object of the present invention to provide a high-resolution and high-definition electro-optical device and an electronic apparatus using the substrate manufactured by the manufacturing method.

[0011]

In order to achieve the above object, a method of manufacturing a substrate for an electro-optical device according to a first aspect of the present invention comprises a method of manufacturing a substrate for an electro-optical device, the method comprising: On a substrate, a plurality of scan lines, a plurality of data lines intersecting the plurality of scan lines, a transistor connected to each scan line and each data line, and a pixel electrode connected to the transistor A method for manufacturing an electro-optical device substrate, comprising: forming an oxide film on a surface of the semiconductor layer on which the transistor is formed; forming an oxidation prevention film on a surface of the oxide film; Forming a selected region, and removing the oxidation preventing film, the oxide film, and the semiconductor layer in the selected region, wherein at least the semiconductor layer is removed by dry etching; Comprising a, and, by thermally oxidizing the substrate to which the dry etching, it is characterized by comprising the step of thermally oxidizing the side surface of said semiconductor layer exposed by the dry etching.

According to the structure of the present invention, when the semiconductor layer is separated into mesas by dry etching, even if a defect due to plasma damage is introduced into the side surface of the semiconductor layer, the side surface is oxidized. Separated from Therefore, an off-leak current of a pixel transistor due to a crystal defect can be reduced. Further, since the oxide film is formed between the semiconductor layer and the oxidation preventing film, the corner of the upper end of the semiconductor layer can be rounded when the side surface is oxidized. Therefore, an effect of preventing generation of a parasitic MOSFET at an upper end portion of the semiconductor layer having a threshold voltage lower than the original threshold voltage of the pixel transistor can be obtained.

In order to achieve the above object, a method of manufacturing a substrate for an electro-optical device according to the second aspect of the present invention comprises at least
A plurality of scanning lines, a plurality of data lines intersecting the plurality of scanning lines, a plurality of data lines intersecting the plurality of scanning lines, A method for manufacturing a substrate for an electro-optical device having a connected transistor and a pixel electrode connected to the transistor, the method comprising: forming a selected region on the semiconductor layer using a photomask; An electro-optical device comprising: a step of removing a layer by dry etching; and a step of thermally oxidizing the dry-etched substrate; and a step of removing the thermally oxidized oxide film by wet etching. Method of manufacturing substrates.

According to the structure of the present invention, when the semiconductor layer is separated into mesas by dry etching, even if a defect due to plasma damage is introduced into the side surface of the semiconductor layer, the semiconductor layer is oxidized and the oxidized portion is wetted. Since it is removed by etching, a defective portion is not introduced into the pixel transistor. Therefore, an off-leak current of a pixel transistor due to a crystal defect can be reduced.

In the method of manufacturing a substrate for an electro-optical device according to the present invention, it is preferable that the oxidation preventing film is a silicon nitride film. With such a configuration, an oxidation prevention film can be formed using a general mass-production type film forming apparatus such as plasma CVD, and the process consistency is high.

On the other hand, in the method of manufacturing a substrate for an electro-optical device according to the present invention, it is preferable that the supporting substrate is a transparent substrate. According to the configuration of the present invention, since the substrate is a transparent substrate, a transmission type liquid crystal device can be manufactured.

In the method of manufacturing an electro-optical device according to the present invention, it is preferable that the support substrate is a quartz substrate. According to the configuration of the present invention, since the substrate is a quartz substrate, T
In manufacturing FT, a high temperature process up to about 1150 degrees Celsius can be applied. Therefore, a high-performance TFT can be obtained.

Subsequently, in the method of manufacturing an electro-optical device according to the present invention, it is preferable that the semiconductor layer is made of single crystal silicon. According to such a configuration, the driving frequency can be increased by using single crystal silicon, and a high-quality, high-definition liquid crystal device can be obtained.

In the method of manufacturing an electro-optical device according to the present invention, it is preferable that the semiconductor layer is made of polycrystalline silicon. According to the configuration of the present invention, it is possible to obtain a high-definition liquid crystal display device at low cost by using polycrystalline silicon.

Next, in the electro-optical device according to the present invention, it is preferable that a light-shielding layer is further provided between the substrate and the semiconductor layer. According to the structure of the present invention, it is possible to prevent light incident directly from the back surface of the substrate or light reflected on the back surface of the substrate from entering the transistor element formation region and to cause light leakage, and to improve signal writing characteristics to pixels. Deterioration can be prevented.

Further, the electro-optical device according to the present invention is characterized in that the substrate manufactured by the manufacturing method according to the present invention has the other substrate disposed so as to face the surface of the one substrate on which the semiconductor layer is formed; Sandwiched between one and the other substrate,
And a liquid crystal driven by a transistor formed in the semiconductor layer.

The electronic apparatus according to the present invention includes a light source, the electro-optical device for receiving light emitted from the light source and performing modulation corresponding to image information, and the light modulated by the electro-optical device. And projection means for projecting.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

(Configuration of Electro-Optical Device) FIG. 1 is a diagram showing an equivalent circuit of an image forming area in a liquid crystal device as an electro-optical device according to an embodiment of the present invention. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films and the like are formed, and FIG. It is A 'sectional drawing. In FIGS. 2 and 3, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawings.

In FIG. 1, a plurality of pixels constituting an image display area of the liquid crystal device according to the present embodiment include a pixel electrode 9a formed in a matrix and a pixel electrode 9a.
And a data line 6a to which an image signal is supplied is connected to the TF.
It is electrically connected to the source of T30. Data line 6
The image signals S1, S2,..., Sn written to a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. .

The scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulsed manner in this order at a predetermined timing. It is configured to be. The pixel electrode 9a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30, which is a switching element, for a certain period, the image signals S1, S2,... Write at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are:
It is held for a certain period between a counter electrode (to be described later) formed on a counter substrate (to be described later).

The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level.
Enables gradation display. In the normally white mode, the incident light cannot pass through the liquid crystal portion according to the applied voltage. In the normally black mode, the incident light passes through the liquid crystal portion according to the applied voltage. The liquid crystal device emits light having a contrast corresponding to the image signal as a whole. Here, in order to prevent the held image signal from leaking, the pixel electrode 9 is used.
A storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the capacitor a and the counter electrode. Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized. In the present embodiment, in particular, in order to form such a storage capacitor 70, a capacitor line 3b having the same resistance as the scanning line or having a low resistance using a conductive light-shielding film is provided as described later. .

Next, FIG. 2 is a plan view showing the configuration of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films and the like are formed. In FIG. 2, on a TFT array substrate of a liquid crystal device, a plurality of transparent pixel electrodes 9a (indicated by dotted lines) are provided in a matrix, and are arranged along the vertical and horizontal boundaries of the pixel electrodes 9a. In addition, a data line 6a, a scanning line 3a, and a capacitance line 3b are provided. this house,
The data line 6a is electrically connected to a source region to be described later in the semiconductor layer 1a such as a single crystal silicon layer via the contact hole 5, and the pixel electrode 9a is connected to the semiconductor layer via the contact hole 8. 1a is electrically connected to the drain region. Further, in the semiconductor layer 1a,
The scanning line 3a is arranged to face the channel region, and the scanning line 3a functions as a gate electrode.

Subsequently, the capacitance line 3b includes a main line portion extending substantially linearly along the scanning line 3a (that is, a first region formed along the scanning line 3a in plan view) and a data line. 6
a protruding portion (that is, upward in the figure) protruding from the location intersecting the data line 6a to the front stage side (upward in the figure)
(A second region extending along the data line 6a).

Although not shown in the figure, a plurality of first light-shielding films (first light-shielding films 11a in FIG. 3) are provided below the region where the semiconductor layer 1a is formed in FIG. More specifically, the first light-shielding film is provided at a position where the first light-shielding film covers the TFT including the channel region of the semiconductor layer 1a in the pixel portion as viewed from the TFT array substrate side.
A main line portion that extends linearly along the scanning line 3a opposite to the main line portion of the capacitor line 3b, and a step side (ie, downward in the drawing) adjacent to the data line 6a from a portion that intersects the data line 6a. And a protruding projection. The tip of the downward protrusion in each step (pixel row) of the first light-shielding film overlaps the tip of the upward protrusion of the capacitor line 3b in the next step below the data line 6a.

Next, as shown in the cross-sectional view of FIG. 3, the liquid crystal device includes a TFT array substrate 10 which is an example of a light-transmitting substrate, and a transparent counter substrate 20 which is disposed to face the TFT array substrate.
And The TFT array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film (not shown in the drawing) on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO film (indium tin oxide film). The alignment film 16 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and an alignment film (a predetermined alignment process such as rubbing process) is formed below the counter electrode (common electrode). (Not shown). The counter electrode 21
For example, it is made of a transparent conductive thin film such as an ITO film. The alignment film is made of an organic thin film such as a polyimide thin film.

As shown in FIG. 3, the TFT array substrate 10 is provided with a pixel switching TFT 30 for controlling the switching of each pixel electrode 9a at a position adjacent to each pixel electrode 9a.

As shown in FIG. 3, the opposing substrate 20 is further provided with a second light-shielding film 23 in a region other than the opening region of each pixel portion. For this reason, incident light from the side of the counter substrate 20 is transmitted to the channel region 1 a ′ of the semiconductor layer 1 a of the pixel switching TFT 30 or an LDD (Lightly Doped Drain).
It does not enter the regions 1b and 1c. Further, the second light-shielding film 23 has functions such as improvement of contrast and prevention of color mixture of color materials.

The sealing member (not shown) surrounds the space between the TFT array substrate 10 and the counter substrate 20, which are configured as described above and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other. Liquid crystal is sealed in the space, and a liquid crystal layer 50 is formed.
Is formed. The liquid crystal layer 50 includes the alignment film 16 and the opposing substrate 20 when no electric field is applied from the pixel electrode 9a.
A predetermined alignment state is taken by the alignment film on the side. Liquid crystal layer 50
Is composed of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is used for bonding the TFT array substrate 10 and the opposing substrate 20 around them.
For example, it is an adhesive made of a photocurable resin or a thermosetting resin, and a spacer such as glass fiber or glass bead for mixing the distance between the two substrates to a predetermined value is mixed.

As shown in FIG. 3, the TFTs 30 are located at positions facing the pixel switching TFTs 30, respectively.
TFT 30 for switching each pixel on the surface of array substrate 10
The first light-shielding films 11a are provided at positions corresponding to. Here, the first light shielding film 11a is preferably made of an opaque high melting point metal such as Ti, Cr, W, Ta, Mo, and P.
It is composed of a metal simple substance, an alloy, a metal silicide or the like containing at least one of b. With such a material, the first light-shielding film 11 a on the TFT array substrate 10 can be formed.
TFT 3 for pixel switching performed after the formation process of
0, the first light-shielding film 11
a can be prevented from being broken or melted. Since the first light-shielding film 11a is formed, the TFT array substrate 10
Can be prevented from entering the channel region 1a 'and the LDD regions 1b and 1c of the pixel switching TFT 30 beforehand, and the characteristics of the pixel switching TFT 30 as a transistor element due to generation of a photocurrent can be prevented. Does not deteriorate.

Further, a first interlayer insulating film 12 is provided between the first light shielding film 11a and the plurality of pixel switching TFTs 30.
Is provided. The first interlayer insulating film 12 is provided for electrically insulating the semiconductor layer 1a constituting the pixel switching TFT 30 from the first light-shielding film 11a. Further, the first interlayer insulating film 12 is formed on the TFT array substrate 1.
By being formed on the entire surface of 0, it also has a function as a base film for the pixel switching TFT 30. That is, the pixel switching TFT 3 may be roughened during polishing of the surface of the TFT array substrate 10 or stains remaining after cleaning.
0 has the function of preventing the deterioration of the characteristic. Here, the first
The interlayer insulating film 12 is made of, for example, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), B
It is made of a highly insulating glass such as SG (boron silicate glass) or BPSG (boron phosphorus silicate glass), or a silicon oxide film, a silicon nitride film, or the like. The first interlayer insulating film 12 can prevent the first light-shielding film 11a from contaminating the pixel switching TFT 30 and the like.

In the present embodiment, the gate insulating film 2 is used as a dielectric film by extending from a position facing the scanning line 3a.
The storage capacitor 70 is formed by extending the semiconductor film 1a to form a first storage capacitor electrode 1f, and further forming a part of the capacitor line 3b opposed thereto as a second storage capacitor electrode.
More specifically, the high concentration drain region 1e of the semiconductor layer 1a
Are arranged opposite to each other via the insulating film 2 to the portion of the capacitance line 3b extending along the data line 6a and the scanning line 3a, and serve as a first storage capacitance electrode (semiconductor layer) 1f. In particular, since the insulating film 2 as a dielectric of the storage capacitor 70 is nothing but the gate insulating film 2 of the TFT 30 formed on the silicon layer by high-temperature oxidation, it can be a thin and high withstand voltage insulating film. 70 can be configured as a large-capacity storage capacitor with a relatively small area.

Further, as can be seen from FIG. 3, the first light-shielding film 11a is provided on the first storage capacitor electrode 1f on the opposite side of the capacitor line 3b as the second storage capacitor electrode by the first interlayer insulating film 12a.
Are arranged to face each other as third storage capacitor electrodes. Although not shown, the first light-shielding film 11a is connected to the power supply potential or the capacitance line 3b.
By fixing to a constant potential such as the same potential as above, the storage capacitor 71 is further provided.
That is, in the present embodiment, a double storage capacitor structure in which storage capacitors are provided on both sides of the first storage capacitor electrode 1f is constructed, and the storage capacitance further increases. Therefore, the function of the liquid crystal device for preventing flicker and burn-in in a display image is improved.

As a result, a space outside the opening area, that is, the area under the data line 6a and the area where the liquid crystal disclination occurs along the scanning line 3a (that is, the area where the capacitance line 3b is formed) is effective. To increase the storage capacitance of the pixel electrode 9a.

The first light-shielding film 11a (and the capacitance line 3b electrically connected thereto) is electrically connected to a constant potential source (not shown) outside the pixel region.
The light-shielding film 11a and the capacitance line 3b are set to a constant potential. Accordingly, the fluctuation in the potential of the first light-shielding film 11a does not adversely affect the pixel switching TFT 30 that is disposed to face the first light-shielding film 11a. Further, the capacitance line 3b can function well as a second storage capacitor electrode of the storage capacitor 70.

In this case, as the constant potential source, a constant potential source of a negative power supply or a positive power supply supplied to a peripheral circuit for driving the liquid crystal device (for example, a scanning line driving circuit, a data line driving circuit, or the like). , A ground power source, a constant potential source supplied to the counter electrode 21, and the like. By using a power supply such as a peripheral circuit, the light-shielding film 11a and the capacitor line 3b can be set at a constant potential without providing a dedicated potential wiring or an external input terminal.

The pixel switching TFT 30 is
It has an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a, a channel region 1a 'of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and a scanning line 3
the gate insulating film 2 that insulates the semiconductor layer 1a from the semiconductor layer 1a, the data line 6a, and the low concentration source region (source side L
DD region) 1b and a lightly doped drain region (drain side L
DD region) 1c, high-concentration source region 1d of semiconductor layer 1a
And a high-concentration drain region 1e.

The high-concentration drain region 1e includes:
A corresponding one of the plurality of pixel electrodes 9a is connected. Source regions 1b and 1d and drain region 1c
And 1e are formed by doping a predetermined concentration of P-type impurity ions into the semiconductor layer 1a.
In the P-type transistor having the above structure, since the parasitic bipolar effect is unlikely to occur, it is not necessary to fix the potential of the channel portion. Therefore, when used as the pixel switching TFT 30, a high aperture ratio can be secured.

The data line 6a is formed of a light-shielding metal thin film such as a metal film of Al or the like or an alloy film of metal silicide or the like. On the scanning line 3a, the gate insulating film 2, and the first interlayer insulating film 12, a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e are respectively formed. An interlayer insulating film 4 is formed. Data line 6a is electrically connected to high-concentration source region 1d via contact hole 5 to source region 1b. Further, a third interlayer insulating film 7 having a contact hole 8 to the high-concentration drain region 1e is formed on the data line 6a and the second interlayer insulating film 4. The pixel electrode 9a is electrically connected to the high-concentration drain region 1e via the contact hole 8 to the high-concentration drain region 1e. The aforementioned pixel electrode 9
“a” is provided on the upper surface of the third interlayer insulating film 7 thus configured. The pixel electrode 9a and the high-concentration drain region 1e are connected to the same Al film or the scanning line 3b as the data line 6a.
And the same polysilicon film may be relayed for electrical connection.

The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c, respectively. A self-aligned TFT in which impurity ions are implanted at a high concentration using the electrode 3a as a mask to form self-aligned high-concentration source and drain regions may be used.

Here, in general, the single crystal silicon layers such as the channel region 1a 'of the semiconductor layer 1a, the low-concentration source region 1b and the low-concentration drain region 1c have a photocurrent due to the photoelectric conversion effect of silicon when light enters. Is generated and the transistor characteristics of the pixel switching TFT 30 are deteriorated. However, in the present embodiment, since the data line 6a is formed of a light-shielding metal thin film such as Al so as to cover the scanning line 3a from above, Light can be effectively prevented from entering at least the channel region 1a 'and the LDD regions 1b and 1c of the semiconductor layer 1a. Further, as described above, since the first light shielding film 11a is provided below the pixel switching TFT 30, at least the channel region 1a 'and the low concentration source region 1b of the semiconductor layer 1a,
It is also possible to effectively prevent return light from entering the low-concentration drain region 1c.

Next, the steps from the mesa separation step of the semiconductor layer 1a to the gate oxidation step in the method of manufacturing the TFT array substrate 10 as shown in FIG. 3 will be described with reference to FIG.

The semiconductor layer 1a shown in FIG. 4A is formed by forming a single crystal silicon on a flattened quartz substrate on which a first light shielding layer 11a and a first interlayer insulating film 12 are formed by a known bonding method. I do. Further, in the case of polycrystalline silicon, after forming amorphous silicon by a CVD method or the like, a temperature of 600 ° C.
To 700 ° C. for about 5 hours to about 10 hours, or by heat treatment using excimer laser annealing. The thickness of the semiconductor layer 1a is 5
It is about 0 nm to 300 nm, for example, 80 nm.
Here, for the semiconductor layer 1a, a method for forming single crystal silicon and polycrystalline silicon has been described; however, the present invention is not limited to the above method. Further, a semiconductor other than silicon can be used. Further, the support substrate is not limited to the above quartz substrate.

An oxide film 40 is formed on the semiconductor layer 1a of the TFT array substrate 10 obtained by the above process by thermal oxidation or CVD. This oxide film thickness is 10 nm to 10
It is desirable that the thickness be about 0 nm. Further, a silicon nitride film 41, which is an oxidation prevention film, is formed on the oxide film 40 by a CVD method or the like to obtain the substrate shown in FIG. This silicon nitride film has a thickness of 100 nm to 300 n.
m. Further, the oxidation preventing film is not limited to the silicon nitride film.

Next, a resist pattern is formed by a known photo process. Then, the silicon nitride film 41 and the oxide film 40 are simultaneously removed by fluorine-based dry etching. Subsequently, the substrate shown in FIG. 4C is obtained by dry etching the semiconductor layer 1a and removing the resist. At this time, after removing the silicon nitride film 41 and the oxide film 40, the resist may be removed, and the silicon film 1a may be removed using the silicon nitride film 41 as a hard mask.
Further, the etching gas is not limited to the above, and any dry gas may be used as long as the etching rates of the silicon nitride film 41 and the oxide film 40 are substantially the same. Further, the removal of the silicon nitride film 41 and the oxide film 40 is not limited to dry etching, and wet etching can be used when there is a margin in dimensional accuracy. The dry etching of the semiconductor layer 1a
Any condition can be used as long as the etching selectivity between a and the first interlayer insulating film 12 can be obtained. In the above description, an example of etching the silicon nitride film 41, the oxide film 40, and the semiconductor layer 1a has been described. However, a process of dry-etching three layers at a time or etching the silicon nitride film 41 first to form the oxide film 40 and the semiconductor layer 1a It may be a process of dry-etching 1a at a time.

Next, the TFT array substrate 10 obtained by the above process is oxidized from 50 nm to 300 nm by thermal oxidation at 800 ° C. to 1100 ° C. After the oxidation, the substrate shown in FIG. 4D is obtained by removing the silicon nitride film on the surface. At this time, since the silicon nitride film 41 serving as an oxidation prevention film is provided on the surface, only the side wall portion of the semiconductor layer 1a exposed by the above-described etching is oxidized. (FIG. 4 (d)
By this process, the semiconductor layer 1a
Can be introduced into the oxide film due to plasma damage introduced when patterning is performed by dry etching. Therefore, it is possible to suppress a leak current via a defect in the side wall of the semiconductor layer 1a. An oxide film 4 is provided between the semiconductor layer 1a and the silicon nitride film 41.
0, the surface edge of the semiconductor layer 1a has an effect of rounding the surface edge because the oxide film 40 becomes thick in a bird's peak shape during thermal oxidation. Therefore, MOSFE
Parasitic MO at the surface edge of the semiconductor layer having a threshold voltage lower than the original threshold voltage of the pixel transistor after the formation of the T
The effect of preventing generation of SFET is also obtained.

Hereinafter, since the steps after the gate oxide film forming step are the same as those in the normal MOSFET manufacturing step, the description is omitted here. However, a gate electrode is formed on the gate oxide film,
Source / drain regions are formed by selectively implanting impurity ions into the semiconductor layer 1a.

(Modification of this Embodiment) FIG. 5 shows a modification from the mesa separation step of the semiconductor layer 1a to the gate oxidation step in the method of manufacturing the TFT array substrate 10 of the above-described embodiment. Only the differences from the above-described embodiment will be described, and the description of the common parts will be omitted.

FIG. 5A has a configuration similar to that of FIG. 4A, and the process up to this point is similar to the above-described process.
Here, the thickness of the semiconductor layer 1a is from 70 nm to 450 nm.
It is preferable to reduce the amount.

A resist pattern is formed on the semiconductor layer 1a of the TFT array substrate 10 obtained by the above process by a known photo process. Then, the semiconductor layer 1a is patterned into a predetermined shape by dry etching, and the resist is removed to obtain FIG. 5B. here,
The etching gas is applied to the semiconductor layer 1a and the first interlayer insulating film 12
Any condition can be used as long as the etching selectivity can be obtained.

Next, the semiconductor layer 1a is heated from 800.degree.
The entire semiconductor layer 1a is covered with an oxide film 43 by thermal oxidation at 0 ° C. to obtain a substrate shown in FIG. The oxide film thickness is the semiconductor layer 1a.
The thickness is preferably 50 nm to 300 nm, depending on the penetration depth of the plasma damage introduced during the dry etching. By such a process, defects due to plasma damage introduced when patterning the semiconductor layer 1a by dry etching are reduced by the oxide film 43.
Can be captured. Therefore, it is possible to suppress a leak current via a defect in the side wall of the semiconductor layer 1a.

Further, the oxide film 43 on the substrate obtained by the above process is removed by wet etching to obtain the substrate shown in FIG. As the wet etching solution, for example, a mixed solution of hydrofluoric acid and ammonium fluoride may be used. Although the thickness of the semiconductor layer 1a is reduced by the above process, it is set in advance in anticipation of the reduced amount. In FIG. 5D, the thickness is changed from 50 nm to 300 nm. Then 8
About 0 nm is desirable, and 150 nm if partially depleted.
Is desirable.

Hereinafter, the steps after the gate oxide film forming step are the same as those in the normal MOSFET manufacturing step, and therefore are omitted here. However, after the gate oxide film is formed, the gate electrode is formed, and the impurity ions are selectively formed in the semiconductor layer 1a. To form source / drain regions.

(Overall Configuration of Liquid Crystal Device) Next, the overall configuration of the liquid crystal device according to the embodiment will be described with reference to FIGS. FIG. 6 shows that the TFT array substrate 10 is
FIG. 7 is a plan view of the components formed thereon as viewed from the counter substrate 20, and FIG. 7 is a cross-sectional view taken along the line HH ′ of FIG.

As shown in FIG. 6, a third light shielding film 53 as a frame made of the same or different material as the second light shielding film 23 is provided on the counter substrate 20 in parallel with the inside of the sealing material 52. ing.

On the other hand, in the TFT array substrate 10, the data line driving circuit 101
And an external circuit connection terminal 102 is provided along one side of the TFT array substrate 10.
Are provided along two sides adjacent to this one side.
If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the screen display area. For example, the odd-numbered data lines 6a supply image signals from a data line driving circuit arranged along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area are provided. Further, at least one of the corners of the opposing substrate 20, the TFT array substrate 10 and the opposing substrate 2
A conductive material 106 for establishing electrical continuity with the zero is provided. Then, as shown in FIG.
The counter substrate 20 having substantially the same contour as that of the sealing material 52
To the TFT array substrate 10.

In addition, on the TFT array substrate 10, an inspection circuit or the like for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or shipping may be further formed. For example, a TN (twisted nematic) mode, an STN (super TN) mode, and a D-STN (dual scan-STN) are provided on the side of the opposite substrate 20 where the projected light is incident and on the side where the emitted light of the TFT array substrate 10 is emitted, respectively. A polarizing film, a retardation film, a polarizing means, and the like are arranged in a predetermined direction according to an operation mode such as a mode) and a normally white mode / normally black mode.

When the above-described liquid crystal device is applied to, for example, a color liquid crystal projector (projection display device), three liquid crystal devices are used for RGB light valves. In this case, the light of each color separated through the dichroic mirror for RGB color separation is respectively incident on each panel, and then combined and projected.
Therefore, in this case, the color filter is not provided on the opposing substrate 20 unlike the embodiment.

However, when the liquid crystal device according to the embodiment is applied as a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector, the second liquid crystal device may be used.
An RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a where the light-shielding film 23 is not formed, together with the protective film.

On the other hand, when the liquid crystal device according to the embodiment is applied to a light valve of a liquid crystal projector, a micro lens may be formed on the opposite substrate 20 so as to correspond to one pixel. In this case, a bright liquid crystal device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20.
According to the counter substrate with the dichroic filter, a brighter color liquid crystal device can be realized.

In the liquid crystal device according to the above-described embodiment, the incident light is made incident from the side of the counter substrate 20. However, since the first light shielding film 11a is provided, the incident light is made incident from the side of the TFT array substrate 10. The light may enter and exit from the counter substrate 20 side. That is, even if the liquid crystal device is mounted as a light valve of a liquid crystal projector, light can be prevented from being incident on the channel region 1a ', the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a. It is possible to display a high quality image. Here, conventionally, the TFT array substrate 10
Anti-reflection AR to prevent reflection on the back side of the
(Anti-reflection) It was necessary to separately arrange the coated polarizing means or to attach an AR film. However, in the embodiment, the first light-shielding film 11a is formed between the surface of the TFT array substrate 10 and at least the channel region 1a ', the low-concentration source region 1b, and the low-concentration drain region 1c of the semiconductor layer 1a. It is not necessary to use such an AR-coated polarizing means or AR film, or to use a substrate obtained by subjecting the TFT array substrate 10 to an AR process. Therefore, according to each of the embodiments, the material cost can be reduced, and the yield is not significantly reduced due to adhesion of dust or scratching when attaching the polarizing means, which is very advantageous. In addition, since the light resistance is excellent, even if a bright light source is used, or polarization conversion is performed by a polarization beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

(Electronic Apparatus) Next, as an example of an electronic apparatus using the liquid crystal device, a configuration of a projection display device will be described with reference to FIG. FIG. 8 shows a case where three liquid crystal devices described above are prepared, and the liquid crystal devices 962R and 962R for RGB are respectively provided.
Projection type liquid crystal device 110 used as 62G and 962B
FIG. 2 is a diagram illustrating a schematic configuration of an optical system No. 0; A light source device 920 and a uniform illumination optical system 923 are employed in the optical system of the projection display device 1100 of this example. Then, the projection display apparatus 1100 includes a color separation optical system 924 that separates the light beam W emitted from the uniform illumination optical system 923 into red (R), green (G), and blue (B). Light valves 925R, 925G, and 925B that modulate G and B, respectively.
And a color synthesizing prism 910 for re-synthesizing the modulated color light flux, and a projection lens unit 906 as a projection unit for enlarging and projecting the synthesized light flux onto the surface of the projection surface 100. Further, a light guide system 927 for guiding the blue light flux B to the corresponding light valve 925B is also provided.

The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931. The two lens plates 921 and 922 are arranged so as to be orthogonal to each other with the reflection mirror 931 interposed therebetween. Uniform illumination optical system 923
The two lens plates 921 and 922 each include a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is transmitted to the first lens plate 92.
The light is split into a plurality of partial light beams by one rectangular lens.
Then, these partial light beams are divided into three light valves 925R and 925R by the rectangular lens of the second lens plate 922.
Superimposed around 5G and 925B. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has an uneven illuminance distribution in the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B are used.
Can be illuminated with uniform illumination light.

Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First,
In the blue-green reflecting dichroic mirror 941, the light flux W
Are reflected at a right angle, and head toward the green reflecting dichroic mirror 942. On the other hand, the red light beam R passes through the blue-green reflecting dichroic mirror 941, is reflected at a right angle by the rear reflecting mirror 943, and is emitted from the emission section 944 of the red light beam R to the color combining optical system side.

Next, the blue-green reflecting dichroic mirror 94
Of the blue light beam B and the green light beam G reflected by 1, only the green light beam G is reflected at a right angle by the green reflecting dichroic mirror 942, and is emitted from the emission unit 945 of the green light beam G to the color combining optical system side. You. Further, the blue light flux B that has passed through the green reflection dichroic mirror 942 is emitted from the emission section 946 of the blue light flux B to the light guide system 927 side. In the present example, the emission unit 94 of each color light beam in the color separation optical system 924 starts from the emission unit of the light beam W of the uniform illumination optical element.
The distances to 4,945 and 946 are set to be substantially equal to each other.

The emission side of the emission portion 944 of the red light beam R by the color separation optical system 924 and the emission portion 94 of the green light beam G.
Condensing lenses 951 and 952 are arranged on the exit side of the light emitting element 5, respectively. Therefore, the red light beam R and the green light beam G emitted from each of the light emitting portions are condensed by these condenser lenses 951,
952, and are collimated.

The red light beam R and the green light beam G thus collimated enter the light valves 925R and 925G and are modulated, and image information corresponding to each color light is added. That is, the switching of these liquid crystal devices is controlled by driving means (not shown) in accordance with the image information, whereby each color light passing therethrough is modulated.

On the other hand, the blue light flux B is guided to the corresponding light valve 925B via the light guide system 927, where it is similarly modulated according to the image information. Note that the light valves 925R, 925G, and 925B of this example further include incident-side polarization means 960R, 960G, and 960, respectively.
B and the output-side polarization means 961R, 961G, 961B
And the liquid crystal devices 962R and 962 disposed therebetween.
G, 962B.

Incidentally, the light guide system 927 is provided with a condenser lens 954 disposed on the exit side of the exit portion 946 of the blue light flux B.
, The input side reflection mirror 971 and the output side reflection mirror 97
2 and an intermediate lens 9 disposed between these reflecting mirrors
73 and a condenser lens 953 disposed on the front side of the light valve 925B. The blue light beam B emitted from the emission unit 946 is guided to the liquid crystal device 962B via the light guide system 927 and is modulated. The optical path length of each color beam,
That is, each liquid crystal device 962R, 9
The distance to 62G and 962B is the longest for the blue luminous flux B, and therefore the loss of the light quantity of the blue luminous flux is the largest. However, by interposing the light guide system 927, the loss of light amount can be suppressed.

Each light valve 925R, 925G, 92
The color light fluxes R, G, and B modulated through 5B are incident on a color combining prism 910, where they are combined. The light combined by the color combining prism 910 is enlarged and projected on the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.

In this example, the liquid crystal devices 962R, 962G,
Since the light-shielding layer is provided below the TFT in the 962B, the light reflected by the projection optical system in the liquid crystal projector based on the light projected from the liquid crystal devices 962R, 962G, and 962B, and the projection light passing therethrough Even if reflected light from the surface of the TFT array substrate, part of the projected light that passes through the projection optical system after being emitted from another liquid crystal device, etc. is incident from the TFT array substrate side as return light, the pixel electrode The switching TFT channel can be sufficiently shielded from light.

For this reason, even if the color combining prism 910 suitable for miniaturization is used, each of the liquid crystal devices 962R, 962G, 9
Since it is not necessary to separately arrange a film for preventing return light or to perform a return light prevention process on the polarizing means between the color combining prism 910 and the color combining prism 910, the configuration can be reduced in size and simplified. It is very advantageous.

In this embodiment, since the influence of the return light on the channel region of the TFT can be suppressed, the polarization means 961R, 91R, 91R, 9R, which directly apply the return light prevention processing to the liquid crystal device.
It is not necessary to attach 61G and 961B. Therefore, as shown in FIG. 8, the polarizing means is formed apart from the liquid crystal device, and more specifically, one of the polarizing means 961R, 961
G and 961B can be attached to the color combining prism 910, and the other polarizing means 960R, 960G and 960B can be attached to the condenser lenses 951, 952 and 953. As described above, when the polarizing means is attached to the color combining prism 910 or the condenser lenses 951, 952, and 953, the heat of the polarizing means is absorbed by the color combining prism 910 or the condenser lenses 951, 952, and 953. The temperature rise of the liquid crystal device can be suppressed, and the malfunction can be prevented.

Although not shown, an air layer is formed between the liquid crystal device and the polarizing means by forming the liquid crystal device and the polarizing means separately. Here, cooling means is provided,
By sending air such as cold air between the liquid crystal device and the polarizing means, it is possible to further suppress the temperature rise of the liquid crystal device and more reliably prevent a malfunction due to the temperature rise of the liquid crystal device.

In the above description, the electro-optical device has been described as a liquid crystal device. However, the present invention is not limited to this, and the present invention can be applied to various electro-optical devices such as electroluminescence and plasma displays. Applicable.

[0082]

As described above, according to the present invention, the display quality can be prevented from deteriorating due to the off-leak current of the transistor, and the transistor size can be reduced, so that the transmission type high-resolution and high-definition electro-optical device can be obtained. It is also possible to secure an aperture ratio.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a configuration of an image forming area in a liquid crystal device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a configuration of a plurality of pixel groups adjacent to each other on a TFT array substrate of the liquid crystal device.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a diagram illustrating a method of manufacturing the electro-optical device according to the embodiment of the invention.

FIG. 5 is a diagram illustrating another method of manufacturing the electro-optical device according to the embodiment of the invention.

FIG. 6 is a plan view showing a configuration of the liquid crystal device.

FIG. 7 is a sectional view taken along the line H-H 'of FIG.

FIG. 8 is a plan view showing a configuration of a projection display device as an example of an electronic apparatus using the liquid crystal device.

[Explanation of symbols]

 1a: semiconductor layer 1a ': channel region 1b: low-concentration source region (source-side LDD region) 1c: low-concentration drain region (drain-side LDD region) 1d: high-concentration source region 1e: high-concentration drain region 3a: scanning line 3a ... wrap-around part 3b ... capacitance line 6a ... data line 9a ... pixel electrode 10 ... TFT array substrate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09F 9/00 338 F Term (Reference) 2H090 HA04 HA05 HB04X HC10 JB04 JB06 JD17 LA04 2H092 HA28 JA28 JA36 JB51 JB56 JB57 KA03 KB24 MA18 MA19 MA25 NA22 NA23 RA05 5F110 AA06 AA26 BB01 CC02 DD03 GG02 GG12 GG13 GG25 GG44 GG58 HJ12 HJ13 HL03 HL05 HL08 HM14 HM15 NN23 NN24 NN25 NN26 NN44 NN46 NN47 Q11 NN62 NN62 NN62 NN62 NN62 NN62 NN62 KK09 KK10

Claims (10)

[Claims] At least a plurality of scanning lines, a plurality of data lines intersecting the plurality of scanning lines, and each of the plurality of scanning lines are provided on a substrate on which a semiconductor layer is formed via an insulating film on a supporting substrate. And a transistor connected to each of the data lines;
A method for manufacturing an electro-optical device substrate having a pixel electrode connected to the transistor, comprising: forming an oxide film on a surface of the semiconductor layer forming the transistor; and an oxidation preventing film on a surface of the oxide film. Forming a selected region using a photomask, and removing the oxidation preventing film, the oxide film, and the semiconductor layer in the selected region, wherein at least the semiconductor layer is removed by dry etching. And a step of thermally oxidizing the dry-etched substrate to thermally oxidize a side surface of the semiconductor layer exposed by the dry etching, the method comprising: . 2. A plurality of scanning lines, a plurality of data lines intersecting the plurality of scanning lines, and each of the plurality of scanning lines, on at least a substrate having a semiconductor layer formed on a supporting substrate via an insulating film. And a transistor connected to each of the data lines;
A method for manufacturing an electro-optical device substrate having a pixel electrode connected to the transistor, comprising: forming a selected region on the semiconductor layer using a photomask; and removing the semiconductor layer in the selected region by dry etching. And a step of thermally oxidizing the dry-etched substrate; and a step of removing the thermally oxidized oxide film by wet etching. 3. The method of manufacturing an electro-optical device substrate according to claim 1, wherein the oxidation prevention film is a silicon nitride film. 4. The method of manufacturing an electro-optical device substrate according to claim 1, wherein the support substrate is a transparent substrate. Production method. 5. The method of manufacturing an electro-optical device substrate according to claim 1, wherein the support substrate is a quartz substrate. Production method. 6. The method of manufacturing an electro-optical device substrate according to claim 1, wherein the semiconductor layer is made of single-crystal silicon. Manufacturing method. 7. The method of manufacturing an electro-optical device substrate according to claim 1, wherein the semiconductor layer is made of polycrystalline silicon. Manufacturing method. 8. The method of manufacturing an electro-optical device substrate according to claim 1, further comprising a light-shielding layer between the support substrate and the semiconductor layer. A method for manufacturing an electro-optical device, comprising: 9. An electro-optical device substrate manufactured by the method of manufacturing an electro-optical device substrate according to claim 1, wherein the semiconductor layer of the electro-optical device substrate is provided. And the other substrate disposed so as to face the surface of the one substrate on which is formed, and a liquid crystal sandwiched between the one and the other substrates and driven by a transistor formed in the semiconductor layer; An electro-optical device, further comprising: 10. The electro-optical device according to claim 9, wherein the light emitted from the light source is incident to perform modulation corresponding to image information, and the light modulated by the electro-optical device is projected. An electronic apparatus comprising: