JP2001267489A - Semiconductor device and semiconductor chip - Google Patents

Abstract

(57) Abstract: A semiconductor device having a chip-on-chip structure capable of reducing an occupied area on a mounting board, and a semiconductor chip for the same are provided. A bonding area (11) of a child chip (2) is set on an active surface of a parent chip (1). The bonding area (11) has a plurality of inter-chip connection bumps (1) made of a conductive material.
2 are raised. An insulating layer 14 having an opening 13 facing the bonding region 11 is laminated on the active surface of the parent chip 1, and a plurality of conductive materials made of a conductive material protrude from the surface of the insulating layer 14. External connection bumps 15 are provided. The child chip 2 has its active surface opposed to the bonding area 11 on the surface of the parent chip 1, and the respective chip-to-chip connection bumps 21 are respectively coupled to the corresponding chip-to-chip connection bumps 12 of the parent chip 1. It is electrically and mechanically connected to the parent chip 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a chip-on-chip structure in which another semiconductor chip is bonded to the surface of a semiconductor chip, and to a semiconductor device having such a chip-on-chip structure. Semiconductor chip.

[0002]

2. Description of the Related Art A semiconductor device having a chip-on-chip structure is formed by bonding a second semiconductor chip (child chip) to a surface of a first semiconductor chip (parent chip) with its surfaces facing each other. It has been proposed to construct
FIG. 3 is a cross-sectional view illustrating a configuration example of a semiconductor device having a chip-on-chip structure. In this chip-on-chip structure, a parent chip 91 and a child chip 92 facing each other
Bumps 93 and 94 are respectively formed on the surfaces of the bumps 93 and 94. By connecting the bumps 93 of the parent chip 91 and the bumps 94 of the child chip 92, electrical connection between the parent chip 91 and the child chip 92 is achieved. Have been. A plurality of external connection pads 95 are also formed on the surface of the parent chip 91 so as to be exposed in the vicinity of the periphery, and the joined body of the parent chip 91 and the child chip 92 is formed by connecting the parent chip 91 to the island of the lead frame 96. By being die-bonded on the lead frame 96a, the lead frame 96 is mechanically connected to the lead frame 96, and the external connection pad 95 and the lead terminal 96b of the lead frame 96 are connected by the bonding wire 97, thereby forming the lead frame 96. Is electrically connected to

[0003]

SUMMARY OF THE INVENTION A chip as described above
Since the semiconductor device having the on-chip structure has a configuration in which the lead terminals 96b are arranged around the parent chip 91, the size of the entire device in a plan view is large and occupies a relatively large space on the mounting board. Therefore, an object of the present invention is to provide a semiconductor device having a chip-on-chip structure capable of reducing an occupied area (mounting area) on a mounting board, and a semiconductor chip for the same.

[0004]

Means for Solving the Problems and Effects of the Invention According to the first aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor chip having a second surface separate from the first semiconductor chip; A semiconductor device having a chip-on-chip structure in which semiconductor chips are bonded to each other, wherein the semiconductor device is formed in a chip bonding region set on a surface of the first semiconductor chip, and is connected to the second semiconductor chip. The second semiconductor chip is formed in a region other than the chip bonding region on the surface of the first semiconductor chip, and the second semiconductor chip is bonded to the chip bonding region. An external connection portion protruding to the surface side of the semiconductor chip.

[0005] The surface of the semiconductor chip refers to the surface on the active surface layer side on which functional elements such as transistors are formed. According to this configuration, the external connection portion is provided in a region other than the chip bonding region on the surface of the first semiconductor chip, and the second external connection portion is bonded to the chip bonding region.
Protrude more toward the front side than the semiconductor chip. Thus, the surface of the first semiconductor chip is opposed to the mounting surface of the mounting substrate, and the external connection portion is connected to the wiring pattern formed on the mounting surface, thereby mounting the semiconductor device on the mounting substrate. Can be achieved. Therefore, since the semiconductor device does not require a lead frame, the device size can be reduced accordingly, and the area occupied on the mounting board (mounting area) can be reduced.

According to a second aspect of the present invention, there is provided a semiconductor chip for a semiconductor device having a chip-on-chip structure in which another semiconductor chip is bonded to a surface of the semiconductor chip, wherein the semiconductor chip is set on the surface of the semiconductor chip. An inter-chip connecting portion formed in the formed chip bonding region and connected to the another semiconductor chip, and formed in a region other than the chip bonding region on the surface of the semiconductor chip; And an external connection portion protruding more toward the surface side than the another semiconductor chip in a state where the semiconductor chip is joined.

With this configuration, the same effect as the effect described in claim 1 can be obtained. That is,
When a semiconductor device having a chip-on-chip structure is manufactured using this semiconductor chip, the area occupied by the semiconductor device on a mounting substrate can be reduced.

[0008]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing a configuration of a semiconductor device according to one embodiment of the present invention. This semiconductor device has a chip-on-chip structure in which a child chip 2 as a second semiconductor chip is joined to an active surface of a parent chip 1 as a first semiconductor chip. In this case, the active surface refers to a surface on the active surface layer region side on which a functional element such as a transistor is formed.
Each of the parent chip 1 and the child chip 2 may be a silicon chip, but may be another type of semiconductor chip such as a compound semiconductor (such as gallium arsenide or gallium phosphide) or a germanium semiconductor. It is not necessary that the types of semiconductors of the semiconductor chip 1 and the child chip 2 match.

The parent chip 1 has, for example, an outer shape in plan view larger than that of the child chip 2. On the active surface of the parent chip 1, a bonding region 11 of the child chip 2 is set, and in this bonding region 11, a plurality of inter-chip connection bumps 12 made of a conductive material are formed so as to protrude. . In addition, a bonding region 1 is provided on the active surface of the parent chip 1.
An insulating layer 14 having an opening 13 opposed to the insulating layer 14 is laminated, and a plurality of external connection bumps 15 made of a conductive material are provided so as to protrude from the surface of the insulating layer 14. Both the inter-chip connection bumps 12 and the external connection bumps 15 are connected to internal wirings provided on a semiconductor substrate serving as a base of the parent chip 1.

On the active surface of the child chip 2, a plurality of chip connecting bumps 21 made of a conductive material are provided at positions corresponding to the respective chip connecting bumps 12 of the parent chip 1.
Are formed. These inter-chip connection bumps 21
Are connected to the internal wiring provided on the semiconductor substrate forming the base of the sub chip 2. The child chip 2 has its active surface opposed to the bonding region 11 on the surface of the parent chip 1, and each of the inter-chip connection bumps 21 is bonded to the corresponding inter-chip connection bump 12 of the parent chip 1, respectively. It is electrically and mechanically connected to the parent chip 1.

The semiconductor device having such a configuration can be directly mounted on a mounting substrate 3 such as a glass substrate for liquid crystal. That is, the semiconductor device is mounted on the mounting substrate 3 by connecting the active surface of the parent chip 1 to the mounting surface of the mounting substrate 3 and externally connecting to a wiring pattern (not shown) formed on the mounting surface. This can be achieved by connecting the bump 15 for use. Therefore, the lead frame can be omitted, and the size of the device can be reduced accordingly, so that the occupied area (mounting area) on the mounting board 3 is reduced.

The external connection bump 15 is formed such that the distance between the top surface thereof and the surface 11a of the bonding region 11 is larger than the thickness (for example, about 30 μm) of the child chip 2. Therefore, when this semiconductor device is mounted on the mounting substrate 3, the back surface of the child chip 2 bonded to the bonding region 11 does not contact the mounting surface of the mounting substrate 3, so that the external connection bump 15 and the mounting substrate There is no possibility that a connection failure with the third wiring pattern will occur. However, as long as the electrical connection between the external connection bumps 15 and the mounting substrate 3 can be secured, the back surface of the child chip 2 may be in contact with the surface of the mounting substrate 3. It may be bonded to the surface with an adhesive.

When the semiconductor device is mounted on the mounting substrate 3, it is preferable that, for example, an ACF (Anisotropic Conductive Film) is interposed between the semiconductor device and the mounting substrate 3. . In this case, at the joint between the external connection bump 15 and the wiring pattern formed on the mounting board 3, the conductive capsule included in the ACF is crushed to exhibit conductivity. And the wiring pattern are electrically connected well. In addition, since the area other than the bonding portion between the external connection bump 15 and the wiring pattern is sealed with the ACF, the corrosion between the chip-to-chip connection bumps 12 and 21 and the external connection bump 15 can be prevented. In addition, since the space in the opening 13 is sealed by the ACF, the active surfaces of the parent chip 1 and the child chip 2 can be protected.

FIG. 2 is a sectional view showing a method of manufacturing the parent chip 1 in the order of steps. Each step shown in FIGS. 2A to 2D is performed in a state of the wafer W before being cut into individual semiconductor chips. The wafer W has undergone various element forming steps, wiring forming steps, and the like. On the internal wiring 16 formed in this wiring forming step, as shown in FIG. A surface protection film (passivation film) 17 having an opening 17a facing the substrate is laminated. The opening 17a is formed by forming a surface protection film 17 so as to cover the entire surface of the wafer W, patterning a resist film on the surface protection film 17 by photolithography, and further etching using the resist film as a mask. Can be formed.

After the opening 17a is formed, FIG.
As shown in FIG. 5, a bump B is formed on the internal wiring 16 exposed through the opening 17a. The bump B can be formed, for example, by patterning a resist film having an opening corresponding to the opening 17a on the surface protective film 17 and then performing plating using a bump material. Bump B
After the formation, the insulating layer 14 is selectively formed as shown in FIG. The insulating layer 14 is formed, for example, by depositing the material of the insulating layer 14 on the entire surface of the surface protection film 17 and the bumps 12 for connecting the chips, and then facing the preset child chip bonding region 11 and the child. It can be formed by selectively removing a portion facing the bump B provided in a region other than the chip bonding region 11 by an etching process.

Next, by performing the same step as the step of forming the inter-chip connection bumps 12, as shown in FIG. 2D, the bumps exposed from the insulating layer 14 in regions other than the sub-chip bonding region 11 are formed. External connection bump 1 on B
5 are formed. The external connection bump 15 thus formed is connected to the internal wiring 16 via the bump B. In addition, the bumps B formed in the sub chip bonding region 11 become inter-chip connection bumps 12 for connection with the sub chip 2 (see FIG. 1). Thereafter, the wafer W is cut along a scribe line (not shown) set in advance, whereby pieces of the plurality of parent chips 1 having the above-described configuration are cut out.

Although one embodiment of the present invention has been described above, the present invention can be embodied in other forms. For example, in the above embodiment, one parent chip 1 has one
Although the configuration in which the plurality of child chips 2 are joined has been described as an example, a plurality of child chips 2 may be joined on one parent chip 1. In addition, various design changes can be made within the scope of the matters described in the claims.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method of manufacturing the semiconductor device in the order of steps.

FIG. 3 is a cross-sectional view illustrating a configuration example of a conventional semiconductor device having a chip-on-chip structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Parent chip (1st semiconductor chip) 2 Child chip (2nd semiconductor chip) 3 Mounting board 11 Child chip bonding area 12 Bump for connection between chips (connection part between chips) 15 Bump for external connection (external connection part) 21 Bump for connecting between chips

Claims (2)

[Claims] 1. A semiconductor device having a chip-on-chip structure in which a second semiconductor chip different from the first semiconductor chip is joined to a surface of the first semiconductor chip, An inter-chip connecting portion formed in a chip bonding region set on the surface of the semiconductor chip for connection to the second semiconductor chip; and a region other than the chip bonding region on the surface of the first semiconductor chip. And an external connection portion protruding to a surface side of the second semiconductor chip in a state where the second semiconductor chip is bonded to the chip bonding region. 2. A semiconductor chip for a semiconductor device having a chip-on-chip structure in which another semiconductor chip is bonded to a surface of a semiconductor chip, wherein the semiconductor chip has a chip bonding region set on the surface of the semiconductor chip. And an inter-chip connection portion for connection with the another semiconductor chip, formed in a region other than the chip bonding region on the surface of the semiconductor chip, and the another semiconductor chip is bonded to the chip bonding region. And an external connection portion protruding to a surface side of the another semiconductor chip in a state in which the semiconductor chip is placed.