JP2001264397A - Delay time measuring device, delay time measuring method, and semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Problem] Delay time of a circuit under test path including a circuit under test
In the method of measuring the delay time Tpd (= Tm−Td) of the circuit under test by subtracting the delay time Td of the dummy circuit path configured to bypass the circuit under test from the circuit path under test from Tm, Time Tm is the delay time of the dummy circuit path
If it is sufficiently shorter than Td, the measurement accuracy of the delay time Tpd of the circuit under test deteriorates. SOLUTION: The phase detection means 5 outputs a delay control signal 17 so that the transition times of the output terminal Smo of the circuit-under-test path and the output terminal Sdo of the dummy circuit path are aligned, and the delay control signal 17 is input to the input terminal Sdi of the dummy circuit path. The delay time of the connected variable delay time circuit 4 is adjusted, and as a result, the delay time Tpd of the circuit under test 8 is controlled to be equal to the delay time of the variable delay time circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a delay time measuring device for measuring a propagation delay time of an internal circuit of a semiconductor integrated circuit, a semiconductor integrated circuit, and a method for measuring the delay time.

[0002]

2. Description of the Related Art In recent years, the speed of semiconductor integrated circuits has been increased due to advances in miniaturization technology. However, variations in the propagation delay time of digital circuits due to variations in the processing of transistors and wiring and an increase in capacitive coupling between wirings. Is becoming relatively large.

Therefore, in order to manufacture a semiconductor integrated circuit capable of operating at a high speed by using a miniaturization technique with a high yield,
It is becoming important to understand the delay time values and statistical variations of circuit paths that control the operation speed of digital circuits at both the prototype circuit and the product level, and to improve the manufacturing process and design.

At the level of a prototype circuit, it is necessary to statistically measure a large number of short delay circuit paths, and at the product level, it is required to incorporate a delay monitor circuit for process control into a product.

Conventionally, to measure the delay time of a circuit under test, which is a part of the signal path of the circuit under test, a dummy circuit path having a configuration bypassing the circuit under test from the circuit path under test is provided. It is known that the delay time of the dummy circuit path is subtracted from the delay time of the path. Usually, the circuit path to be measured has a structure in which an input circuit, a circuit to be measured, and an output circuit are connected in series in order, and the dummy circuit path has a structure in which an input circuit and an output circuit are connected in series.

Hereinafter, a conventional delay time measuring method will be described with reference to the drawings. FIG. 6 is a signal waveform diagram of each terminal of a circuit path to be measured having an input terminal Smi and an output terminal Smo and a dummy circuit path having an input terminal Sdi and an output terminal Sdo.

The delay time Tm of the circuit path to be measured is
It can be obtained by subtracting the input time tSmi of the input terminal Smi from the transition time tSmo of Smo by a value Tm = tSmo-tSmi. The delay time Td of the dummy circuit path is a value Td = tSdo-t obtained by subtracting the input time tSdi of the input terminal Sdi from the transition time tSdo of the output terminal Sdo.
Required by Sdi. Then, the delay time Tpd of the circuit under test is calculated as Tpd = Tm−Td as the difference between these delay times.

In a conventional delay time measurement, an input terminal
Smi, give the input timing of the input terminal Sdi aligned (tSmi
= tSdi), and by measuring the time difference between the output transition times tSmo and tSdo, the delay time Tpd (Tpd = Tm−Td = tS
mo-tSdo), and the Tm and Td are determined by operating the circuit-under-measurement path and the dummy circuit path independently.

[0009]

However, in a high-speed operation semiconductor integrated circuit utilizing a miniaturization technique,
To increase the speed of the circuit under test, the delay time of the circuit under test
Tpd has become sufficiently smaller than the delay time Tm of the circuit-under-test path and the delay time Td of the dummy circuit path,
As a result, T is defined by the ratio of the measurement error δmeas generated when the delay time is differentiated to the delay time Tpd of the circuit under test.
It was found that the relative error δmeas / Tpd of pd deteriorated rapidly.

Assuming that the delay times of the circuit path to be measured and the dummy circuit path including the measurement error are Tm (meas) and Td (meas), respectively, Tm (meas) = Tdum (vdd) + Tpd + δe1 Td (meas) = It is given by Tdum (vdd ') + δe2. Here, Tdum (vdd) and Tdum (vdd ') are delay times at the power supply voltages vdd and vdd' of the dummy circuit path, respectively, and δe1 and δe2 are errors in timing measurement due to distortion of the output waveform, that is, when the output waveform amplitude is Shows the error when searching for the time when the threshold value is reached.

The measurement error δmeas is given by: = Tdum (vdd) -Tdum (vdd ') + δe1-δe2 (Equation 1)

Equation (1) gives a timing measurement error δmeas
Indicates that the error is caused by an error (Tdum (vdd) -Tdum (vdd ')) due to a slight difference in power supply voltage between the two circuit paths and an error (δe1-δe2) due to a difference in output waveform shape. .

As an example, in a prototype circuit of 1-2 [ns] Tpd formed by a 0.25 μm CMOS process, δmeas / Tpd = 50-90
%, Which is unacceptable.

An object of the present invention is to determine the delay time of a circuit under test (Tpd = Tm−
Td) for the circuit configuration
pd is the delay time T of the circuit path to be measured and the dummy circuit path
An object of the present invention is to provide a delay time measuring device, a semiconductor integrated circuit, and a delay time measuring method capable of accurately measuring the delay time Tpd of a circuit under test even if the delay time becomes sufficiently smaller than m and Td.

[0015]

Means for Solving the Problems In the description of the means for solving the problems, for ease of understanding, reference numerals used in the drawings related to the embodiments to be described later are also described. It shall be. [Claims] at the beginning
The same applies to the description in the section. The present invention should not be construed in a limited manner by using the codes.

(1) The delay time measuring apparatus of the present invention comprises a circuit path to be measured including a circuit to be measured, and a dummy circuit path having a configuration in which the circuit to be measured is bypassed from the circuit path to be measured. Input terminal Smi and output terminal S of the path
The delay time Tm between mo and the input terminal Sdi of the dummy circuit path
In the delay time measurement of the semiconductor integrated circuit configured to determine the delay time Tpd (= Tm-Td) of the circuit under test by the difference between the circuit path under test and the delay time Td between the output terminals Sdo, Both output terminals Sm of dummy circuit path
Both input terminals Sm of the circuit path to be measured and the dummy circuit path are aligned so that transition times tSmo and tSdo of o and Sdo are aligned.
It is characterized in that it is configured to determine input signals of i and Sdi.

Since the output waveforms of the output terminal Smo of the circuit path to be measured and the output terminal Sdo of the dummy circuit path are simultaneously switched, the shapes of the output waveforms are automatically aligned.
As a result, the measurement error Δe1−Δe2 of the circuit under measurement due to the distortion of the output waveform can be sufficiently suppressed.

The output-related operations of the circuit path to be measured and the dummy circuit path are simultaneous, the output operation periods for generating power supply noise are simultaneously parallel, and the power supply voltage condition is different between the circuit path to be measured and the dummy circuit path. Since they are the same, the power supply voltage vdd of the circuit under test path and the power supply voltage vdd 'of the dummy circuit path
And the delay time Tdum (vdd) and Tdum by each
(vdd ') is substantially equal to the measurement error Tdum (vdd)-
Tdum (vdd ') can also be kept sufficiently small.

Furthermore, since the output-related operation is not performed in the dummy circuit path during the transition of the internal signal of the circuit to be measured, the fluctuation of the power supply voltage of the circuit to be measured can be suppressed sufficiently.

In general, since the circuits related to the input to the circuit under test on the circuit path to be measured are circuits that accept external inputs, these circuits are lower than the circuits related to the output which need to drive the external circuit. Based on the fact that it is noise.

(2) In addition to the above means, the delay time measuring apparatus of the present invention further comprises a variable delay time circuit whose delay time is controlled by the delay control signal, and a pulse generation circuit for generating an arbitrary digital signal. Means, and a phase detecting means for measuring a time difference of a signal transition between digital signals, wherein a signal output of the pulse generating means is connected to an input terminal Smi of the circuit-under-test and an input terminal Sdi of the dummy circuit path. Is connected via the variable delay time circuit,
The output of the output terminal Smo of the circuit-under-test path and the output of the output terminal Sdo of the dummy circuit path are input to the phase detection means, and from the phase detection means, each of the two circuit paths with respect to the variable delay time circuit. The delay control signal is fed back so that the phases of the outputs of the output terminals Sdo and Smo match.

When the feedback loop is stabilized, the transition times of both outputs of the dummy circuit path and the circuit-under-test are aligned, so that the delay time of the variable delay circuit provided at the input terminal Sdi of the dummy circuit path is determined. This is the delay time of the circuit.

By introducing the idea of the feedback loop, the delay time of the circuit to be measured can be easily obtained with high accuracy by observing only one point of the delay control signal for the variable delay time circuit.

(3) The semiconductor integrated circuit of the present invention comprises a circuit path to be measured including the circuit to be measured, a dummy circuit path having a configuration in which the circuit to be measured is bypassed from the circuit path to be measured, and a control voltage line. Voltage control delay line whose amount of delay time is controlled by the potential, a phase comparator that outputs the phase relationship between input signals, a charge pump that controls the charge and discharge of the output line, and the removal of high-frequency components of potential changes And a low-pass filter that holds the input charge, and a ring oscillator configured with a voltage-controlled delay line equivalent to the voltage-controlled delay line, and an input digital signal is input terminal Smi of the circuit-under-test path, An output terminal Smo of the circuit-under-test path and an output of the output terminal Sdo of the dummy circuit path are connected to the phase comparator through a voltage control delay line to the input terminal Sdi of the dummy circuit path. The charge signal output and the discharge signal output of the phase comparator are connected to the charge pump, and the output of the charge pump constitutes the control voltage line of the voltage control delay line and the ring oscillator via the low-pass filter. The voltage control delay line is connected in parallel to a control voltage line of a voltage control delay line equivalent to the voltage control delay line, the delay time of the voltage control delay line is monotonically decreasing with respect to a control voltage, and the phase comparator is connected to the circuit path under test By comparing the transition time tSmo of the output terminal Smo with the transition time tSdo of the output terminal Sdo of the dummy circuit path, when tSdo> tSmo, only the charge signal is activated, and when tSdo <tSmo, only the discharge signal is activated, When tSdo = tSmo, the charge signal and the discharge signal are deactivated. When the charge signal or the discharge signal is activated, the charge pump forms the low-pass filter, respectively. Controlling the control voltage of the voltage control delay line by charging or discharging a capacitance, and measuring a delay time of the circuit under test based on an output frequency of the ring oscillator. I do.

The input digital signals input to the circuit path to be measured and the dummy circuit path are transition times tSmo and tSd, respectively.
Output with o.

The relationship of the output timing is, for example, tSdo>
At tSmo, the phase comparator charges the low-pass filter to increase the potential of the control voltage line of the voltage control delay line. When the control voltage increases, the delay amount of the voltage control delay line provided at the input of the dummy circuit path decreases, and the input time tSdi for the dummy circuit path is earlier,
The output transition time tSdo is also earlier, so that tSdo = tS
The state of the circuit changes in the direction of mo. Conversely, tS
When do <tSmo, the phase comparator lowers the potential of the control voltage line of the voltage control delay line by discharging from the low-pass filter. When the control voltage decreases, the delay amount of the voltage control delay line provided at the input of the dummy circuit path increases, and the input time tSdi to the dummy circuit path is further delayed, so that the output transition time tSdo is also delayed,
The state of the circuit changes in the direction where tSdo = tSmo. As a result, the feedback loop converges so that tSdo = tSmo.

When the circuit operation is stabilized at tSdo = tSmo, the output of the charge pump enters a high impedance state, and the voltage of the control voltage line is held. At this time, the delay time of the voltage control delay line provided at the input of the dummy circuit path automatically becomes the delay time value of the circuit under test.

Further, since the control voltage line is connected to the voltage control delay line constituting the ring oscillator, the oscillation frequency of the ring oscillator oscillates at a cycle that is an integral multiple of the delay time of the circuit under test.

The measurement of the oscillation frequency is easier than the measurement of the delay time, and can be measured only by monitoring a single line, and the delay time of the circuit element to be measured can be measured very easily from outside the semiconductor element. be able to.

(4) The semiconductor integrated circuit according to the present invention
In addition to the above means, the charge pump is provided with a sampling stop signal input, and is configured to forcibly bring the output of the charge pump into a floating state when the sampling stop signal is activated. And

(5) Further, the semiconductor integrated circuit of the present invention comprises:
In addition to the above means, the phase comparator is provided with a sampling stop signal input, and is configured to forcibly deactivate a charge signal and a discharge signal when the sampling stop signal is activated. Features.

Even if the input digital clock is always input, the delay time of the circuit under test in a desired circuit state can be selectively measured by a sampling stop signal.
By holding the delay time of the voltage control delay line at a constant value when reading the frequency of the ring oscillator, the frequency measurement can be performed stably.

(6) The delay time measuring method according to the present invention employs a circuit under test including a circuit under test in which a signal input at time tSmi is output at time tSmo, and a circuit under test from the circuit under test path. In the delay time measuring method for obtaining a delay time of a circuit to be measured based on a delay time difference from a dummy circuit path in which a signal input at time tSdi is output at time tSdo having a configuration bypassing the circuit, Output transition time tSmo and the output transition time tSdo of the dummy circuit path.
And the time difference tsw = tSmo-tSdo is measured. The process of measuring the time difference tsw is repeated while accumulating the value of tsw, and the difference between the input time tSdi of the dummy circuit path and the input time tSmi of the circuit path to be measured obtained after the end of the iterative process is calculated. The delay time of the measurement circuit is configured.

The shape of the output waveform of the output terminal Smo of the circuit under test path and the output terminal Sdo of the dummy circuit path can be matched, and the measurement error δe1 of the circuit under test due to waveform distortion.
-δe2 can be kept sufficiently small.

Further, the output-related operations of the circuit path to be measured and the dummy circuit path are simultaneous, and the output operation period for generating power supply noise is simultaneously parallelized in the two circuit paths, so that the delicate power supply between the two circuit paths Measurement error Tdum due to voltage fluctuation
(vdd) -Tdum (vdd ') can be kept sufficiently small.

Further, during the transition of the internal signal of the circuit under test, the output-related operation with a high noise level is not performed in the dummy circuit path, so that the fluctuation of the power supply voltage of the circuit under test can be suppressed to a sufficiently small level. The power supply voltage dependence of the delay time of the measuring circuit can be measured with high accuracy.

(7) In addition to the above-described means, the delay time measuring method of the present invention further comprises the step of accumulating the value of the time difference tsw at the input time tSdi of the dummy circuit path by multiplying the time difference tsw by a positive coefficient k. It is characterized by being configured to accumulate tsw.

For example, by setting a value of 0 <k ≦ 1 as k, the state of tSdo = tSmo can be gradually approached, and the state of tSdo> tSmo and the state of tSdo <tSmo can be changed. Vibration can be suppressed. As a result, the convergence of the iterative process can be completed in a short time, and the delay time of the circuit under test can be obtained at high speed.

(8) In addition to the above-mentioned means, the delay time measuring method of the present invention further comprises, as an ending condition of the iterative process, a difference between a time difference tsw before and after the repetition and a predetermined threshold value ΔT.
It is characterized in that it is configured by adding that it becomes pd2 or less.

In the case where vibration occurs between the state of tSdo = tSmo and the state of tSdo> tSmo, or between the state of tSdo = tSmo and the state of tSdo <tSmo, the simulation of the repetitive process is performed. Convergence can be detected, and a more accurate delay time can be obtained.

[0041]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the invention.
It is a lineblock diagram of a delay time measuring device in an embodiment.

In FIG. 1, the delay time measuring device 1 comprises a semiconductor integrated circuit 2, pulse generating means 3, variable delay time circuit 4, and phase detecting means 5.

The semiconductor integrated circuit 2 has an input terminal Smi
6 and an output terminal Smo10, an input circuit 7, a circuit under test 8, and an output circuit 9 in which a circuit path under test 11 is connected in series, and an input circuit between an input terminal Sdi12 and an output terminal Sdo15. 13, an output circuit 14 is provided with a dummy circuit path 16 connected in series in order. Here, the input circuit 7
, The input circuit 13 and the output circuit 9 and the output circuit 14 are circuits having equivalent delay times.

The output of the pulse generating means 3 is supplied to an input terminal Smi6.
Is supplied to the circuit path under test 11 and supplied to the input terminal Sdi1 via the variable delay time circuit 4.
2 to supply an input signal to the dummy circuit path 16.

These input signals are inputted to the phase detecting means 5 from the output terminal Smo10 and the output terminal Sdo15. The phase detection means 5 feeds back the delay control signal 17 to the variable delay time circuit 4 so that the phases of the input signals coincide, and controls the delay time of the variable delay time circuit 4.

FIG. 2 is a signal waveform diagram of the delay time measuring apparatus 1 in a state where tSdo = tSmo and the feedback loop has converged. FIG. 2 shows each terminal Smi, Smo,
The waveforms of Sdi and Sdo are shown. Sdi ^* indicates a waveform input to the variable delay time circuit 4.

For example, the transition time tSdo of the output terminal Sdo15
Transitions earlier than the transition time tSmo of the output terminal Smo10, that is, when tSmo> tSdo, the delay control signal 1
7 controls the delay time of the variable delay circuit 4 to increase by the value of tSmo-tSdo. Conversely, if tSmo <tSdo,
The delay time of the variable delay time circuit 4 is controlled so as to decrease by the value of tSdo-tSmo.

As described above, the delay control signal 17 is tSdo = tSm
It forms a feedback loop to make o.

The delay control signal 17 is supplied to the variable delay time circuit 4
Is realized by a voltage-controlled delay circuit, it is an analog control voltage. When the variable delay time circuit 4 is realized by a digital delay circuit controlled by a digital value, it corresponds to a digital signal line.

The delay time of the circuit path under test 11 is Tm = tSmo−
It is given by tSmi and is the sum of the delay times of the input circuit 7, the circuit under test 8, and the output circuit 9. The delay time of the dummy circuit path 16 is given by Td = tSdo-tSdi, and is the sum of the delay times of the input circuit 13 and the output circuit 14.

The delay time Tpd of the circuit under test 8 is Tpd = Tm−Td
Is required. Since the input time tSdi ^* from the pulse generation means 3 to the variable delay time circuit 4 is made equal to tSmi, the delay time Tpd matches the delay time of the variable delay time circuit 4.

The output of each circuit path transitions simultaneously, and tSmo = t
Since Sdo is an equivalent circuit between the output circuit 9 and the output circuit 14, the waveform shapes of the output terminals match, and the term δe1-δe2 of the measurement error caused by the distortion of the output waveform in Equation 1 is canceled. , 0.

The switching noise during the operation of the output circuits 9 and 14 is generally larger than that of the input circuits 7 and 13. The term Tdum (vdd) -Tdum (vdd ') in equation 1 is the output circuit 9,
Since the operation periods of No. 14 match exactly as shown in FIG. 2, the power supply voltage conditions are considered to be the same for Tm and Td, and
d) -Tdum (vdd ') = Tdum (vdd) -Tdum (vdd) = 0, and the fluctuation of the timing due to the fluctuation of the power supply voltage between the circuit paths due to the delay time is canceled.

Further, when the transition times of the output waveforms are not aligned, the output circuit 14 of the dummy circuit path 16 operates during the operation of the circuit under test 8, and the power supply voltage of the circuit under test 8 may fluctuate. However, by making the transition times of the output waveforms coincide with each other as shown in FIG.
The circuit under test 8 is operated during the operation of Step 3, so that the fluctuation of the power supply voltage of the circuit under test 8 can be suppressed to a minimum, and the power supply dependency of the delay time can be measured with high accuracy. become.

As described above, according to the present embodiment, the input signal is provided so that the transition times of the output terminal Smo and the output terminal Sdo of the circuit path 11 to be measured and the dummy circuit path 16 are aligned, so that the circuit path under test The measurement error, which has been a problem in obtaining the delay time of the circuit under test from the difference between the delay time and the dummy circuit path, can be skillfully canceled, and the delay time of the circuit under test can be measured with high accuracy.

FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 3, the semiconductor integrated circuit 30 includes a voltage control delay line 31, a circuit path under test 3,
2. Dummy circuit path 33, phase comparator 34, charge pump 35, low-pass filter 36, and ring oscillator 3.
7.

An input digital signal 38, which is an internal signal of the semiconductor integrated circuit 30, is input to the input Smi of the circuit path under test 32 which is connected in series with the input circuit 39, the circuit under test 40, and the output circuit 41 in this order, and the delay time Tm Thereafter, the signal is output from the output terminal Smo via the buffer 45 as an output digital signal 46 which is an internal signal of the semiconductor integrated circuit 30, and is input to the phase comparator 34.

The input digital signal 38 is supplied to the voltage control delay line 3 whose delay time is controlled by the voltage of the control voltage line 42.
1 and is delayed by the delay time tdl, and the input circuit 4
3, input to the input terminal Sdi of the dummy circuit path 33 connected in series in the order of the output circuit 44, input to the buffer 47 equivalent to the output buffer 45 from the output terminal Sdo after the delay time Td, and input to the phase comparator 34 Is done.

The buffer 47 is a dummy buffer for equalizing the output load of the circuit path under test 32 and the output load of the dummy circuit path 33.

The input circuits 39 and 43 and the output circuits 41 and 44 are equivalent circuits. The electrical length of the connection between the input circuit 39 and the circuit under test 40 and the electrical length of the connection between the circuit under test 40 and the output circuit 41 and the input circuit 43
The electrical length of the connection between the circuit and the output circuit 44 is designed to be the same length, and each connection is designed so that the transition time of the signal waveform is equal to the logic threshold voltage.

The flow of signals after the phase comparator 34 will be described. The charge signal 48 and the discharge signal 49 are connected to the charge pump 35 from the phase comparator 34, and the output of the charge pump 35 is input to the control voltage line 42 of the voltage control delay line 31 via the low-pass filter 36.

FIG. 4 is a characteristic diagram of the voltage control delay line 31. The delay time tdl of the voltage control delay line 31 is
2 has a characteristic of monotonously decreasing with respect to the voltage Vcnt.

Generally, a voltage control delay line has a structure in which elements such as an inverter and a differential amplifier are connected in a chain. The voltage control mechanism of the delay time uses a PN junction capacitor that can control the voltage as the output load capacitance of the elements that compose the chain, or controls the constant current value using a constant current source in the load circuit of the element. Is achieved.

The delay lock loop of the DLL circuit 54 composed of the phase comparator 34, the charge pump 35, the low-pass filter 36, the control voltage line 42, and the voltage control delay line 31 will be described below.

The phase comparator 34 compares the transition time tSmo of the output terminal Smo with the transition time tSdo of the output terminal Sdo, and
When o> tSmo, only the charging signal 48 is activated and tSdo
When <tSmo, only the discharge signal 49 is activated and tSdo =
At tSmo, both the charge signal 48 and the discharge signal 49 are designed to be inactive.

When the charge signal 48 is activated, that is, when tSdo> tSmo, the charge pump 35 charges the capacitance constituting the low-pass filter 36, and raises the control voltage Vcnt of the control voltage line 42. As a result, the delay time tdl of the voltage control delay line 31 is reduced, the transition time tSdo in the dummy circuit path 33 is advanced, and the state of the circuit changes in the direction of tSdo = tSmo.

When the discharge signal 49 is activated, that is, when tSdo <tSmo, the capacitance forming the low-pass filter 36 is discharged, and the control voltage of the control voltage line 42 is controlled.
Vcnt is decreased, the delay time tdl of the voltage control delay line 31 is increased, the transition time tSdo in the dummy circuit path 33 is delayed, and the state of the circuit changes in the direction of tSdo = tSmo.

The time until the circuit operation stabilizes to the state of tSdo = tSmo and the stability depend on the parameters of the low-pass filter 36.

When the circuit operation is stable at tSdo = tSmo, that is, when the circuit is locked, both the charge signal 48 and the discharge signal 49 become inactive, the output of the charge pump 35 becomes a high impedance state, and the control voltage Vcnt of the control voltage line 42 Is retained. The delay time of the voltage control delay line 31 at this time
tdl becomes equal to the delay time Tpd of the measured circuit 40 to be obtained. That is, tdl = Tpd.

The ring oscillator 37 is constituted by a ring connection of N voltage control delay lines 50 equal to the voltage control delay line 31 and an inverter 51 and oscillates at a frequency of f = 1 / (2 × Td1 × n). . The oscillation output 53 is output from the buffer 52.

Since the control voltage line 42 is connected to the voltage control delay line 50 constituting the ring oscillator 37, tSdo =
When the circuit operation is locked to tSmo, the ring oscillator 37
Is the above-mentioned frequency f = 1 / (2 × Td1 × n)
Becomes

As a method of reading out the delay time, the oscillation output of the ring oscillator 37 was read out to the outside.
It is of course conceivable to amplify the analog voltage of the control voltage line 42 or convert it to a digital value and read it out.

The charge pump 35 is provided with an optional sampling stop signal 56. Table 1 shows the sampling stop signal 56, the charge signal 48, and the discharge signal 4
9 shows the relationship of the control voltage line 42. When the sampling stop signal 56 is activated, the control voltage line 42
8. The state is held regardless of the state of the discharge signal 49.

If the sampling stop signal 56 is activated during the delay time measurement by providing the sampling stop signal 56, even if the input digital signal 38 is stopped during the measurement period or the intermittent operation is performed, the accuracy of the measurement data is impaired. It will not be. Further, when the circuit under test 40 takes a plurality of delay times Tpd according to the state of the control signal 55, the sampling stop signal 56 is deactivated in synchronization with the control signal 55 in a desired state, so that the circuit under test 40 The delay time can be measured selectively.

[0075]

[Table 1] The same effect can be obtained even if the sampling stop signal 56 is realized by the phase comparator 34 in a state where both the charge signal 48 and the discharge signal 49 are inactive.

As described above, according to the present embodiment, the DLL (delay lock loop) circuit 54 and the dummy circuit path are connected to the circuit path under test 32 to which the input digital signal 38 is input and output as the output digital signal 46. By connecting the delay measuring circuits 57 constituted by 33 in parallel, it is possible to measure the delay time of the circuit under test 40 as the delay time of the voltage control delay line 31 with high accuracy and easily.

Further, by providing a ring oscillator 37 composed of a voltage control delay line equivalent to the voltage control delay line 31 and making the voltage control delay line 31 and the control voltage line 42 common, measurement from outside the semiconductor element can be performed. Even a difficult delay time can be easily measured from a single output line in terms of the frequency of the ring oscillator 37 that can be easily measured.

Next, a flowchart of the delay time method according to the third embodiment of the present invention is shown in FIG. FIG. 5 shows a procedure for obtaining the delay time of the circuit under test 8 of the semiconductor integrated circuit 2 of FIG. 1 using a logic tester or the like.

FIG. 5 will be described below step by step with reference to FIG.

(Step 1) First, transition times tSmi and tSmi of the input signals supplied from the logic tester to the input terminal Smi of the circuit path under test 11 and the input terminal Sdi of the dummy circuit path 16
Sdi is initialized to 0 [ns].

The output transition time of the circuit path under test 11
Time difference between tSmo and output transition time tSdo of dummy circuit path 16
Output transition time difference as a variable that stores the tSmo-tSdo Tsw_
New and Tsw_old are initialized to 0 [ns]. In a software language such as the C language, it is expressed as follows.

Tsw_new = 0; Tsw_old = 0; (Step 2) Next, as the value of the input transition time tSdi of the dummy circuit path 16, the output transition time difference Tsw_new is 0 <
The value multiplied by the coefficient k of k ≦ 1 is accumulated to the accumulated value.

The input transition time tSmi of the circuit under test 11
Is initialized to 0 [ns] in step 1, the input time tSdi corresponds to the delay time of the input terminal Sdi of the dummy circuit path 16 with respect to the input terminal Smi of the circuit path under test 11. In a software language such as the C language, tSdi is expressed as follows.

TSdi = tSdi + k * Tsw_new; When Step 2 is executed for the first time, since Tsw_new = 0, tSdi = 0 [ns] + k * 0 [ns] = 0 [ns].

(Step 3) Using the edge search function of the logic tester, the value of tSdi calculated in step 2 and the input time tSmi fixed to 0 ns are set as input timing conditions, and the circuit path under test 11 Output transition time tSmo
And the output transition time tSdo of the dummy circuit path 16 is measured.

(Step 4) Output transition time difference Tsw_old
The output transition time difference Tsw_n calculated in the previous loop iteration
Save the value of ew. In a software language such as the C language, it is expressed as follows.

Tsw_old = Tsw_new; When Step 4 is executed for the first time, Tsw_new = 0 [n
s], so that Tsw_old = 0 [ns].

(Step 5) Output transition time difference Tsw_new
Is recalculated using the output transition time tSmo and the output transition time tSdo measured in step 3. In a software language such as the C language, it is expressed as follows.

Tsw_new = tSmo-tSdo; (Step 6) The output transition time difference Tsw_new is not smaller than the predetermined threshold value ΔTpd and the output transition time difference Tsw_new and Tsw
When the absolute value of the difference of _old is not equal to or smaller than the predetermined threshold value ΔTpd2, the process loops to Step 2. In a software language such as the C language, it is expressed as follows.

If (! ((Tsw_new <ΔTpd) && (| Tsw_new-Tsw_old | <ΔTpd2))) ｛goto “step 2”;｝ The values of ΔTpd, ΔTpd2, and k of step 2 determine the convergence of the loop. I do.

(Step 7) Finally, the value of tSdi is obtained as the delay time Tpd of the circuit under test 8.

As described above, according to the present embodiment, since the output terminal Smo and the output terminal Sdo transition simultaneously, the shapes of the output waveforms can be made uniform, and the difference error of the delay time measurement due to the distortion of the output waveform can be obtained. Is sufficiently small and substantially minimized.

The output-related operations of the circuit path to be measured and the dummy circuit path are simultaneously performed, the output operations for generating power supply noise are simultaneously performed in parallel, and the delay time caused by the subtle power supply voltage fluctuation between circuit paths is reduced. The difference error of the measurement is small enough,
Substantially minimized.

Further, by accumulating the value of the input transition time tSdi to the value obtained by multiplying the output transition time difference Tsw_new by a coefficient of 0 <k ≦ 1, it is possible to gradually approach the state of tSdo = tSmo. Therefore, the oscillation between the state of tSdo> tSmo and the state of tSdo <tSmo can be suppressed, the convergence of the loop can be completed in a short time, and the delay time of the circuit to be measured can be obtained at high speed. .

Further, by setting the difference between the transition time differences tsw_old and tsw_new before and after the repetition to a predetermined threshold value ΔTpd2 or less as an end condition of the repetition process, the state of tSdo = tSmo can be obtained.
When oscillation occurs between the state of tSdo> tSmo or between the state of tSdo = tSmo and the state of tSdo <tSmo, it is possible to detect a pseudo convergence of the repetitive process, More accurate delay time can be obtained.

[0096]

According to the delay time measuring apparatus of the present invention,
For a circuit configuration in which the delay time of the circuit under test is determined from the delay time difference between the circuit path under test and the dummy circuit path, the output transition times of the two circuit paths and the power supply voltage The difference can be canceled by the difference between the delay times, and the delay time of the high-speed circuit to be measured can be measured with high accuracy.

Further, in the semiconductor integrated circuit of the present invention, by introducing the idea of a feedback loop into the measurement of the delay time, only one point observation of the delay control signal of the variable delay time circuit is required, and the delay of the circuit to be measured is reduced. Time can be obtained with high accuracy and ease.

In the semiconductor integrated circuit of the present invention, the delay time can be measured by the oscillation frequency by copying the delay time of the variable delay circuit to the ring oscillator. Further, the oscillation frequency can be measured only by monitoring a single line, and the delay time of the circuit element to be measured can be easily measured from outside the semiconductor element.

Further, in the semiconductor integrated circuit of the present invention, by providing a sampling stop signal input to the charge pump or the phase comparator, it is possible to stabilize the frequency measurement of the ring oscillator or to obtain a desired circuit state of the circuit under test. Can be selectively measured.

Also, in the delay time measuring method of the present invention, the convergence of the iterative process is completed in a short time by introducing a constant k into the accumulation of the delay difference tsw in the iterative process, and the delay of the circuit under test is increased at a high speed. You can ask for time.

Also, in the delay time measuring method of the present invention, the predetermined thresholds ΔTpd, ΔTpd2
, Pseudo convergence of the iterative process can be avoided and the measurement accuracy can be improved.

As described above, by using the present invention, it is possible to grasp the delay time value and the statistical variation of the circuit path that controls the operation speed of the digital circuit at both the prototype circuit and the product level, and to realize the high-speed operation. It can be used as a stepping stone in manufacturing a semiconductor integrated circuit with high yield.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a delay time measuring device according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram of the delay time measuring device according to the first embodiment.

FIG. 3 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a characteristic diagram of a voltage control delay line of the semiconductor integrated circuit according to the second embodiment.

FIG. 5 is a flowchart of a delay time measuring method according to a third embodiment of the present invention.

FIG. 6 is a signal waveform diagram in a conventional delay time measuring method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Delay time measuring device 2 ... Semiconductor integrated circuit 3 ... Pulse generation means 4 ... Variable delay time circuit 5 ... Phase detection means 6 ... Input terminal Smi 8 ... Measured circuit 10 ... Output terminal Smo 11 Circuit path to be measured 12 Input terminal Sdi 15 Output terminal Sdo 16 Dummy circuit path 17 Delay control signal 31 Voltage control delay line 32 Circuit path to be measured 33 Dummy circuit Path 34 Phase comparator 35 Charge pump 36 Low-pass filter 37 Ring oscillator 38 Input digital signal 40 Circuit under test 42 Control voltage line 48 Charge signal 49 Discharge signal 50: Voltage control delay line 53: Oscillation output 54: DLL circuit 56: Sampling stop signal 57: Delay measurement circuit Smi: Input terminal of the circuit to be measured Smo: Circuit to be measured Output terminal Sdi …… Dummy circuit path input terminal Sdo …… Dummy circuit path output terminal

Claims (8)

[Claims] 1. A circuit path to be measured including a circuit to be measured, and a dummy circuit path configured to bypass the circuit to be measured from the circuit path to be measured, and an input terminal of the circuit path to be measured
The delay time Tpd (= Tm-Td) of the circuit under test is determined by the difference between the delay time Tm between Smi and the output terminal Smo and the delay time Td between the input terminal Sdi and the output terminal Sdo of the dummy circuit path. In the delay time measurement of the configured semiconductor integrated circuit, the circuit path to be measured and the dummy circuit path are set so that transition times tSmo and tSdo of both output terminals Smo and Sdo of the circuit path to be measured and the dummy circuit path are aligned. A delay time measuring device configured to determine input signals of both input terminals Smi and Sdi. A variable delay circuit whose delay time is controlled by the delay control signal; a pulse generating means for generating an arbitrary digital signal; and a phase detecting means for measuring a time difference between signal transitions between the digital signals. The signal output of the pulse generating means is connected to the input terminal Smi of the circuit path to be measured and to the input terminal Sdi of the dummy circuit path via the variable delay time circuit, The output of the output terminal Smo and the output of the output terminal Sdo of the dummy circuit path are input to the phase detection means. From the phase detection means, the output terminals Sdo and Smo of the two circuit paths are supplied to the variable delay time circuit. The delay time measuring device according to claim 1, wherein the delay control signal is fed back so that the phases of the outputs match. 3. A circuit path to be measured including a circuit to be measured, a dummy circuit path having a configuration in which the circuit to be measured is bypassed from the path to be measured, and voltage control in which a delay time is controlled by a potential of a control voltage line. A delay line, a phase comparator that outputs a phase relationship between input signals, a charge pump that controls charging and discharging of the output line, and a low-pass filter that removes a high-frequency component of a potential change and holds an input charge. A ring oscillator constituted by a voltage-controlled delay line equivalent to the voltage-controlled delay line, wherein an input digital signal is input to the input terminal Smi of the circuit-under-test path.
Is connected to the input terminal Sdi of the dummy circuit path via the voltage control delay line, and the outputs of the output terminal Smo of the circuit-under-test path and the output terminal Sdo of the dummy circuit path are connected to the phase comparator. The charge signal output and the discharge signal output of the phase comparator are connected to the charge pump, and the output of the charge pump configures the control voltage line of the voltage control delay line and the ring oscillator via the low-pass filter. The voltage control delay line is connected in parallel to a control voltage line of a voltage control delay line equivalent to the voltage control delay line, and the delay time of the voltage control delay line is monotonically decreasing with respect to a control voltage. The transition time tSmo of the output terminal Smo is compared with the transition time tSdo of the output terminal Sdo of the dummy circuit path. When tSdo> tSmo, only the charge signal is activated, and when tSdo <tSmo, the charge signal is discharged. Signal is activated, and when tSdo = tSmo, the charge signal and the discharge signal are deactivated. When the charge signal or the discharge signal is activated, the charge pump discharges or charges the capacitance constituting the low-pass filter, respectively. And controlling a control voltage of the voltage control delay line to measure a delay time of the circuit under test based on an output frequency of the ring oscillator. 4. The charge pump according to claim 1, further comprising a sampling stop signal input, wherein when the sampling stop signal is activated, an output of the charge pump is forced to a floating state. The semiconductor integrated circuit according to claim 3. 5. A phase comparator comprising a sampling stop signal input, wherein a charge signal and a discharge signal are forcibly deactivated when the sampling stop signal is activated. The semiconductor integrated circuit according to claim 3. 6. A circuit under test including a circuit to be measured in which a signal input at time tSmi is output at time tSmo, and a circuit bypassing the circuit to be measured from the circuit under test path at time tSdi. In a delay time measuring method for obtaining a delay time of a circuit under test by a delay time difference from a dummy circuit path at which an input signal is output at time tSdo, an output transition time tSmo of the circuit under test and Time difference tsw = tSmo-tSdo from output transition time tSdo
While accumulating the value of the time difference tsw at the input time tSdi of the dummy circuit path as a termination condition of the iterative process that the value of the time difference tsw is equal to or less than a predetermined threshold value ΔTpd with the measurement error as a lower limit, The process of measuring the time difference tsw is repeated, and the difference between the input time tSdi of the dummy circuit path and the input time tSmi of the circuit under test obtained after the end of the repetition process is set as the delay time of the circuit under test. A delay time measuring method characterized by comprising: 7. When the value of the time difference tsw is accumulated at the input time tSdi of the dummy circuit path, a time difference tsw multiplied by a coefficient k satisfying 0 <k ≦ 1 is accumulated. The delay time measuring method according to claim 6. 8. The method according to claim 7, wherein a condition that the difference of the time difference tsw before and after the repetition is equal to or less than a predetermined threshold value ΔTpd2 is added as an end condition of the repetition process. Delay time measurement method.