JP2001245222A - Semiconductor device and control method thereof - Google Patents

Abstract

(57) [Summary] [Problem] To keep the variation of the output voltage of an image sensor due to the variation of an amplifying element or the detector itself within a dynamic range, and smoothly perform signal amplification and signal processing performed inside or outside the image sensor. To do. SOLUTION: A detection circuit 601 whose output signal level changes by changing a bias current, and a detection unit 604 which detects whether a signal output from the detection circuit is equal to or less than a threshold set within a dynamic range. A counter 605 for counting the number detected by the detection unit 604, and a bias current of the detection circuit 601 and a full-scale current value of the FPN correction circuit are automatically determined based on the value counted by the counter 605. A setting unit 607 for setting the output signal level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a control method thereof, and more particularly to a semiconductor device in which an output signal level is changed by changing a bias current. The present invention relates to a detector array, a display array, a detector array for detecting visible light, infrared rays, ultraviolet rays, ultrasonic waves, pressure, and the like, a display array semiconductor device for outputting these, and a control method therefor.

[0002]

2. Description of the Related Art As an example of such a semiconductor device, there is an imaging device described in, for example, JP-A-11-150683. FIG. 12 shows a circuit diagram of this conventional imaging device. This circuit integrates a plurality of pixels so that a two-dimensional infrared image can be obtained. On a semiconductor substrate, a thermoelectric conversion element 1101, an NPN transistor 1102, a resistor 1103, a PNP transistor 1104, a switch 1100, an FPN correction constant current source 1
113, integrating capacitor 1105, reset switch 1
106 are formed.

In FIG. 12, a thermoelectric conversion element 1101
In this example, a bolometer whose electric resistance value changes according to the temperature is used, and titanium is used as the bolometer. Titanium bolometer 1101 is sensitive to incident infrared radiation. When the voltage VB1 is applied to the base of the NPN transistor 1102, the NPN transistor 11
Assuming that the base-emitter voltage of V02 is VBE, a voltage of (VB1 -VBE) is applied to the titanium bolometer 1101.
Assuming that the resistance of the titanium bolometer 1101 is RB1, NP
IC1 = (VB1
-VBE) / RB1 will flow.

Assuming that the resistor 1104 is RB2, since RB2 is used as a reference for the titanium bolometer 1101, the resistance value of the resistor 1104 is
01 is the same as the resistance value. PNP transistor 110
When the base voltage VB2 of 3 is applied, the PNP
The collector of the transistor 1103 has IC2 = (VB2−
VBE) / RB2 flows.

A base voltage 1103 is set so that the currents IC1 and IC2 are balanced with the incident infrared rays cut off. Therefore, almost no current flows through the integration capacitor 1105. When infrared rays are incident, the temperature of the thermally separated diaphragm increases, and the resistance value of the titanium bolometer 1101 on the diaphragm changes. This change in resistance changes IC1. Since the resistance value of the diffusion resistor 1104 on the substrate does not change, IC2 does not change. This change in IC1 results in a difference ΔI = (IC2−IC1), which is stored in the integrating capacitor 1105. This difference ΔI is a signal component and a bias component that cannot be removed, and a large bias component is removed.

In the example disclosed in Japanese Patent Application Laid-Open No. 11-150683, when the variation in resistance between pixels is large, an FPN (abbreviation of fixed pattern noise) correction circuit 1 is used.
In steps 106 to 1108, a current Ifpn is supplied to each pixel. If RB1 is larger than the standard, IC1 flowing to RB1 will be smaller. Since IC2 is constant, the difference ΔI increases.
By flowing the current Ifpn, IC2 = (IC2-Ifpn), and the difference due to the resistance variation is corrected.

The signal stored in the integration capacitor 1105 is converted from high impedance to low impedance by a source follower composed of NMOS transistors 1107 and 1108. A sample and hold circuit including a switch 1109 and a hold capacitor 1110 samples signals input in time series and temporarily holds the signals. The switch 1109 includes a transfer gate that connects a PMOS transistor and an NMOS transistor. NMOS transistor 111
1, 1112 also constitutes a source follower, and is output to S / Hout 1114 with low impedance.

[0008]

SUMMARY OF THE INVENTION Japanese Patent Application Laid-Open No. H11-1506
According to the technique disclosed in Japanese Patent No. 83, when the resistance value varies in a larger direction, the variation can be corrected by the FPN correction current. However, when the resistance value varies in a smaller value, or when the full-scale of the FPN correction current is used. If the variation is larger than the current, it is necessary to adjust the canceller current. Until now, since there was no hardware or software for adjustment, it was performed by a method of manually adjusting the canceller current, but this is a complicated operation. Also, when the canceller current is fixed, the resistance value varies in a smaller direction, or when the variation of the FPN correction current is larger than the full-scale current, the correction cannot be completed.
It is difficult to increase the signal amplification.

Normally, in an image pickup apparatus including a plurality of pixels, there is variation between pixels. This is particularly noticeable in infrared imaging devices and amplification type imaging devices. Some of the causes of these pixel-to-pixel variations are variations in detectors such as bolometers, and some are variations in VT and parasitic capacitance of the amplification elements. Taking a bolometer type infrared imaging device as an example, the bolometer resistance varies from several percent to several tens percent due to variations in the thickness of the bolometer film, variations in the specific resistance, and variations in dimensions when patterned.

[0010] Such variations greatly hinder the reading of signals. For example, when a subject having a temperature difference of 1 ° C. is viewed, the temperature change of the bolometer section is about 1 m ° C., and the resistance change of the bolometer due to this is about 0.001% as the bolometer has a resistance temperature coefficient of 1% / ° C. It is preferable to amplify the resistance on the image sensor in order to read the weak resistance change. However, if the resistance variation between pixels is large, the dynamic range of the amplifier circuit is limited by the variation and the amplification degree cannot be increased.

An example of correcting the variation of the detector itself is disclosed in Japanese Patent Application Laid-Open No. H11-150683.
If the resistance of the detector fluctuates to the higher side, FPN
It is possible to correct by extracting the canceller current with the correction current.However, if the resistance value of the detector varies in a smaller direction, even if the canceler current is extracted with the FPN correction current, the variation will only increase. Cannot be corrected. Until now, since there was no hardware or software for adjustment, it was performed by a method of manually adjusting the canceller current, but this is a complicated operation. If the canceller current is fixed, if the resistance value fluctuates to the smaller side, or if the variation of the FPN correction current is larger than the full-scale current, the correction cannot be completed and the signal amplification should be increased. Is difficult. Similarly, for the full-scale current of the FPN correction current,
If fixed, the correction cannot be completed if the variation is large, and if the variation is small, the correction range is unnecessarily widened although resolution can be improved originally.

An object of the present invention is to examine variations in the resistance value of a detector and automatically set a full-scale current value of a bias canceller current and an FPN correction current to an optimum value, thereby obtaining a bias canceller current or an FPN correction current. Provided is a semiconductor device and a control method for a semiconductor device capable of keeping an output signal within a dynamic range when a variation is corrected by flowing a current and smoothly performing signal amplification and signal processing performed inside or outside an image sensor. It is to be.

[0013]

A semiconductor device according to the present invention has a detection element, and changes a bias current of the detection element and a full-scale current of correction means for correcting fixed pattern noise of the detection element. A signal processing circuit that changes the level of the detection output signal by causing the signal to be output; a comparing unit that compares a signal output from the signal processing circuit with a threshold set within a dynamic range of the circuit; It is characterized by including counting means for counting the result, and control means for controlling a bias current of the signal processing circuit and a full-scale current of the correction circuit based on a value counted by the counting means.

The control means designates the number of detected pixels below or above the threshold, manipulates the MSB (most significant bit) of the bias current of the signal processing circuit, and designates the count result of the count means. The MSB of the bias current is determined from the comparison result of the number of pixels, and the value of each bit of the bias current is sequentially determined by the same operation and determination up to LSB (least significant bit). .

[0015] The control means may include a bias current value when the number of detected pixels below the threshold reaches the specified number of pixels, and a bias current value when the number of detected pixels exceeding the threshold reaches the specified number of pixels. , Respectively, and the full-scale current value of the correction means is determined from these bias current values.

The control means may further comprise a bias current value when the number of detected pixels below or above the threshold reaches a specified lower limit set value, and a bias current value when the number of detected pixels below or above the threshold becomes a specified upper limit set value. And a bias current value at that time, and a full-scale current value of the correction means is determined from these bias current values.

Further, the control means designates a full-scale current value of the correction means, and counts a current at a certain bias current and a count value at a current value obtained by subtracting the full-scale current of the correction means from the bias current. It is characterized in that the bias current is determined so that the result is almost the same.

According to the control method of the present invention, a detection output signal is provided by changing a bias current of the detection element and a full-scale current of correction means for correcting fixed pattern noise of the detection element. A method for controlling a semiconductor device including a signal processing circuit having a variable level, wherein a comparison step of comparing a signal output from the signal processing circuit with a threshold set within a dynamic range of the circuit; And a control step of controlling a bias current of the signal processing circuit and a full-scale current of the correction circuit based on the value counted in the counting step.

In the control step, the number of detected pixels equal to or less than the threshold is specified, the MSB (most significant bit) of the bias current of the signal processing circuit is manipulated, and the result is specified as the count result of the count step. Of the bias current from the comparison result of the number of pixels
, And the value of each bit of the bias current is determined by the same operation and determination up to the LSB (least significant bit).

[0020] The control step may include a step of determining a bias current value when the number of detected pixels below the threshold reaches the specified number of pixels, and a step of setting a bias current value when the number of detected pixels exceeding the threshold reaches the specified number of pixels. , Respectively, and the full-scale current value of the correction means is determined from these bias current values.

Further, in the control step, the bias current value when the number of detected pixels below or above the threshold reaches a specified lower limit set value and the number of detected pixels below or above the threshold become a specified upper limit set value. And a bias current value at that time, and a full-scale current value of the correction means is determined from these bias current values.

Still further, in the control step, a full-scale current value of the correction means is designated, and a count result at a certain bias current and a count value at a current value obtained by subtracting the full-scale current of the correction means from this bias current are designated. It is characterized in that the bias current is determined so that the result is almost the same.

[0023]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an overall view of an imaging apparatus showing one embodiment of the present invention. On a semiconductor substrate, a thermoelectric conversion element 101, an NPN transistor 102, a PNP transistor 103, a resistor 104, a resistor 105 having a binary resistance value, an NPN transistor 106, F
A PN correction switch 107, an integration capacitor 108, and a reset switch 109 are formed. Thermoelectric conversion element 1
01 uses a bolometer formed on a diaphragm in this example, and is sensitive to incident infrared rays. This thermoelectric conversion element 101 has one
It is formed in a large number of dimensions or two dimensions, and is switched by the switch 100 and sequentially selected.

When the voltage VB1 is applied to the base of the NPN transistor 102, the thermoelectric conversion element 1 is applied when the voltage between the base and the emitter of the NPN transistor 102 is VBE.
01 is applied with a voltage of (VB1 -VBE). Assuming that the resistance of the thermoelectric conversion element 101 is Rb1, the NPN transistor 10
A current of IC1 = (VB1-VBE) / Rb1 flows through the collector of the second.

The base of the NPN transistor 102 is VB1
It is connected to a bias setting circuit 131. The VB1 bias setting circuit 131 is a constant voltage source for adjusting the base voltage VB1 of the NPN transistor 102, and has a configuration such as the circuit elements 200 to 211 shown in FIG.

The VB1 bias setting circuit 131 includes a shift register 200, a switch 201, a resistor 202 connected to its drain, an NPN transistor 203, a PNP transistor 206 connected to its collector,
A PNP transistor 204 connected to the collector of the PN transistor 203; a resistor 205 connected to the PNP transistor; a PNP transistor 210 connected to the base of the PNP transistor 204;
A resistor 211 connected to the emitter of the P transistor
, An NPN transistor 209 connected to the collector of the PNP transistor 210, an NPN transistor 208 connected to the collector of the PNP transistor 210, and a resistor 207 connected to the emitter of the NPN transistor 210. Bias setting circuit 131
Is composed of several stages of constant current sources, and the current value of each constant current source is weighted by an integer power of two, such as I ₀ , 2I ₀ , 4I ₀ ,. In order to perform the weighting of an integer power of 2, the resistor 202 is weighted by an integer power of 2 such as 2R1, R1, R1 / 2,. In order to minimize the variation in the resistance, each resistance is obtained by combining a unit resistance R1.

The emitter size of the NPN transistor 203 is double (m = 2), quadruple (m = 4), based on the emitter size of the current I ₀ stage (m = 1).
Weights are given in proportion to the current as in. The above-described base voltage VB1 of the NPN transistor 102 can be adjusted by turning on / off the switches of each stage. When the constant current source is a bit having n stages, the aforementioned NP
The base voltage VB1 of the N transistor 102 can be adjusted to 2 ⁿ .

The reason for changing the emitter size (m) is as follows. The base current IB and the base - the relationship between the emitter voltage VBE is the reverse leakage current IB _0, the elementary charge q, the Boltzmann constant k, absolute temperature as _{T, IB = mIB 0 Exp [} qVBE / k / T ]. The base current is given by IB = I
Since it is expressed by C / β, if the collector current changes while m is constant, VBE also changes. Since the same voltage Vb1 is applied to the base of each transistor, the V
If the BE is different, the current value of each stage will not be exactly as described above. by changing m in proportion to the current value,
BE is the same, and the current value can be set as described above.

This configuration of connecting a resistor to the emitter is equivalent to N
This has the effect of reducing the effects of shot noise of the PN transistor 103, Johnson noise of the base resistance (rbb), and noise of a constant voltage source connected to the base.

When the voltage VB2 is applied to the base of the PNP transistor 103, a current of IC2 = (VB2-VBE) / Rb2 flows through the collector of the PNP transistor 103 as described above. Here, Rb2 is the resistance value of the resistor 104. IC1 and IC2 are almost balanced, and a small difference ΔI = (IC2−IC1) flows through the integrating capacitor 108. This difference ΔI is a signal component and a bias component that cannot be completely removed, and most of the bias components have been removed.

The base of the PNP transistor 103 is VB2
It is connected to a bias setting circuit 132. The VB2 bias setting circuit 132 is a constant voltage source for adjusting the base voltage VB2 of the PNP transistor 103, and has a configuration such as circuit elements 212 to 230.

The VB2 bias setting circuit 132 includes a shift register 212, a switch 213, a resistor 214 connected to its drain, an NPN transistor 215, an NPN transistor 217 connected to its collector, a resistor 216 connected to its emitter, and an NPN PNP transistor 22 connected to the collector of transistor 215
0 and PNP transistor 21 connected to its emitter
8, a resistor 219 connected to its emitter, an NPN transistor 222 connected to the base of an NPN transistor 215, and a resistor 2 connected to its emitter.
21, an NPN transistor 223 connected to the base of the NPN transistor 222, a PNP transistor 224 connected to the base thereof, a resistor 225 connected to the emitter thereof, a PNP transistor 229 connected to the base of the PNP transistor 224, and an emitter thereof 230 connected to PNP transistor 2
NPN transistor 228 leading to collector of 29
And an NPN transistor 227 connected to the emitter
And a resistor 226 connected to the emitter. The bias setting circuit 132 includes 214 to 215 stages of constant current sources, and the current values of the constant current sources are I ₁ and 2I.
Weights are raised to the power of 2 such as ₁ , 4I ₁ ,. To weight this integer power of two, a resistor 2
14 is weighted by an integer power of 2, such as 2R1, R1, R1 / 2,. In order to minimize the variation in the resistance, each resistance is obtained by combining a unit resistance R1.

216, 2 of the VB2 bias setting circuit 132
The current I2 flowing to the constant current source 17 is the current I2 flowing to the constant current sources 207 and 208 of the VB1 bias setting circuit 131.
This is the same current value as 2. The current I3 flowing to the constant current sources 222 and 221 of the VB2 bias setting circuit is a quarter of the current I2 flowing to the constant current sources 207 and 208 of the VB1 bias setting circuit.

Further, the emitter size of the NPN transistor 215 is twice (m = 2), four times (m = 4) based on the emitter size of the stage of the current I1 (m = 1).
Weights are given in proportion to the current as in. The above-described base voltage VB2 of the NPN transistor 103 can be adjusted by turning on / off the switches of each stage. When the constant current source is a bit having n stages, the aforementioned NP
The base voltage VB2 of the N transistor 103 can be adjusted to 2 ⁿ .

The base of the NPN transistor 106 is V
It is connected to the B0 bias setting circuit 130. The VB0 bias setting circuit is a constant voltage source that adjusts the base voltage VB0 of the NPN transistor 106, and has a configuration such as the circuit elements 231 to 237 in FIG.

The VB0 bias setting circuit 130 includes a shift register 231, a switch 232, a resistor 233 connected to any drain, an NPN transistor 234, a PNP transistor 235 connected to its collector, and N
PNP transistor 236 connected to the collector of PN transistor 234 and resistor 23 connected to the emitter
Consists of seven. 233-234 of the bias setting circuit 130
Is composed of several stages of constant current sources, and the current value of each constant current source is weighted by an integer power of two, such as I4, 2I4, 4I4,. The resistance 233 is weighted by an integer power of 2 such as 2R1, R1, R1 / 2,. In order to minimize the variation in resistance, each resistance is obtained by combining a unit resistance called R1.

Further, the emitter size of the NPN transistor 234 is double (m = 2), quadruple (m = 4) based on the emitter size of the current I4 stage (m = 1).
Weights are given in proportion to the current as in. The above-described base voltage VB0 of the NPN transistor 106 can be adjusted by turning on / off the switches of each stage. When the constant current source is a bit having n stages, the aforementioned NP
The base voltage VB0 of the N transistor 234 can be adjusted to 2 ⁿ .

To reduce the temperature drift of the imaging device,
Currents I0, 2I0, 4I of VB1 bias setting circuit 131
0,... And the current I1 of the VB2 bias setting circuit 132
, And the currents I4, 2I4, 4I4,... Of the VB0 bias setting circuit 130 need to have low temperature dependence. The current values serving as references for the current values I1, I1, 4I1, ... and the current values I2, 2I2, 4I2, ... are I0, 2I0, 4I0, .... The base applied voltage REFIN, which is a reference for this current value, is designed so that the temperature dependency is reduced. In order to reduce the temperature dependence, it is preferable to use a constant voltage source having extremely low temperature dependence, such as a band gap reference.

The signal stored in the integrating capacitor 108 is converted from high impedance to low impedance by a source follower composed of NMOSFETs 110 and 111. Switch 112, hold capacitor 113
Is sampled and temporarily held by sampling a signal input in time series. The switch 112 is composed of a transfer gate connecting the sources of the PMOSFET and the NMOSFET and connecting the drains of the PMOSFET and the NMOSFET. The NMOSFETs 114 and 115 also constitute a source follower, and output to the amplifier 16 with low impedance. Other configurations will be described later.

FIG. 3 is a circuit diagram of the entire image pickup device including the readout circuit of FIG. 1 and its periphery. The readout circuit includes a horizontal shift register 301 and a multiplexer 302, a readout circuit 303, an FPN correction buffer 304, an FPN correction current source 305, a thermoelectric conversion element 101, and a pixel switch 10.
0, vertical shift register 308, bias setting circuit 30
9 mag.

In this example, the thermoelectric conversion elements 101 are formed two-dimensionally on a substrate in a matrix,
It is switched by 0 and sequentially selected. In order to read out the signal of each thermoelectric conversion element, in this example, a reading out circuit 303 is formed in each column of the matrix to read out the signal. There is the following trade-off in how the readout circuit is formed.

When a readout circuit is formed in each column. Since each column can perform the read operation at the same time, the read time can be lengthened. If the read time is long, the noise band can be narrowed accordingly, and the noise can be reduced. On the other hand, the number of readout circuits increases and the chip area increases.

If one readout circuit is used by dividing into a plurality of columns, the number of readout circuits is reduced and the chip area is reduced. On the other hand, the reading time is shortened and the noise band is widened by the time division sharing.

The vertical shift register 308 sequentially selects each row of the matrix.

FP supplied to FPN correction current source 305
The N correction data stores correction data for all pixels in a memory outside the chip, for example. When the readout circuit of each column performs a readout operation such as integration, the buffer 304 holds FPN data of the pixel being read out.

The bias setting data supplied to the bias setting circuit 309 is serially provided by, for example, a switch or a memory outside the chip, and is stored in a shift register in the bias setting circuit. Noise filter 31
In the case of 0, for example, a CR filter is provided outside the chip to remove noise.

The output of the readout circuit 303 in each column is connected to a sample and hold circuit in each readout circuit 303. The sample / hold output S / Hout of each column is sequentially selected by the multiplexer 302 and is output to the output out. The horizontal shift register 301 sequentially selects the switches of the multiplexer 302 in each column, and also selects the FP in each column.
The N data buffers 304 are sequentially selected. F
PN DATA is a data bus connected to the FPN data buffer 304. For example, the PN DATA is a FPN correction constant current source 3 for each column.
When 05 is 3 bits, there are three lines. BIAS
DATA is a data bus connected to the FPN correction current source 305 and the readout circuit circuit 303. For example, when three transistors need to be set, three lines are used.

FIG. 4 is a timing chart showing the signal timing of each section. φV is, for example, a vertical synchronization signal of about 30 Hz, and is input to the data terminal V of the vertical shift register 308. φH is, for example, a horizontal synchronization signal of about 7 kHz, and is input to the clock terminal H of the vertical shift register 308. Thereby, a signal for selecting each row of V1, V2,... Is output from the vertical shift register 308.

While a certain row is selected, a read operation at the time of integration is performed in the read circuit of each column. VC is a voltage waveform (integrated waveform) of the integrating capacitor 108 in FIG. ΦS / H is applied to the sample and hold circuit 112, and the voltage after integration is sampled and held in the hold capacitor 113. After sampling, a reset pulse φR is applied to the reset switch 109 to reset the integrating capacitor 108.

Data terminal H of horizontal shift register 301
, And signals φ1, H2,... Are obtained. Are the multiplexer 302 and the FPN data buffer 30 shown in FIG.
4 are sequentially selected.

ΦH ′ may use the same signal as φH. The signal held in the hold capacitor of each column is output to the output terminal via the multiplexer 302 as indicated by OUT.

The FPN data (FPN DATA) is transferred to the FPN data buffer before reading a certain row. The control terminal of the data buffer 304 in FIG.
1, H2, ... are input.

Bias setting current (BIAS DATA)
Is transferred to the bias setting circuit before or during reading by the reading circuit 303. Each voltage generated by the bias setting circuit passes through the noise filter 310 and sets the base of the transistors 102 and 103 of the reading circuit 303 and the base voltage of the transistor 106 of the FPN 305.

FIG. 5 is a block diagram of the whole image pickup apparatus showing one embodiment of the present invention. The imaging device includes an imaging device 50
1, amplifier 116, sample hold 117, A / D converter 118, VRAM 121, FPN memory controller 119, FPN memory 120, digital subtractor 1
36, D / A converter 134, NTSC signal generator 1
35, a comparator 122, an FPN memory controller 123, an FPN memory 124, a comparator 125, a counter 126, a comparator 127, a bias data creation circuit 517, and the like.

The image pickup device 501 has, for example, the structure shown in FIG. 3 formed on one silicon substrate. The incident light is condensed on the image sensor 501 by the optical system 520, converted into an electric signal by the image sensor 501, amplified by an integrating circuit or the like, and output to the outside. Amplifier 116 amplifies the output signal, and sample and hold circuit 117 temporarily holds the signal. The A / D converter 118 converts the held signal into a digital signal. Note that the amplifier 116
Can be omitted if the output signal of the image sensor 501 is sufficiently large.

The VRAM 121 is a memory for holding a digital signal of each pixel.
Assuming that the digital signal of one pixel is 12 bits with the number of pixels of × 240, the capacity may be 320 × 240 × 12 bits.

The FPN memory 120 stores F in the image sensor.
This is a memory for correcting the variation that cannot be removed by the PN correction, and holds variation data of each pixel to be corrected. The FPN memory controller 119 is a circuit for controlling the FPN memory 120,
The digital subtractor 136 is for subtracting the variation amount of each pixel from the signal of each pixel input in real time.

A with the incident light blocked by a shutter or the like
The data of each pixel output from the / D converter 118 has a variation that cannot be removed by the FPN correction in the image sensor. This data is stored in the FPN memory 120. This operation is performed when the power is turned on or when the previous correction is shifted. In a normal imaging state, the stored FP
The variation data of the N memory 120 is passed to the subtractor 136, and is subtracted from the signal of each pixel supplied in real time to obtain a signal falling within the dynamic range.

Note that the subtractor 136 is connected to the FPN memory 12
Naturally, it is possible to change to an adder, for example, by taking the complement of data of 0. The subtractor 136 is connected to the VRAM 12
1 and the D / A converter 134.

The D / A converter 134 converts the processed digital signal into an analog signal and outputs it to the NTSC signal generator 135. The NTSC signal generator 135 combines the analog signal and the synchronizing signal and outputs an NTSC composite signal. The NTSC signal generator is not limited to NTSC, but may be another type of signal generator such as PAL or RGB output as required.

The FPN correction circuit (10 in FIG. 1) in the image sensor
The acquisition of the correction data to be supplied to (5) to (107) is performed as follows. The comparator 122 is a digital comparator in this example, and determines the magnitude relationship between the signal level of each pixel and a certain reference level. This reference level is set to the upper or lower limit of the dynamic range of a signal processing circuit such as an integrating circuit, an amplifier or an A / D converter in the image sensor, or added to a value obtained by adding a margin of a level at the upper or lower limit. Can be set. The determination of the magnitude relationship can be determined to be good for a certain reference level or more, good for a certain reference level or less, or good for a certain two reference level ranges.

The FPN memory controller 123 creates FPN correction data according to the comparison result. The created correction data is held in the FPN memory 124.
The FPN memory 124 may have a capacity obtained by multiplying the total number of pixels by the number of bits of the FPN correction data. For example, 320
In the case of the number of pixels of × 240, if the number of bits of the FPN correction data is 3, the capacity of 320 × 240 × 3 bits is sufficient. In order to control data on a byte basis, it is possible to increase the capacity as needed.

The acquisition of the bias setting data to be supplied to the bipolar transistors (102, 103, and 106 in FIG. 1) in the image sensor is performed as follows. Comparator 12
Reference numeral 5 denotes a digital comparator in this example, which determines a magnitude relationship between a signal level of each pixel and a threshold set within a dynamic range. This threshold is determined by the integration circuit, amplifier, A / D converter, etc. in the image sensor.
It can be set to the upper or lower limit of the dynamic range of the signal processing circuit, or to a value obtained by adding a margin of a certain level to the upper or lower limit. The determination of the magnitude relationship can be determined as good for a threshold or more, good for a threshold or less, or good for a certain two threshold ranges.

The counter 126 counts according to the comparison result. In this case, either the case where the judgment result of the comparator 125 is good or the case where the judgment result is bad is counted, or both of the judgment results of the comparator 125 are counted using two counters 126. You can also

The comparator 127 is a digital comparator in this example, and determines the magnitude relationship between the count value of the counter 126 and a certain reference level. As the reference level, the number of pixels above the threshold set within the dynamic range, the number of pixels below the threshold, and the like can be set.

The bias data creation circuit 517 creates bias setting data according to the comparison result. The generated bias data is sent to a bias circuit 518 in the image sensor 501. The bias circuit 518 creates a bias voltage using a constant current source based on the digital data created by the bias data creation circuit.

The noise filter 310 is a low-pass filter in this example, and removes noise of the bias voltage generated by the bias circuit.

Reference numeral 521 denotes a temperature stabilizing element such as a Peltier that keeps the image pickup element at a constant temperature, and 522 denotes a control circuit thereof.

FIG. 6 is a block diagram of the entire apparatus showing an embodiment of the present invention, and is a high-level conceptual block diagram of the apparatus including the case where the image pickup device of FIG. 5 is used. This apparatus includes a detector 601, a sample hold 602, an A / D converter 603, a comparator 604, and a counter 60.
5, comparator 606, voltage setting circuit 607, D / A
It comprises a converter 608 and a subtractor 609.

The detector 601 is, for example, an image sensor 5 shown in FIG.
The detector changes the output signal level by changing the bias current as indicated by 01. In this example, the output signal is an analog signal. Sample and hold circuit 6
02 temporarily stores the signal. The A / D converter 603 converts the held signal into a digital signal.

The comparator 604 is a digital comparator in this example, and determines the magnitude relation between the output signal level of the detector and the threshold. This threshold can be set to the upper or lower limit of the dynamic range of the output signal, or to a value obtained by adding a margin of a level to the upper or lower limit. The determination of the magnitude relationship can be made as good when it is equal to or higher than the threshold, as good when it is equal to or less than the threshold, or as good when it is within a certain two threshold ranges.

The counter 605 performs counting based on the comparison result. In this case, either one of a case where the judgment result of the comparator 604 is good and a case where the judgment result is bad is counted, or two counters 605 are used.
Both the good and bad of the judgment result of the comparator 604 can be counted. The comparator 606 is a digital comparator in this example, and determines the magnitude relationship between the count value of the counter 605 and a certain reference level. As the reference level, a number equal to or greater than the threshold set within the dynamic range, a number equal to or smaller than the threshold, and the like can be set.

The voltage setting circuit 607 creates voltage setting data according to the comparison result. D / A converter 6
08 converts the generated digital signal into an analog signal. The subtractor 609 subtracts from the signal of the detector 601 supplied in real time to obtain a signal falling within the dynamic range.

FIG. 7 is a flowchart showing a method for generating a bias current value of the read circuit. It is assumed that the bias current value is 3 bits. Step 701 of setting the threshold, and setting the position of the bit of the bias current value to MS
Step 702 for changing from B (most significant bit) to LSB (least significant bit); step 703 for setting the count value of the counter and setting the bit of interest in step 702 to 1; and step 704 for changing the V address. 705 for changing the H address
Step 706 for performing a conditional jump based on the threshold determination, Step 707 for counting pixels below the threshold, and Step 70 for determining the flag
8 and a step 709 for resetting the bit to 0.

The flow of steps 701 to 709 is represented by an image 801 in FIG. The horizontal axis is the bias current value, the vertical axis is the number of pixels below the threshold,
In this example, when the bias current value is small, the current flowing through the transistor is small, so that almost all pixels below the threshold are used. As the bias current increases, the number of pixels below the threshold decreases.

At step 701, the threshold TH is set. The bias current value initially set in steps 702 and 703 is such that the MSB is 1 and the other bits are all 0.
Therefore, the bias current value of 1/2 (of 801 in FIG. 8)
It is. The number of pixels below the threshold set in step 703 is the pixel number setting value 801 in FIG. In steps 704 to 707, the number of pixels below the threshold is counted, and in step 708, a determination is made. When this is represented by the example of 801 in FIG. 8, the number of pixels below the threshold value at the time of the bias current is larger than the set value, so that the bias current value is smaller than the target current value.
The MSB is set to 1 as it is.

Returning to step 702, the bit of interest is shifted by one bit to the LSB side, and 1 is set. 801 in FIG.
In the example, the bias current value is "110", which is a 3/4 bias current value (at 801 in FIG. 8). Steps 704 to 70
The number of pixels below the threshold is counted at 7, and the determination is made at step 708. When this is represented by the example of 801 in FIG. 8, since the number of pixels below the threshold value at the time of the bias current is smaller than the set value, the bias current value is larger than the target current value. Set the bit to 0.

By repeating the loop from step 702 to step 709 until the LSB of the bias current value is obtained, the target bias current value can be obtained.

Referring to the flowchart of FIG. 7, step 701 is a part for setting a threshold (TH in FIG. 7). In this example, it is a judgment value of a digital comparator. This threshold can be set to the upper or lower limit of the dynamic range of the output signal, or can be set to a value obtained by adding a margin of a certain level to the upper or lower limit. Step 702 is a part for sequentially changing bits (b in FIG. 7) for operating from the MSB to the LSB, and performs a loop process as shown in FIG. Step 703 sets the count value of the counter (c in FIG. 7) and step 70
This is the part where the bit of interest (b in FIG. 7) is set to 1 in 2, and in this example, the count value is set to the number of pixels below the threshold. Step 704 is a part for changing the V address, and step 705 is a part for changing the H address. Steps 704 and 705 form a loop, and step 704 changes the V address from 0 to 239, for example. Step 705
Changes the H address from 0 to 319, for example.

In step 706, the subsequent processing is divided into two based on the judgment of the comparator. In this example, the data of the selected pixel ((V, H) in FIG. 7)
Is determined by a digital comparator. In this determination, if the value is equal to or smaller than the threshold set in step 701, the bias current value given to the pixel selected in step 704 or step 705 is equal to or smaller than the threshold.
At 7, the pixels below the threshold are counted. Step 707 is a down counter in this example,
Count down from the set value in step 703.

Step 708 is to divide the subsequent processing into two based on the judgment of the comparator. In this example, a method is employed in which a digital comparator determines whether the value counted in step 707 is 0 or less. In this determination, if the value counted in step 707 exceeds 0, in step 709, the bit b of interest in step 702 is reset to 0. If the result of the determination in step 708 is 0 or less, step 709 is not executed because bit b may remain 1.

In 802 of FIG. 8, in addition to the target value of 801, the number of pixels exceeding the threshold is compared with the set number of pixels to determine the bias current.
The full-scale current value of FPN is obtained from the two bias currents.

Referring to 802 in FIG. 8, the threshold is set and the number of pixels below the threshold is set (802).
First, the MSB of the bias current value is manipulated in the same manner as in the flow of FIG. 7 in order to obtain the target value, and MS is calculated from the comparison result between the count result and the pixel number set value.
B, and sequentially determine the respective bits of the bias current by the same operation and determination up to the LSB, and then operate the MSB of the bias current value in the same manner as in the flow of FIG. , The MSB is determined from the comparison result between the count result and the pixel number set value, and each bit of the bias current is determined by the same operation and determination up to the LSB.

The operation of 802 in FIG.
5 will be described. At the time of setting 802, the distribution of the signal level of each pixel is as shown at 805. Pixels below the threshold at this time are defective pixels. The pixel number setting value is set so that this defective pixel number group can be excluded.
At the time of setting 802, the distribution of the signal level of each pixel is as shown by 807 in FIG. Pixels above the threshold at this time are also defective pixels, and the pixel number setting value is set so as to exclude this defective pixel group. Note that the set pixel number may be different from the set pixel number.

Thus, the level of (1) can be known, and the level of (-) is set to the full scale of the FPN correction circuit. Thereafter, the level of the bias current is determined and the FPN correction is applied, so that the signal of each pixel is gathered near the threshold as indicated by 806 in FIG. As a result, the signal of each pixel has a wide dynamic range on the upper side. It is of course possible to set this threshold to the upper side and to have a wide dynamic range on the lower side. In addition, it is of course possible to configure the algorithm by appropriately replacing the value below the threshold with the value above.

In FIG. 8, reference numeral 803 denotes a bias current obtained by setting an upper limit value of the number of pixels below the threshold instead of counting the number of pixels exceeding the threshold of 802, and calculating FPN from the two bias current values. Is obtained.

Referring to 803 in FIG. 8, the threshold is set, the lower limit of the number of pixels below the threshold and the upper limit of the number of pixels below the threshold are set, and a target value is obtained in the same manner as in the flow of FIG. The MSB of the bias current value is manipulated, the MSB is determined from the result of the comparison between the count result and the pixel number set value, and the respective bits of the bias current are sequentially determined by the same operation and determination up to the LSB, and the next target value To determine the value, the MSB of the bias current value is manipulated in the same manner as in the flow of FIG. 7, and the MSB is determined from the comparison result between the count result and the pixel number set value. To determine.

As the upper limit set value, a value obtained by subtracting A from the total number of pixels can be set. A designates a pixel having a level exceeding 807, that is, the number of upper defective pixels. As a result, the pixels from which the defective pixels have been removed can be collected at a threshold as shown at 806 in FIG.

In FIG. 8, reference numeral 804 designates a full-scale current value of the FPN, instead of setting the number of pixels 802.
The bias current is determined so that the count result at a certain bias current and the count result at a current value obtained by subtracting the full-scale current value of FPN from this bias current are substantially the same.

Referring to 804 in FIG. 8, the threshold is set, the full-scale current value of FPN is set, and the MSB of the bias current value is operated in the same manner as in the flow of FIG. The result is obtained, and the count result for the bias current obtained by subtracting the full-scale current value of FPN from the bias current value at this time is also obtained.
The difference between the two count results is compared, the MSB is determined so that the difference between the two becomes smaller, and each bit of the bias current is determined sequentially by the same operation and determination up to the LSB.

This method is effective when it is not desired to increase the full-scale current of the FPN correction circuit. When the full scale is increased, the residual of the FPN correction circuit (80 in FIG. 9)
6) increases, and the degree to which the residual occupies the dynamic range increases.

As a method for obtaining the target value 804 in FIG.
In addition to the method of calculating each bit of the bias current from MSB to LSB, the bias current value is sequentially changed from the minimum value to the maximum value, and the number of pixels below the threshold and the number of pixels exceeding the threshold are all once determined. There is also a method of acquiring the target bias current value by taking it into a PC (the personal computer 133 in FIG. 1) and executing the above algorithm on software. The advantage of this method is that the circuit size of the logic can be reduced. In addition, the captured data can be displayed in a graph on the screen, which makes it easy to understand when setting the full-scale current value of the FPN.

FIG. 10 shows a relationship 901 between the frame and the algorithm for setting the bias current and the full-scale current of the on-chip FPN. φV is, for example, a vertical synchronization signal of about 30 Hz, and one cycle of this clock is one frame. First, configure the settings. The period of this setting differs depending on the number of bits of the shift register (SR in FIG. 2) in the bias circuit, but in this example, it is assumed to be 18 bits, which is 18 pixel clock periods. One frame is required to measure all pixels, and since 18 pixel clocks are used in the setting, all pixels cannot be measured in this frame. Therefore, a waiting time is provided until the next frame. In the second frame, the output signals of all pixels are compared and counted. At the same time as counting is performed, comparison with the set value of the count is also performed. Therefore, the comparison result is known at the same time when all the pixels are completed, and can be reflected in the setting of the next frame. This process is repeated by the number of bits of the bias current, or from the minimum value to the maximum value of the bias current value.

The operation of the contents of the integrating circuit for outputting the signal described above will be briefly described below. FIG. 11 shows an integration waveform of the integration capacitor section of the integration circuit. 100
No. 1 indicates that the bolometer has no self-heating or is negligibly small depending on the voltage applied to the bolometer.
The left diagram shows the waveform before the FPN correction is applied, and the right diagram shows the waveform after the FPN correction is applied. As described above, the search for finding the optimum canceller setting is performed so that the integrated waveform of the pixel having the minimum bolometer resistance is close to the lower limit of the dynamic range and is at the above-described threshold. Vm is
Since the bolometer resistance changes when an infrared ray is input, it is provided as a margin. The integrated waveform of the pixel having the maximum bolometer resistance often exceeds the upper limit of the dynamic range before correction.

By performing the FPN correction, the integrated waveform of each pixel gathers near the lower limit of the dynamic range as shown in the right figure. There is a limit in how to gather after correction due to the problem of the accuracy of FPN correction, and a residual is generated as shown in FIG. The sampling of the integrated waveform is performed at the end point in FIG. The occurrence of the residual in the integrated waveform is due to the quantization error of the correction circuit, and is not directly related to the magnitude of the bolometer resistance. That is, the large correction residual in FIG. 11 includes a large bolometer resistance and a small bolometer resistance.

Reference numeral 1002 denotes a case where the voltage applied to the bolometer generates relatively large self-heating in the bolometer. The left figure shows each waveform before FPN correction is applied, and the right figure shows each waveform after FPN correction is applied. It is assumed that the bolometer has a negative temperature coefficient of resistance TCR. As in the case of 1001, a search for finding an optimal canceller setting is performed so that the integrated waveform of the pixel with the minimum bolometer resistance comes to the threshold.

By performing the FPN correction, the integrated waveform of each pixel gathers near the lower limit of the dynamic range as shown in the right figure. Similarly to 1001, the large correction residual includes a large bolometer resistance and a small bolometer resistance. Therefore, the maximum amplitude Vmax of the integrated waveform is obtained by adding about の of the residual to the integrated waveform curve of the pixel having the minimum bolometer resistance. The reason for １ ／ is that the integral waveform bend becomes maximum at about の of the integration end point. From the figure on the right, to minimize Vmax in the presence of the integral waveform curve, the integrated voltage levels at the start and end points of the integral waveform are adjusted at the pixel with the small correction residual, and the residual is on the convex side of the integral curve. It turns out that it is good to make it.

When the temperature coefficient of resistance TCR of the bolometer is positive, the curve of the integral waveform is opposite to that described above. However, in the pixel having a small correction residual, the integral voltage levels at the start point and the end point of the integral waveform are adjusted, and the residual is integrated. The problem remains if it is made to be on the convex side of the bend.

A specific example of 1002 is shown below. When a so-called pulse bias drive for applying a voltage to each pixel in a time-division manner is used as the bolometer resistor, several kΩ to several tens
About kΩ can be considered. Bolometer temperature coefficient of resistance TC
As R, several% / K can be considered. The bolometer applied voltage is preferably about 0.5 V to about 5 V in order to increase the signal and to handle the voltage in a normal IC process. The integral capacitance is preferably about several pF to several hundred pF in order to increase the sensor output voltage by increasing the integral gain and to suppress the amplitude Vmax of the integral waveform to some extent. Integration time from several μs to several hundred μs
The degree is preferable for reducing the number of readout circuits and increasing the integral gain. At this time, the self-heating temperature of the bolometer ranges from several degrees Celsius to several tens degrees Celsius. It is preferable that the self-heating is small in order to reduce the bending of the integrated waveform,
Noise equivalent temperature difference NETD corresponding to sensor temperature resolution
Is often proportional to the square root of the Joule heat applied to the bolometer, that is, the square root of the self-heating temperature (for example,
Tanaka et al., Thermal Infrared Image Sensor, Electronic Information Technology E
D98-265 pp. 9-16) In that sense, a certain amount of self-heating temperature is required.

A bolometer resistance of about 10 kΩ, TCR
Assuming about −2% / K, about 2 V as an applied voltage, about 100 pF as an integration capacitance, about 30 μs as an integration time, about 30 times as an integration gain, and about 7 ° C. as a self-heating temperature, the integrated waveform bend Vmax becomes It is about 2V. The residual voltage varies depending on the number of bits of the FPN correction, but is about 0.2 V assuming about 6 bits.

[0101]

As described above, the present invention has the following effects. First, by having a constant current source that corrects the current value given to each pixel, it is possible to keep the variation of the output voltage of the image sensor due to the variation of the amplification element and the variation of the detector itself within the dynamic range. Alternatively, signal amplification and signal processing performed outside the imaging element can be performed smoothly.

Also, since the target bias current value is obtained by comparing the count value when the bit of the bias current is operated with the set value, the circuit size is small and the target bias current value can be obtained at high speed. Can be done. Further, another target bias current is added, the count value when the bit of the bias current is operated is compared with a set value to obtain a target bias current value, and the FPN correction circuit of the FPN correction circuit is obtained from those bias current values. Since the full-scale current value is obtained, the circuit scale is small, and the bias current value and FPN can be quickly set
The correction full-scale current value can be obtained at the same time.

Further, another set value is added, the count value when the bit of the bias current is operated is compared with the set value to obtain a target bias current value, and the FPN is calculated from those bias current values. Since the full-scale current value of the correction circuit is obtained, the circuit scale is small, and the bias current value and the full-scale current value of the FPN correction can be simultaneously obtained at high speed.

Further, the full-scale current value of the FPN correction circuit is designated, and the count result at a certain bias current is substantially the same as the count result at a current value obtained by subtracting the full-scale current of the FPN correction circuit from this bias current. Therefore, the bias current value when the full-scale current value of the FPN correction is freely set can be obtained at a high speed with a small circuit scale.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an entire image pickup apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a bias circuit in a read circuit according to one embodiment of the present invention.

FIG. 3 is a circuit diagram of an entire image pickup device of the image pickup apparatus according to the embodiment of the present invention.

FIG. 4 is a timing chart illustrating an operation of the imaging device of FIG. 1;

FIG. 5 is an overall block diagram illustrating an imaging apparatus according to an embodiment of the present invention.

FIG. 6 is an overall block diagram showing an apparatus according to an embodiment of the present invention.

FIG. 7 is a flowchart for setting a bias current.

FIG. 8 is a diagram schematically illustrating an algorithm for setting a bias current and a full-scale current of an on-chip FPN.

FIG. 9 is a diagram schematically illustrating an algorithm for setting a bias current and a full-scale current of an on-chip FPN.

FIG. 10 is a diagram showing a relationship between a frame and an algorithm for setting a bias current and a full-scale current of an on-chip FPN.

FIG. 11 is a diagram showing the operation of the contents of the integration circuit.

FIG. 12 is a circuit diagram of a conventional imaging device.

[Explanation of symbols]

 Reference Signs List 100 vertical switch 101 detector 102, 106 NPN transistor 103 PNP transistor 104, 105 resistor 107, 109, 112 switch 108 integration capacitor 110, 111 114, 115 NMOSFET 113 hold capacitor 116 amplifier 117 sample / hold circuit 118 A / D converter 119 FPN Memory controller 120 FPN memory 121 VRAM 122, 125, 127 Comparator 123 FPN memory controller 124 FPN memory 126 Counter 128 Bias controller 129 Parallel / serial converter 130-132 Bias circuit 133 PC (personal computer) 134 D / A converter 135 NTSC signal Generator 301 Horizontal shift register 30 2 Multiplexer 303 Readout circuit 304 FPN data buffer 305 FPN correction current source 308 Vertical shift register 309 Bias setting circuit 310 Noise filter

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme coat ゛ (Reference) H01L 27/14 Z F-term (Reference) 2F055 AA40 BB20 CC60 DD20 EE40 FF11 GG31 2G065 AB02 AB04 AB05 BA02 BA12 BA34 BC01 BC03 BC07 BC08 BC10 BC14 BC15 BC16 BC17 BC19 BC22 BC28 BC33 BD01 CA12 DA01 DA18 4M118 AA06 AB01 BA06 CA14 CB14 DD09 DD11 DD12 GA10 5C024 AX01 AX06 AX09 GX08 GX10 HX23 HX29 HX32 HX55 5J022 AA01 AB01 CF01 CF10

Claims (10)

[Claims] 1. A level of a detection output signal is changed by changing a bias current of the detection element and a full-scale current of a correction unit for correcting fixed pattern noise of the detection element. A signal processing circuit; comparison means for comparing a signal output from the signal processing circuit with a threshold set within a dynamic range of the circuit; counting means for counting a comparison result of the comparison means; A control means for controlling a bias current of the signal processing circuit and a full-scale current of the correction circuit based on the value counted in (1). 2. The method according to claim 1, wherein the control means specifies the number of pixels to be detected that is equal to or less than the threshold, operates the MSB (most significant bit) of a bias current of the signal processing circuit, and designates a count result of the count means. The MSB of the bias current is determined from the comparison result of the number of pixels, and the value of each bit of the bias current is sequentially determined by the same operation and determination up to LSB (least significant bit). The semiconductor device according to claim 1. 3. A bias current value when the number of detected pixels below the threshold reaches a specified number of pixels, and a bias current value when the number of detected pixels exceeding the threshold reaches a specified number of pixels. 2. The semiconductor device according to claim 1, wherein a full-scale current value of said correction means is determined from said bias current values. 4. The control unit according to claim 1, wherein the number of detected pixels below or above the threshold reaches a specified lower limit set value, and the number of detected pixels below or above the threshold becomes a specified upper limit set value. 2. The semiconductor device according to claim 1, wherein a bias current value at that time is obtained, and a full-scale current value of said correction means is determined from these bias current values. 5. The control means specifies a full-scale current value of the correction means, and counts a count result at a certain bias current and a count result at a current value obtained by subtracting the full-scale current of the correction means from the bias current. 2. The semiconductor device according to claim 1, wherein the bias current is determined so that the values are substantially the same. 6. A level of a detection output signal is changed by changing a bias current of the detection element and a full-scale current of a correction unit for correcting fixed pattern noise of the detection element. A control method for a semiconductor device including a signal processing circuit, comprising: a comparison step of comparing a signal output from the signal processing circuit with a threshold set within a dynamic range of the circuit; and a comparison result of the comparison step. A control method comprising: a counting step of counting; and a control step of controlling a bias current of the signal processing circuit and a full-scale current of the correction circuit based on the value counted in the counting step. 7. The control step specifies the number of pixels to be detected below or above the threshold, manipulates the MSB (most significant bit) of the bias current of the signal processing circuit, and specifies the count result of the count step. The MSB of the bias current is determined from the comparison result of the number of pixels, and the value of each bit of the bias current is sequentially determined by the same operation and determination up to LSB (least significant bit). The control method according to claim 6. 8. The method according to claim 1, wherein the controlling step comprises: setting a bias current value when the number of detected pixels below the threshold reaches the specified number of pixels; and a bias current value when the number of detected pixels exceeding the threshold reaches the specified number of pixels. 7. The control method according to claim 6, wherein a full-scale current value of said correction means is determined from these bias current values. 9. The method according to claim 1, wherein the controlling step comprises: setting a bias current value when the number of detected pixels below or above the threshold reaches a specified lower limit set value; and setting a bias current value when the number of detected pixels below or above the threshold becomes a specified upper limit set value. 7. A control method according to claim 6, wherein a bias current value at that time is obtained, and a full-scale current value of said correction means is determined from these bias current values. 10. The control step specifies a full-scale current value of the correction means and counts a count result at a certain bias current and a count result at a current value obtained by subtracting the full-scale current of the correction means from the bias current. 7. The control method according to claim 6, wherein the bias current is determined so that the bias currents are substantially the same.