JP2001244581A - Wiring board and electronic device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure sufficient rigidity and flatness in mounting a semiconductor device. SOLUTION: A wiring board incorporates a signal line layer and a GND layer, an insulating layer for insulating them, and two layers of hard base material for keeping insulation and rigidity of the layers. There are provided a GND layer-signal layer-GND layer of strip line structure where the signal line layer is sandwiched between the GND layers with the insulating layer in between, and the hard base material is so provided as to sandwich the GND layer-signal layer-GND layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting a semiconductor device and a technique effective when applied to an electronic device using the same.

[0002]

2. Description of the Related Art A memory module (RIMM) will be described as an example of a conventional electronic device using a wiring board for mounting a semiconductor device.

FIG. 7 is a diagram for explaining the configuration of a conventional memory module. FIG. 1A is a three-dimensional diagram.
FIG. 1B is a side view seen from the arrow direction.

A conventional memory module 100 is shown in FIG.
As shown in FIG. 7A and FIG. 7B, the semiconductor device 20 is mounted on the wiring board 10 on both sides.

FIG. 8 is a cross-sectional view for explaining the structure of a conventional wiring board 10. As shown in FIG.

As shown in FIG. 8, a conventional wiring board 10 has a semiconductor device mounting surface having a wiring layer and a power supply layer on its surface, a signal line layer 12, a GND layer 13, and an insulating layer for insulating those layers. For example, a TAB tape 16 formed in a microstrip line structure having a polyimide layer 15 is attached to both surfaces of a hard base material (core material) 11 made of glass epoxy resin or the like and maintaining rigidity. Take.

[0007]

As shown in FIG. 8, in a conventional memory module 100, a TAB tape 16 is attached to both surfaces of a hard base material 11, and a semiconductor layer 15 is formed on an insulating layer (for example, a polyimide layer) 15 thereof. A device mounting surface layer is provided, and the semiconductor device 20 is mounted thereon.

The reason for this configuration is that fine wiring processing cannot be performed on the hard base material 11. Therefore, a configuration as shown in FIG. 8 is provided in which a non-fine wiring process such as the GND layer 13 is provided on the hard base material 11.

However, in the configuration shown in FIG. 8, since the insulating layer 15 on which the semiconductor device 20 is mounted does not have sufficient rigidity and flatness, distortion occurs and the reliability of mounting (joining) of the semiconductor device is affected. After the semiconductor device 20 is mounted, there is a problem that the semiconductor device 20 peels off due to its weight or the semiconductor device 20 itself falls off. From this,
Conventionally, it has been difficult to laminate three or more layers on one side of the hard base material 11 in order to maintain flatness.

Since the thermal expansion coefficient of the insulating layer 15 is larger than the thermal expansion coefficient of the semiconductor device, stress is applied when the semiconductor device 20 is mounted on the insulating layer 15, and the insulating layer 15
However, there was a problem that it was warped.

As described above, the conventional multilayer wiring board of the memory module has a problem that sufficient rigidity and flatness for mounting the semiconductor device are not obtained. There is a problem that stress is generated due to a difference in thermal expansion coefficient between the insulating layer and the insulating layer, and the insulating layer is warped.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a technique capable of obtaining sufficient rigidity and flatness in mounting a semiconductor device on a wiring board. It is in.

Another object of the present invention is to provide a technique capable of preventing the insulating layer, and hence the wiring board, from warping.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present invention, typical ones will be briefly described as follows.

(1) A wiring board including a signal line layer and a constant potential layer, an insulating layer for insulating each of these layers, and two layers of a hard base material for maintaining the insulation and rigidity of each of the layers. A constant potential layer having a strip line structure in which the signal line layer is sandwiched between constant potential layers via an insulating layer;
Signal line layer-constant potential layer, and said constant potential layer-signal line layer-
And a hard substrate provided so as to sandwich the constant potential layer.

(2) n (n is a natural number) signal line layers;
2 × for isolating n + 1 constant potential layers and their respective layers
n insulating layers, and 2 layers for maintaining insulation and rigidity of each layer.
A plurality of constant-potential layers-signal lines provided so as to sandwich said n-layer signal line layers for each layer with a constant-potential layer interposed therebetween through an insulating layer. And a hard base material provided so as to sandwich the pattern layers of the constant potential layer, the signal line layer, and the constant potential layer.

(3) a plurality of pattern layers of a constant potential layer, a signal line layer, and a constant potential layer provided so as to sandwich the plurality of signal line layers by a constant potential layer via an insulating layer for each layer; A wiring substrate having therein a hard substrate provided so as to sandwich the constant potential layer, the signal line layer, and the constant potential layer pattern layer, and electrically connected to the signal line layer or the constant potential layer of the wiring substrate. And a semiconductor device provided on the hard base material as described above.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a wiring board for mounting a semiconductor device of the present invention and an electronic device (memory module) using the same will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a view for explaining the configuration of a memory module provided with a wiring board of Embodiment 1; FIG. 1A is a three-dimensional view; FIG. () Is a side view seen from the direction of the arrow.

The memory module 100a according to the first embodiment
Is a wiring board 1 as shown in FIGS.
The semiconductor device 20 (for example, RDRAM or the like) is mounted on both sides (a total of eight semiconductor devices are mounted on each side, four semiconductor devices) on Oa. In addition, the memory module 10 of the first embodiment
0a, as shown in FIG. 1 (b), to make the device pitch and the electrical pitch the same,
The semiconductor device 20 is mounted such that the length of the semiconductor device 20 is shifted by half the length between the front surface and the back surface of Oa.

FIG. 2 is a cross-sectional view for explaining the configuration of the wiring board 10a of the first embodiment.

As shown in FIG. 2, the wiring board 10a according to the first embodiment includes a signal line 12 formed of an insulating layer (polyimide layer) 15
, And sandwiched between the GND layer 13 and the rigid base material 11 (for example, a glass epoxy resin or a BT resin) having an insulating property on which the signal line layer 12 and the power supply layer 14 are formed. 11a, 11b).

Further, as shown in FIG.
Is sandwiched between the GND layers 13 with the insulating layer (polyimide layer) 15 interposed therebetween, which is a strip line structure, in which the hard base material 11a on which the signal line layer 12 and the power supply layer 14 are formed,
Each of the structure of the ground layer 11b and the GND layer 13 is a microstrip line structure.

That is, the wiring board 10a of the first embodiment
Has a stripline structure at the center position and a microstripline structure on its upper and lower surfaces (back surface). This strip line structure is formed by a laminated TAB tape.

As described above, the wiring board 10 of the first embodiment
In a, conventional wiring for fine processing of a semiconductor device mounting surface is
By providing the tape in a TAB tape having a strip line structure, only non-fine wiring such as connection pads of the semiconductor device can be formed on the semiconductor device mounting surface. 11a, 1
1b.

That is, the hard base materials 11a and 11b
With the structure in which the B tape is interposed, it is possible to increase the density of wiring using a TAB tape having a strip line structure. In addition, the high density can reduce the number of wirings provided on the semiconductor device mounting surface, and eliminates the need for providing fine processing wiring on the semiconductor device mounting surface. 11b can be provided. This makes it possible to ensure sufficient rigidity and flatness of the semiconductor mounting.

Next, the above-described strip line structure and microstrip line structure will be described.

FIG. 3 is a diagram for explaining a strip line structure and a micro strip line structure.

The microstrip line structure is shown in FIG.
As shown in (a), the structure is such that a signal line 12 is provided on a GND layer via an insulating layer (here, a hard base material 11) (a structure of a signal line layer-GND layer).

The strip line structure is shown in FIG.
As shown in (b), the structure is such that the signal line 12 is interposed between the GND layers 13 with the insulating layer (polyimide layer) 15 interposed therebetween (the structure of GND layer-signal line layer-GND layer).

At this time, the height of the insulating layer shown in FIGS. 3A and 3B is "h", the signal line width is "W1", and
If “W2”, h is equal: W2 ≒ 1/2 × W
1, the strip line structure can make the signal line width narrower than the microstrip line structure. That is, in the strip line structure, signal lines can be arranged with high density. In the strip line structure, the signal line width W2 can be reduced as the value of h is reduced.

The details of the relationship between the height of the insulating layer of the strip line structure and the microstrip line structure and the signal line width are disclosed in "Printed Circuit Technology Handbook" published by Nikkan Kogyo Shimbun.

In the first embodiment, the case where the strip line or the microstrip line structure is provided using the GND layer has been described. However, instead of the GND layer, a layer (for example, a VDD layer) showing a constant potential is provided. The same effect can be obtained even if it is provided.

Next, the wiring board 10 according to the first embodiment will be described.
The effect of a will be described.

FIG. 4 shows a wiring board 1 according to the first embodiment.
FIG. 9 is a diagram for explaining a comparison between the conventional wiring board 10 and a conventional wiring board 10.

Since the conventional wiring board 10 has a structure in which the TAB tapes M1 and M2 are attached to the center of the hard base material 11, the rigid base material having the rigidity is provided only at the center, so that the semiconductor device 20 is mounted. Although sufficient rigidity and flatness were not obtained, the wiring board 10a of the first embodiment
Since the semiconductor device 20 has a structure in which the semiconductor device 20 is mounted on the hard substrates 11a and 11b by being sandwiched between the two hard substrates 11a and 11b, sufficient rigidity and flatness for mounting the semiconductor device 20 can be obtained. This has the effect of improving the reliability of the connection.

Further, since the thermal expansion coefficients of the hard base materials 11a and 11b (glass epoxy resin) are smaller than the thermal expansion coefficient of the insulating layer 15 (polyimide), the difference in the thermal expansion coefficient with the semiconductor device 20 is small. The stress caused by the difference in the coefficient of thermal expansion can be reduced, and the wiring board can be prevented from warping.

Furthermore, since the conventional wiring board 10 has a structure in which the TAB tapes M1 and M2 having a microstrip line structure are respectively attached to the front and back surfaces of the hard base material 11, the signal lines 12 have two layers. As a result, as described above, the width of each signal line 12 increases.

On the other hand, the wiring board 10 of the first embodiment
a, a TAB tape S having a strip line structure
1 is sandwiched between the hard base materials 11a and 11b, so that the conventional two signal line layers 12 can be integrated into one layer.

As a result, the wiring board 10 of the first embodiment
In the case of a, even if two layers of the thick hard base material 11 are provided, each layer of the signal line layer 12 and the insulating layer 15 can be reduced. It is possible to make it thinner. Since the height of the insulating layer 15 can be reduced by using a TAB tape, a thin and high-density wiring board can be provided by the above-described strip line structure.

(Embodiment 2) In Embodiment 2, a memory module 100b including a wiring board having signal lines 12 of a multilayer strip line structure therein will be described. In the second embodiment, two layers are taken as an example of a multilayer strip line structure.

The memory module 100b according to the second embodiment
Since the external configuration is the same as the configuration of the memory module 100a according to the first embodiment shown in FIG. 1, the description is omitted, and only the wiring board 10b is described.

FIG. 5 is a cross-sectional view for explaining the configuration of the wiring board 10b according to the second embodiment.

As shown in FIG. 5, the wiring board 10b of the second embodiment is provided with three GND layers 13,
It has a two-layer strip line (two-layer GND layer-signal line layer-GND layer pattern layer) structure in which the signal line layer 12 is provided between the ND layers 13 with the insulating layer 15 interposed therebetween. A structure in which the signal line layer 12 and the power supply layer 14 are formed on the hard substrate 11 (11a, 11b) on the (back surface).

That is, the wiring board 10b of the second embodiment
Has a two-layer strip line structure (GND layer-signal line layer-GND layer-signal line layer-GND layer) at the center position and a microstrip line structure on the upper and lower surfaces (back surface). At this time, of the three GND layers 13, the GND layer located at the center is a common GND layer 13 for realizing a two-layer strip line structure.

As in the first embodiment, the two-layer strip line structure is formed thin by a TAB tape laminating technique.

As described above, the wiring board 10 of the second embodiment
In b, the conventional wiring for fine processing of the semiconductor device mounting surface is
By providing the multi-layered strip line structure in the TAB tape, wiring processing on the semiconductor device mounting surface can be performed only for non-fine wiring processing of connection pads and the like of the semiconductor device (or wiring of a detour for wiring to cross). Therefore, it is possible to realize a configuration in which a wiring board having a wiring structure equivalent to that of a conventional wiring board is sandwiched between the hard substrates 11a and 11b.

That is, when the hard base materials 11a and 11b are
By adopting a structure in which the B tape is sandwiched, it is possible to make the wiring multi-layered by the TAB tape lamination technology. Further, the multi-layered structure can reduce the number of wirings provided on the semiconductor device mounting surface, and eliminates the need for providing fine processing wiring on the semiconductor device mounting surface. Can be provided. This makes it possible to secure sufficient rigidity and flatness of the semiconductor mounting.

In the second embodiment, the case where the strip line or the microstrip line structure is provided by using the GND layer has been described. However, instead of the GND layer, a layer (for example, a VDD layer) showing a constant potential is provided. The same effect can be obtained even if it is provided.

Next, the wiring board 10 according to the second embodiment will be described.
The effect of b will be described.

FIG. 6 shows a wiring board 1 according to the second embodiment.
FIG. 5 is a diagram for explaining a comparison between Ob and a conventional wiring board 10.

Since the conventional wiring board 10 has a structure in which the TAB tapes S2 and S3 are attached to the center of the hard base material 11, the hard base material having rigidity is only at the center, so that the semiconductor device on which the semiconductor device 20 is mounted is mounted. Although sufficient rigidity and flatness were not obtained on the mounting surface, the wiring board 10b of the second embodiment was sandwiched between two layers of hard bases 11a and 11b, and a semiconductor was mounted on the hard bases 11a and 11b. Because of the structure for mounting the device 20, sufficient rigidity and flatness for mounting the semiconductor device 20 can be obtained, and there is an effect that the reliability of the connection is improved.

Since the thermal expansion coefficients of the hard bases 11a and 11b are smaller than the thermal expansion coefficient of the insulating layer 15, the difference in thermal expansion coefficient with the semiconductor device 20 is small. And the warpage of the wiring board can be prevented.

Further, in the conventional wiring board 10, a TAB having a strip line structure
Since the TAB tapes S1 and S2 have independent structures and cannot be combined into one, since the tapes S2 and S3 are bonded to each other, the GND layer 13 is used.
Need four layers.

On the other hand, the wiring board 10 of the second embodiment
b, a TAB tape S having a strip line structure
4 are sandwiched between the hard base materials 11a and 11b, respectively, so that the two-layer strip line structure can be integrated into one.

As a result, the wiring board 10 of the second embodiment
b is GND even if two thick hard base materials 11 are provided.
Since each layer of the layer 13 and its insulating layer 15 can be reduced, it is possible to make the thickness equal to or smaller than that of the conventional wiring board 10.

In the second embodiment, the case where the number of the signal line layers 12 is two has been described. However, the present invention is not limited to this, and includes three or more signal line layers 12. The case is equally applicable.

In the case where a plurality of signal line layers 12 are provided, if the number of signal line layers is n (n natural number), the insulating layer 1
The number of 5 is 2 × n layers, the number of GND layers 13 is n + 1 layers, and it is an n-layer pattern layer of GND layer-signal line layer-GND layer.

As described above in Embodiments 1 and 2, the wiring board of the present invention sandwiches one or more signal line layer portions between two hard base materials, and places the signal line layer portions on the hard base materials. Since the semiconductor device has a structure in which the semiconductor device is mounted, sufficient rigidity and flatness for mounting the semiconductor device are obtained, and the reliability in connection is improved.

Further, since one or a plurality of signal line layer portions are sandwiched between two hard base materials, the signal line layer can be easily formed into a strip line structure. Since the wiring board can be arranged at a high density and the number of signal line layers can be reduced, the wiring board and the electronic device using the same can be made smaller (thinner). In particular, when a plurality of signal line layers are provided, the wiring substrate and the electronic device using the same can be made smaller (thinner) by adopting a strip line structure using a common GND layer and reducing the number of GND layers. .

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0062]

The effects obtained by the representative inventions among the inventions disclosed in the present invention will be briefly described.
It is as follows.

Since one or more signal line layer portions are sandwiched between two hard substrates and the semiconductor device is mounted on the hard substrates, sufficient rigidity and flatness for mounting the semiconductor device are obtained. Property is obtained.

Since the thermal expansion coefficient of the hard base material is smaller than the thermal expansion coefficient of the insulating layer, the difference in thermal expansion coefficient with the semiconductor device is small, so that the stress caused by the difference in thermal expansion coefficient can be reduced. The warpage of the wiring board can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration of a memory module including a wiring board according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a wiring board 10a according to the first embodiment.

FIG. 3 is a diagram for explaining a slip line structure and a microstrip line structure.

FIG. 4 is a diagram for comparison between the wiring board 10a according to the first embodiment and the conventional wiring board 10;

FIG. 5 is a cross-sectional view illustrating a configuration of a wiring board 10b according to a second embodiment.

FIG. 6 is a diagram for comparison between a wiring board 10b according to the second embodiment and a conventional wiring board 10;

FIG. 7 is a diagram for explaining a configuration of a conventional memory module.

FIG. 8 is a cross-sectional view illustrating a configuration of a conventional wiring board 10.

[Explanation of symbols]

 10, 10a, 10b Wiring board 11, 11a, 11b Hard base material 12 Signal line layer 13 GND layer 14 Power supply layer 15 Insulating layer 16 TAB tape 20 Semiconductor device 100, 100a Memory module

Continued on the front page (72) Inventor: Tomo Yasuda 3-1-1, Sukekawa-cho, Hitachi-shi, Ibaraki F-term in the electric wire plant of Hitachi Cable, Ltd. (reference) 5E338 AA03 AA16 BB72 BB75 CC02 CC04 CC06 EE01 EE13 EE26 EE33

Claims (3)

[Claims] 1. A wiring board comprising a signal line layer and a constant potential layer, an insulating layer for insulating each of these layers, and two layers of a hard base material for maintaining the insulation and rigidity of each of the layers. A constant potential layer, a signal line layer, and a constant potential layer having a strip line structure provided so as to sandwich the signal line layer with a constant potential layer via an insulating layer; and the constant potential layer, the signal line layer, and the constant potential layer. And a hard substrate provided so as to sandwich the wiring substrate. 2. An n (n is a natural number) signal line layer, and n + 1
A fixed potential layer, a 2 × n insulating layer for insulating each of these layers, and a two-layer hard base material for maintaining the insulation and rigidity of each of the layers, and a wiring board including therein a A plurality of constant-potential layers, a signal line layer, a pattern layer of a constant-potential layer, and a plurality of constant-potential layers provided so as to sandwich the n-layer signal line layers for each layer with a constant-potential layer interposed therebetween. A wiring substrate, comprising: a signal line layer-a hard base material provided so as to sandwich a pattern layer of a constant potential layer. 3. A plurality of constant potential layers provided so that a plurality of signal line layers are sandwiched between the constant potential layers via an insulating layer for each layer.
A wiring substrate having therein a signal layer-a constant potential layer pattern layer, and a hard base material provided so as to sandwich the plurality of constant potential layers-signal line layer-constant potential layer pattern layers; A semiconductor device provided on the hard substrate so as to be electrically connected to a signal line layer or a constant potential layer of the substrate.