JP2001242331A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To provide an optical input / output structure for a signal processing integrated circuit in ultra-high-speed optical communication. SOLUTION: An optical wiring layer is monolithically formed on the front or back surface of a chip of an optical / electrical integrated circuit using a surface type light receiving / light emitting element, and an optical path conversion structure is provided in the layer to provide an optical path conversion structure. This is an optical interface in an electrofusion integrated circuit, and inputs and outputs from and to optical wiring outside the chip such as an optical fiber from the end face of the chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a signal processing integrated circuit optical input / output structure in ultra-high speed optical communication.

[0002]

2. Description of the Related Art At present, under the situation where communication backbone traffic is explosively increasing, various researches for the coming ultra-high-speed and large-capacity communication are in progress. In a signal processing integrated circuit using a current electric interface, 40 Gb / s
Signal processing is said to be the limit. This is limited by the input / output speed of the electric signal of the packaged integrated circuit. As a method for solving this problem, a high-speed signal of 60 Gb / s or more is input / output by light, and a low-speed signal of less than 60 Gb / s is used. It has been studied to perform input and output with electric signals.

An optical-electrical integrated circuit (OEIC) having both optical and electrical interfaces has realized a surface photodiode which can operate at high speed, and operates at 40 Gb / s. Has been confirmed. However, since the light receiving section has a planar structure, the package is as shown in FIG. This is by introducing a collimator lens system (confocal system) from the back of the chip,
This is for inputting light. However, a new connection method is required due to disadvantages of mounting, in which the electrical wiring direction and the optical wiring direction are perpendicular to each other, and an increase in cost due to difficulty in alignment and the like.

[0004]

SUMMARY OF THE INVENTION According to the present invention, as a means for establishing an optical interface of an optical / electrical integrated circuit, an optical interface for performing signal input / output from a surface direction of a semiconductor chip is provided. The purpose is to have a form that is compatible with the electrical interface that performs signal input and output from the end face direction, and a form that enables highly efficient and easy connection to optical wiring outside the chip such as an optical fiber. I do.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: an electric wiring layer for handling a low-speed signal; Characterized in that an optical wiring layer having an optical input / output structure that handles the above is mounted. A semiconductor device according to a second aspect of the present invention that solves the above problem is characterized in that the optical wiring layer according to the first aspect is optically connected to the optical device by an optical path conversion unit. According to a third aspect of the present invention, there is provided a semiconductor device according to the third aspect, wherein the optical path converting means is a flat mirror or a micromirror having a condensing action, which is formed on the waveguide layer. Features. According to a fourth aspect of the present invention, there is provided a semiconductor device, wherein the optical wiring layer according to the first, second or third aspect has a single mode optical waveguide, and the waveguide has a branch. And In a semiconductor device according to a fifth aspect of the present invention for solving the above problems, the optical wiring layer according to the first, second, third or fourth aspect has a single mode high refractive index difference waveguide or a ridge type waveguide. The waveguide has a spot size converter at a connection portion with an external optical wiring.

[0006]

[Embodiment 1] As a first embodiment of the present invention, a conceptual diagram of a chip in which an optical wiring layer is incorporated in an electric wiring layer on a chip surface is shown in FIG. FIG. 1A is an overall external view, and FIGS. 1B to 1D are enlarged views of a lower portion of the surface photodiode. In the present embodiment, an InP-based surface-type photodiode (P
D) is taken as an example of an optical device. Since an electrode is present above the planar photodiode, the optical path is changed so that signal light can be incident from below the planar photodiode.

As shown in FIG. 1, an optical device having an optical wiring layer having an optical input / output structure for handling a high-speed signal and an optical wiring layer having an optical input / output structure for handling a high-speed signal is provided on a substrate 10 on which an optical device or an electronic device is fabricated. -The electrofusion wiring layer 20 is mounted. light·
An optical waveguide 30 having a structure in which a surface-type photodiode 50 is mounted and a core is sandwiched between claddings is formed in the electrofusion wiring layer 20, and one end of the optical waveguide 30 is connected to an external optical fiber 40. . On the other hand, a mirror 60 is formed at the other end of the optical waveguide 30, and the signal light input from the optical fiber 40 is guided to the vicinity of the surface photodiode 50, and the optical path of the mirror 60 is changed by the mirror 60. Reach to the bottom.

Here, utilizing the fact that the semiconductor has a high refractive index, the semiconductor is made incident on the surface photodiode 50 by reflection at the interface between the substrate 10 and air on the back surface of the chip or reflection by a metal film. As shown in FIG. 1B, when heat is required to be released from the integrated circuit by bringing the back surface into contact with the housing, an air space 11 is secured on the back surface of the chip as a light reflecting portion. Also, as shown in FIG.
If the etching 12 using the crystal plane is performed, the incident angle of light can be adjusted. Furthermore, as shown in FIG. 1D, light can be guided by forming a reflective film 13 typified by a metal thin film. In particular, in an optical / electrical integrated circuit, heat generation due to an electronic circuit is conceivable, so the structure shown in FIG. 1B is effective.

FIG. 3 is a conceptual diagram of a chip having an optical branching function equipped with a 3 dB coupler 31 using two high-refractive index difference single-mode optical waveguides 30a and 30b. If the signal from the optical fiber 40 is guided to one single mode optical waveguide 30a, the signal can be branched into two by the 3 dB coupler 31. The single-mode optical waveguides 30a and 30b are designed so that there is no loss due to minute bending that fits in the chip.
The waveguide has a high refractive index difference. In the case of a ridge-type waveguide, a smaller bending structure is possible because a difference in refractive index from air can be used. In the case of such a single mode optical waveguide having a high refractive index difference, the mode field radius (spot size: SS) of the waveguide becomes smaller than that of the optical fiber, but by providing the spot size converter 32 at the connection site. , Connection efficiency and tolerance can be improved.

Although the 3 dB coupler 32 has been described as an element to be formed in the optical wiring layer, a passive element such as a beam splitter or a filter can be mounted, and the function and type thereof are not particularly limited. Optical waveguides 30, 3
As a material of the layers 0a and 30b, since an organic material (polymer) of an insulating film is used for the electric wiring layer, a manufacturing process using the same material is of course possible. The wave layer can be integrated after the IC process is completed. In this case, the waveguide material is not particularly limited to a polymer such as a semiconductor / glass material. Further, as an electrode of the surface type photodiode 50, I
If a transparent electrode such as TO (Indium Tin Oxide) is used, direct input / output from the upper surface of the chip as shown in FIGS. 4A and 4B is possible. FIG. 4A shows a structure in which incident light is reflected by a mirror 60 above a surface photodiode 50, and FIG. The wave is guided up to.

Embodiment 2 As a second embodiment of the present invention, FIG. 5 is a conceptual view of a chip in which an optical wiring layer is formed on the back surface of the chip. As shown in FIG. 5, on the upper surface of the substrate 10, an electric wiring layer 70 for handling a low-speed signal on which a planar photodiode 50, an FET and the like are mounted is mounted, while on the lower surface of the substrate 10, an optical waveguide 30 is provided. An optical wiring layer 80 formed and handling a high-speed signal is mounted. In the present embodiment, unlike the first embodiment, since light can be guided directly from the optical waveguide 30 to the surface photodiode 50, a 45-degree mirror 60 may be used for optical path conversion.

The angle of the mirror 60 is not limited to 45 degrees, and need not be a flat plate. For example,
When the optical distance from the optical waveguide 30 to the planar photodiode 50 is long, light emitted from the optical waveguide 30 may be diffused and light receiving efficiency may be reduced. Therefore, as shown in FIG. 5B, by giving the mirror 60 a curvature, a micro mirror having a light condensing action can be obtained.
As described in the first embodiment, when heat radiation from the back surface is required, if the optical wiring layer 80 is formed on the back surface of the chip using a material having low thermal conductivity such as a polymer, May be an obstacle.

Therefore, as shown in FIG.
It is conceivable that the embedded optical wiring layer 80a composed of the core and the clad portion having a thickness necessary for light propagation is embedded in the substrate 10. FIG. 6A is an overall perspective view, and FIG.
FIG. 6B is a cross-sectional view taken along the line AA ′ in FIG.
Is a view from the back side. As described above, if the buried optical wiring layer 80a is embedded in the substrate 10, even if a material having low thermal conductivity such as a polymer is used as the optical wiring layer 80a on the back surface of the chip, the substrate can be formed of a material having low thermal conductivity. Since the area 10 is not completely surrounded, the problem of heat radiation can be solved. Further, as shown in FIG. 7, when the device section 90 that generates heat and the light receiving section area 100 can be separated from each other, a step 120 for heat dissipation can be formed on the back surface of the chip. Also,
As shown in FIG. 8, a step 120 is formed in the housing 110,
There is a method of increasing the heat radiation efficiency from the substrate 10.

For a plurality of surface photodiodes, it is possible to input light to each surface photodiode 50 as shown in FIG. 9A, or as described in the first embodiment. By providing a passive function such as waveguide branching, it is possible to guide one input light to a different planar photodiode 50 as shown in FIG. 9B.
Even in these cases, it goes without saying that the heat dissipation measures described with reference to FIGS. Also, as shown in FIG.
An optical / electrical fusion connector 140 in which an electric signal line 130 as an electrical interface and an optical fiber 40 as an optical interface are integrated can be connected to the optical / electrical integrated circuit 160 in the package 150, which is simple and convenient.
Inexpensive and space-saving mounting can be achieved.

In the present invention, an optical wiring layer is monolithically formed on the front or back surface of a chip of an optical / electrical integrated circuit using a surface-type light-receiving or light-emitting element, and an optical path conversion structure is provided in this layer. In this way, the optical interface is used as an optical interface in the integrated optical / electrical integrated circuit, and input / output from / to optical wiring outside the chip such as an optical fiber is performed from the chip end face direction. For example, butt-j
oint), and does not require any special optical system outside the chip.

[0016]

As described above in detail with reference to the embodiments, the present invention establishes an optical input / output interface in an optical / electrical integrated circuit by introducing optical wiring on a chip. is there. In particular, it enables simple, inexpensive, and space-saving mounting, and is expected to be 100 Gb / s in the future.
It aims to realize the realization of integrated optical / electrical circuits used in ultra-high-speed and large-capacity communications that exceed the standard.

[Brief description of the drawings]

FIG. 1A is an explanatory view of a chip structure when an optical wiring layer is provided on the surface of an IC chip, and FIG. 1B is a partially enlarged view in which an air space for a mirror is secured; 1) is a partially enlarged view in which a structure for controlling a reflection angle is provided in a mirror air space, and FIG. 1D is a partially enlarged view in which a reflection film is formed as a mirror.

FIG. 2 is an explanatory diagram of a conventional surface-type photodiode package.

FIG. 3 is a perspective view showing a structure in which an optical wiring layer has a passive function (two branches by a coupler).

FIG. 4A is a conceptual diagram illustrating a state in which reflected light from the upper surface is incident on a surface-type photodiode using a transparent electrode, and FIG. FIG. 4 is a conceptual diagram showing a state of incidence on a photodiode.

FIG. 5A is an explanatory diagram of a chip structure in a case where an optical wiring layer is provided on the back surface of an IC chip, and FIG. 5B is a structural diagram in which an optical path conversion mirror has a light collecting function. .

FIG. 6A is a bird's-eye view of a structure in which an embedded optical wiring layer is formed on the back surface of an IC chip, and FIG.
FIG. 6C is a cross-sectional view taken along the line −A ′, and FIG.

FIG. 7 is an explanatory view of an IC chip in a case where a heat-generating portion and a light-receiving portion region can be separated from each other when viewed from an end surface direction.

FIG. 8 is a conceptual diagram in the case where a heat-dissipating step is formed on the housing side.

FIG. 9A is a conceptual diagram of an optical wiring for a plurality of surface photodiodes, and FIG. 9B is an optical wiring in a case of one input for a plurality of surface photodiodes. It is a conceptual diagram.

FIG. 10 is a conceptual diagram of application of an optical / electrical fusion interface.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 11 Space 12 Etching 13 Reflection film 20 Optical / Electric fusion wiring layer 30 Optical waveguide 30a, 30b Single mode optical waveguide 31 3dB coupler 32 Spot size conversion part 40 Optical fiber 50 Surface photodiode (PD) 60 Mirror 70 Electric wiring Layer 80 Optical wiring layer 80a Embedded optical wiring layer 90 Device area 100 Light receiving area 110 Housing 120 Step 130 Electric signal line 140 Optical / electrical fusion connector 150 Package 160 Optical / electrical fusion integrated circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tomoyuki Akeyoshi 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 2H037 AA01 BA11 BA24 CA34 CA37 2H047 KA03 KA04 KA05 KB08 KB09 MA05 MA07 5F088 AA01 AB07 BA02 BA18 BB01 FA04 JA13 JA14 JA20

Claims (5)

[Claims] 1. A semiconductor wherein an electrical wiring layer for handling low-speed signals and an optical wiring layer having an optical input / output structure for handling high-speed signals are mounted on a substrate on which optical devices and electronic devices are fabricated. apparatus. 2. The semiconductor device according to claim 1, wherein the optical wiring layer is optically connected to the optical device by an optical path changing unit. 3. The semiconductor device according to claim 2, wherein said optical path changing means is a flat mirror or a micro mirror having a light-condensing action formed on said waveguide layer. 4. The semiconductor device according to claim 1, wherein the optical wiring layer has a single mode optical waveguide, and the waveguide has a branch. 5. The optical wiring layer has a single mode high refractive index difference waveguide or a ridge type waveguide, and the waveguide has a spot size converter at a connection portion with an external optical wiring. The semiconductor device according to claim 1, 2, 3, or 4, wherein