JP2001136671A - Secondary battery charge control circuit - Google Patents

Abstract

(57) [Problem] To realize a secondary battery charge control circuit capable of freely setting a charging current and a charging time according to a type and a charging state of a secondary battery. A switch circuit (2) connected in series with a secondary battery (3) and whose conduction and open state is controlled by an output signal of a level shift circuit (16), a reference voltage generation circuit (5) including, for example, a three-terminal regulator, and a reference voltage generation circuit (5) A clock signal generating circuit 6 for generating a clock signal for setting the output level of the circuit 5 to high and the ground potential to low level, a duty factor variable terminal 4 for varying the duty factor, and a clock input from the clock signal generating circuit 6 Signal amplitude is A
A level shift circuit 16 for converting the output voltage level of the C / DC converter 1 to an amplitude between the ground potential and the output, and
Reset circuit 17 for fixing the output level of level shift circuit 16 when the output of reference voltage generation circuit 5 is at the ground potential
And

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a secondary battery charge control circuit for controlling the charging of a secondary battery in a battery pack incorporated in a portable device, a personal computer, or the like.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional charge control circuit for a secondary battery. In FIG. 2, the adapter power supply 1b is A
It comprises a C / DC (AC / DC) converter 2b and a charging current control circuit 3b. When charging the secondary battery 4b in the battery pack 5b, the adapter power supply 1
The charging is performed by the charging current control circuit 3b of b.

[0003]

As described above, the secondary battery 4b in the battery pack 5b of a portable device, a personal computer, or the like is charged using the charging current control circuit 3b built in the adapter power supply 1b. When the type, charging current and charging time of the secondary battery 4b change,
Since it is necessary to change the adapter power supply 1b itself, there is a problem that it is difficult to cope with a change in the charging condition.

The present invention solves the above-mentioned conventional problems, and provides a secondary battery charge control circuit that can freely set a charging current and a charging time according to a type and a charging state of the secondary battery. The purpose is to do so.

[0005]

In order to achieve this object, a secondary battery charging control circuit according to the present invention comprises: a switch circuit connected in series with a secondary battery to which a charging voltage is applied; A reference voltage generation circuit that generates a reference voltage as an output voltage when the voltage is equal to or higher than a predetermined voltage, and sets a level of the output voltage to the ground potential when the voltage is lower than the predetermined voltage; A clock signal generation circuit for generating a clock signal having an amplitude between the clock signal generation circuit, duty factor variable means for varying the duty factor of the clock signal generated from the clock signal generation circuit, and a clock signal input from the clock signal generation circuit Is converted into an amplitude between the level of the charging voltage and the ground potential and output. The level of the output signal controls whether the switch circuit is in a conductive state or an open state. A level shift circuit which performs the level of the output voltage of the reference voltage generating circuit and a level shift circuit output fixing means for fixing the output signal of the level shift circuit when the ground potential.

The level shift circuit has a first conductivity type channel having a source connected to the ground potential.
Field effect transistor, third and fourth field effect transistors of a second conductivity type channel whose sources are connected to the level of the external voltage, and an inverting amplifier using the output voltage of the reference voltage generating circuit as a power supply voltage. The output terminal of the inverting amplifier is connected to the gate of the first field effect transistor, the input terminal of the inverting amplifier and the input terminal of the clock signal are connected to the gate of the second field effect transistor, Is connected to the drain of the third field-effect transistor and the gate of the fourth field-effect transistor. The drain of the second field-effect transistor, the gate of the third field-effect transistor, and the fourth
Is connected to the drain of the field-effect transistor of
Alternatively, an output signal can be taken out from the drain of the second field effect transistor, and the level shift circuit output fixing means can be configured to include the fifth and sixth field effect transistors of the first conductivity type channel whose source is connected to the ground potential. A transistor having one end connected to an external voltage level; a gate of the fifth field-effect transistor connected to the output voltage level of the reference voltage generation circuit; The other end of the resistor is connected to the gate of the sixth field-effect transistor, and the drain of the sixth field-effect transistor is connected to the drain of the first or second field-effect transistor.

According to the configuration of the present invention, the duty factor of the clock signal generated by the clock signal generation circuit is changed by the duty factor variable means, thereby turning on and off the switch circuit connected in series with the secondary battery. Since the time ratio of the state can be changed and the average value of the charging current per unit time can be changed, the effect that the charging current and the charging time can be set freely according to the type of the secondary battery and the charging state. Have.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a secondary battery charging control circuit according to an embodiment of the present invention. In the present embodiment,
The adapter power supply 18 only needs to include the AC / DC converter 1 that converts an externally supplied AC voltage into a DC voltage and outputs the DC voltage.
b (see FIG. 2) is unnecessary. The battery pack 19 includes a lithium ion secondary battery 3, a switch circuit 2 connected in series with the lithium ion secondary battery 3, a reference voltage generation circuit 5, a clock signal generation circuit 6, and a duty factor variable terminal 4 (duty factor variable Means), a level shift circuit 16 and a reset circuit 17 (level shift circuit output fixing means).

The reference voltage generating circuit 5 includes, for example, the secondary battery 3
When the voltage of the secondary battery 3 is equal to or higher than a predetermined voltage, a reference voltage is generated as an output voltage. When the voltage is lower than the predetermined voltage, the level of the output voltage becomes the ground potential.

The clock signal generation circuit 6 is a clock signal for setting the output potential of the reference voltage generation circuit 5 to a high level and setting the ground potential to a low level, that is, the reference voltage generation circuit 5
A clock signal having an amplitude between the level of the output voltage and the ground potential is generated. The duty factor variable terminal 4 is for varying the duty factor of the clock signal. For example, the voltage of the secondary battery 3 is detected (exclusive IC
Alternatively, the voltage is sent to the microcomputer, and the duty factor is adjusted by the dividing circuit of the microcomputer. That is, the duty coefficient variable terminal 4 is an input terminal of the microcomputer, and the output of the clock signal generation circuit 6 is a PWM output of the microcomputer.

The level shift circuit 16 converts the amplitude of the clock signal input from the clock signal generation circuit 6 into an amplitude between the level of the charging voltage and the ground potential, and outputs it.
The switch circuit 2 is turned on (conduction state) by the output signal.
・ Off (open state) is controlled.

The reset circuit 17 is connected to the level shift circuit 16 when the output of the reference voltage generation circuit 5 is at the ground potential.
Is a circuit for fixing the output signal (output potential).
That is, the reset circuit 17 is provided to prevent the output of the level shift circuit 16 from becoming unstable when the output of the reference voltage generation circuit 5 is at the ground potential.

FIG. 1 shows a configuration for charging the secondary battery 3. An adapter power supply 18 is connected to an AC power supply (not shown), and a battery pack 19 is mounted on the adapter power supply 18. As a result, the output voltage of the AC / DC converter 1 inside the adapter power supply 18 is applied to both ends of the switch circuit 2 and the secondary battery 3. When the battery pack 19 is used in a portable device or the like, a terminal (not shown) for extracting the voltage between both ends of the secondary battery 3 is connected to the portable device or the like.

The secondary battery charging control circuit according to the present embodiment includes components in the battery pack 19 except for the secondary battery 3. Hereinafter, the internal configurations of the level shift circuit 16 and the reset circuit 17 will be described in detail. The charging voltage described in claims 1 and 2 is AC / DC
An output voltage of the converter 1, wherein the first conductivity type channel according to claim 2 is an N channel (N-ch), the second conductivity type channel is a P channel (P-ch), and a first field effect. The transistor is a high-breakdown-voltage Nch-MOS transistor 10, and the second field-effect transistor is a high-breakdown-voltage Nch-MOS transistor.
-The MOS transistor 11, the third field effect transistor is a high voltage Pch-MOS transistor 12, the fourth field effect transistor is a high voltage Pch-MOS transistor 13, and the fifth field effect transistor is a high voltage Nch-
The MOS transistor 8 and the sixth field effect transistor are a high voltage Nch-MOS transistor 9, the resistor is a high voltage Pch-MOS transistor 7, and the inverting amplifier is a low voltage inverter 14.

The level shift circuit 16 has a high breakdown voltage Nch-
MOS transistors 10 and 11 and high voltage Pch-MO
It comprises S transistors 12 and 13, a low voltage inverter 14 using the output of the reference voltage generation circuit 5 as a power supply, and a high voltage inverter 15. The clock signal of the clock signal generation circuit 6 whose duty factor has been adjusted by the duty factor variable terminal 4 is input to the input terminal 16P of the level shift circuit 16, and the high level and the low level are determined according to the high level and the low level of the clock signal. And outputs the high level of the output signal to AC /
An output voltage level of the DC converter 1 is output, and a low level is output as a ground potential. The switch circuit 2 according to the high and low levels of the output signal of the level shift circuit 16
The conduction state and the release state are controlled.

The reset circuit 17 has a high withstand voltage N whose gate is connected to the output of the reference voltage generating circuit 5 and whose source is grounded.
a channel-MOS transistor 8, a gate of which is grounded, and a drain of the high-voltage Nch-MOS transistor 8 and AC / D
High breakdown voltage Pch-MOS transistor 7 connected between one output of C converter 1 and used as a high resistance element
And a high voltage Nch-M transistor having a gate connected to the drain of the high voltage Nch-MOS transistor 8 and a source grounded.
An OS transistor 9 is provided. And
The drain of the high breakdown voltage Nch-MOS transistor 9 is connected to the drain of the high breakdown voltage Nch-MOS transistor 11 of the level shift circuit 16. Here, high withstand voltage P
Although the ch-MOS transistor 7 is used as a resistor, a diffusion resistor can be used instead of the high-breakdown-voltage Pch-MOS transistor 7.

The operation of the secondary battery charging control circuit configured as described above will be described. It is assumed that the switch circuit 2 is configured by a Pch-MOS transistor. Here, for example, the secondary battery 3 is finally charged to 17.2 V, and the reference voltage generating circuit 3 supplies 5 V when the voltage of the secondary battery 3 is 8 V or more (8 V to 17.2 V). A reference voltage is generated, and when the voltage of the secondary battery 3 is less than 8 V (when it is less than 0 V to less than 8 V), the output is made constant at 0 V (ground potential). And the configuration of FIG.
When the voltage of the secondary battery 3 is 8 V or more, the control of the rapid / pulse charging of the secondary battery 3 is performed. When the voltage of the secondary battery 3 is less than 8 V, another means (not shown) (not shown) is used. Charging is performed by control.

First, for example, the duty factor variable terminal 4
Is adjusted, and a clock signal is generated from the clock signal generation circuit 6 so that the duty factor becomes 50%. The amplitude level of the clock signal generated at this time is such that the low level is the ground potential and the high level is the potential of the reference voltage generating circuit 5 (hereinafter referred to as VCC), and VCC is set to 5V. This clock signal is applied to the input terminal 16P of the level shift circuit 16, and when the clock signal is at the high level VCC, the high voltage Nch-MOS transistor 11 is turned on, the output of the low voltage inverter 14 becomes the ground potential, The breakdown voltage Nch-MOS transistor 10 is turned off. As a result, the high voltage Pch-MOS transistor 12 is turned on, and the high voltage Pch-MOS transistor 13 is turned on.
Is turned off, and the output of the high-voltage inverter 15
/ DC converter 1 potential (hereinafter VA: VA> V
CC). As a result, the switch circuit 2 including the Pch-MOS transistor is opened by the output of the high-voltage inverter 15. Conversely, when the clock signal output from the clock signal generation circuit 6 is at the low level ground potential, the output of the high voltage inverter 15 is at the low level, and as a result, the switch circuit 2 is conductive.

When the potential of the secondary battery 3 becomes extremely low (less than 8 V) due to overdischarge or the like and the output potential of the reference voltage generating circuit 5 drops to the ground potential, the reset circuit 17
, The high breakdown voltage Nch-MOS transistor 8 is turned off,
When the high voltage Nch-MOS transistor 9 is turned on, the output potential of the high voltage inverter 15 is fixed at VA, so that the switch circuit 2 is fixed in an open state without being uncertain. In this case, A
The switch circuit 2 is turned on using the output of the C / DC converter 1 to perform charging. In other cases, the high-voltage Nch-MOS transistor 8 is on and the high-voltage Nch-MOS transistor 9 is off, so that the output potential of the high-voltage inverter 15 is not fixed by the reset circuit 17.

As described above, according to the level state of the clock signal output from the clock signal generation circuit 6, the switching state of the switch circuit 2 is set to 50% for the conduction state and the release state.
The secondary battery 3 is charged by the AC / DC converter 1. By changing the duty factor of the clock signal with the duty factor variable terminal 4 depending on the type of the secondary battery 3 or the state of charge, the average value of the charging current per unit time can be freely changed. As described above, the charging current can be freely set, and therefore, the charging time can be freely set.

In the present embodiment, the output signal of the level shift circuit 16 is taken out from the drain of the high breakdown voltage Nch-MOS transistor 11 via the high voltage inverter 15. Alternatively, it may be taken out directly from the drain 11. In this case, the operation of the switch circuit 2 with respect to the clock signal level (high, low) of the clock signal generation circuit 6 is reversed.

The output signal of the level shift circuit 16 may be taken out directly from the drain of the high-breakdown-voltage Nch-MOS transistor 10 or via a high-voltage inverter.

In the configuration shown in FIG. 1, when the voltage of the secondary battery 3 is less than a predetermined voltage (less than 8 V in the above-described example), the output of the reference voltage generating circuit 5 becomes the ground potential. The level shift circuit 16 and the reset circuit 17 are connected so that the output of the shift circuit 16 is fixed so that the switch circuit 2 is in an open state, but the drain of the high breakdown voltage Nch-MOS transistor 9 of the reset circuit 17 is connected. High withstand voltage Nc of level shift circuit 16
By connecting to the drain of the h-MOS transistor 10, when the output potential of the reference voltage generating circuit 5 drops to the ground potential, the switch circuit 2 can be fixed to the conductive state.

The switch circuit 2 is a Pch-MO
Although an S transistor is used, a PNP transistor can also be used.

[0026]

As described above, according to the present invention, the duty factor of the clock signal generated by the clock signal generation circuit is changed by the duty factor variable means, thereby enabling the switching circuit connected in series with the secondary battery to be changed. Since the time ratio between the conducting state and the open state can be changed and the average value of the charging current per unit time can be changed, the charging current and charging time can be set freely according to the type and charging state of the secondary battery. can do.

[Brief description of the drawings]

FIG. 1 is a diagram showing a secondary battery charging control circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional secondary battery charging control circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 AC / DC converter 2 Switch circuit 3 Secondary battery 4 Duty coefficient variable terminal 5 Reference voltage generation circuit 6 Clock signal generation circuit 7, 12, 13 High voltage Pch-MOS transistor 8, 9, 10, 11 High voltage Nch-MOS Transistor 14 Low voltage inverter 15 High voltage inverter 16 Level shift circuit 16P Input terminal of level shift circuit 16 17 Reset circuit 18 Adapter power supply 19 Battery pack

Claims (2)

[Claims] 1. A switch circuit connected in series with a secondary battery to which a charging voltage is applied, wherein a reference voltage is generated as an output voltage when a voltage of the secondary battery is equal to or higher than a predetermined voltage, and is lower than the predetermined voltage. A reference voltage generation circuit that sets the level of the output voltage to the ground potential; a clock signal generation circuit that generates a clock signal having an amplitude between the output voltage level of the reference voltage generation circuit and the ground potential; Means for varying the duty factor of the clock signal generated from the clock signal generation circuit; and the amplitude of the clock signal input from the clock signal generation circuit to the amplitude between the charging voltage level and the ground potential. And a level shift circuit that controls the conduction state and the open state of the switch circuit based on the level of the output signal. Secondary battery charge control circuit having a level shift circuit output fixing means for fixing the output signal of the level shift circuit when the level of the ground potential of the output voltage of the pressure generating circuit. 2. A level shift circuit comprising: first and second field effect transistors of a first conductivity type channel having a source connected to a ground potential; and a second conductivity type channel having a source connected to a charging voltage level. Third and fourth field-effect transistors, and an inverting amplifier that uses the output voltage of the reference voltage generating circuit as a power supply voltage. An output terminal of the inverting amplifier is connected to a gate of the first field-effect transistor, The input terminal of the inverting amplifier and the input terminal of the clock signal are connected to the gate of the second field-effect transistor, and the drain of the first field-effect transistor, the drain of the third field-effect transistor, and the fourth The gate of the field-effect transistor is connected, and the drain of the second field-effect transistor and the gate of the third field-effect transistor are connected. And the drain of the fourth field-effect transistor is connected to take out an output signal from the drain of the first or second field-effect transistor. The level shift circuit output fixing means includes a source connected to the ground potential. Fifth and sixth field-effect transistors of the first conductivity type channel, and a resistor having one end connected to the level of the charging voltage, and the gate of the fifth field-effect transistor is connected to the reference voltage generating circuit. And the drain of the fifth field-effect transistor is connected to the other end of the resistor and the gate of the sixth field-effect transistor, and the drain of the sixth field-effect transistor is connected to the drain of the sixth field-effect transistor. 2. The secondary battery charge control circuit according to claim 1, wherein the secondary battery charge control circuit is connected to a drain of the first or second field effect transistor.