JP2001128163A - Image decoding device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce the circuit scale. An address generation unit having a simple increment counter is added by utilizing a characteristic that a transfer rate of code data from a transmission line is input at an extremely low rate as compared with an internal processing capability of a code restoration unit or the like. By arbitrating access to the memory in a time-division manner, the processing of the synchronization detection circuit 1, the error correction circuit 5, and the code restoration circuit 6 is realized by the single memory 4, and the syndrome calculation table ROM is used for the error correction circuit 6. Instead, a value for detecting a syndrome error is obtained by a coefficient arithmetic circuit and a serial arithmetic unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding apparatus for decoding data after image transmission.

[0002]

2. Description of the Related Art In recent years, with the progress of digital signal processing technology and the development of communication infrastructure, the field of multimedia communication mainly for image communication is expected to grow. However, when the image data is directly digitized and handled, the amount of information becomes enormous. For effective use of the transmission path, ITU-T Recommendation H. 261, H .; It is necessary to transmit the image data while reducing the amount of information by a compression technique such as H.263.

[0003] A general image decoding apparatus will be described below.

FIG. 8 is a block diagram showing a configuration of a general image decoding apparatus. In FIG. 8, reference numeral 101 denotes a synchronization detection circuit that detects synchronization bits inserted at regular intervals.

[0005] Reference numeral 102 denotes a synchronization detection FIFO that stores data for a predetermined period for synchronization detection by the synchronization detection circuit 101.
O (first in first out) memory.

Reference numeral 103 denotes an error correction circuit for detecting and correcting an error in the code data coming from the transmission line.

An error correction FIFO memory 104 stores one frame of delayed data used in the error correction circuit 103.

Reference numeral 106 denotes a code restoration FIFO memory for storing code data in which a transmission error has been corrected by the error correction circuit 103.

Reference numeral 105 denotes a code restoration FIFO memory 106.
Is a code restoring circuit for restoring the code data stored in the image data into image data.

Reference numeral 107 denotes a switch for switching between a state in which the data received from the transmission path is sent to the synchronization detection circuit 101 and a state in which the data is sent to the error correction circuit 103.

FIG. 9 shows an error correction circuit 103 and an error correction F
FIG. 2 is a block diagram showing a general configuration of an IFO memory 104. In FIG. 9, reference numeral 111 denotes a syndrome register for accumulating code data from a transmission path for performing a syndrome operation and for accumulating a finally calculated syndrome value.

Reference numeral 112 denotes a syndrome calculator for performing a syndrome operation based on the data stored in the syndrome register 111 and the code data from the transmission line.

Reference numeral 113 denotes a syndrome calculation table ROM for converting the value of the syndrome register 111 in which the finally calculated syndrome value is stored into data for error correction.

Reference numeral 114 denotes a FIFO memory for delaying the data on the transmission line by one frame, and the FIFO for error correction shown in FIG.
It is the same as the FO memory 104.

115 is a syndrome calculation table ROM
A syndrome error register for storing the data converted by 113 and detecting a syndrome error by a serial operation. The syndrome error detection means that the remainder is 0 due to a serial operation (division).
Is to detect that there is no error.

Reference numeral 116 denotes a syndrome error register 11
5 is a syndrome error calculator for performing a calculation for a syndrome error. Note that the operation for syndrome error means that when the remainder is other than 0, the sign bit has an error, so that coefficient conversion (multiplication) is performed by serial operation based on the remainder data. .

Reference numeral 117 denotes 1 by the FIFO memory 114.
A correction circuit that performs error correction based on the transmission path data delayed by the frame and the data stored in the syndrome register 115 and outputs code restoration data.

The operation of the above image decoding apparatus will be described below.

In FIG. 8, the first data after connection of the transmission line is first stored in the FIFO memory 102 for synchronization detection via the switch 107 and the synchronization detection circuit 101. The synchronization detection FIFO memory 102 detects a synchronization pattern using data delayed by one frame and data of two or more bits of data received from the transmission line, and detects a synchronization bit position. The procedure for detecting a synchronization pattern in this conventional example is the same as the detection of a synchronization pattern in the embodiment described later. However, in the case of the embodiment described below,
Since it refers to the state after the synchronization has been determined, only one bit needs to be observed (for each frame). In order to reduce the memory, the embodiment does not use a memory.

When a synchronization bit is detected, the switch 107
, The data other than the synchronization bit is sent to the error correction circuit 103, and the error correction FIFO memory 104
Error correction is performed using. Synchronization detection and error correction are calculated in accordance with the transfer rate from the transmission line, and are stored in the code restoration FIFO memory 106 at regular intervals as image code data. The code data of the image is read out in accordance with the processing capability of the code restoration circuit 105, and restoration to image data is performed. Note that the switch 107 is always switched to the error detection circuit 103 after the synchronization is detected, and is switched to the synchronization detection circuit 101 when the synchronization is lost.

The error correction circuit 103 and the error detection F
The operation with the IFO memory 104 is as follows.

First, when data received from the transmission path is input, a serial operation is performed by the syndrome register 111 and the syndrome calculator 112 every time data is input, and a syndrome operation for one frame is performed.

When the syndrome calculation for one frame is completed, the calculation result is converted into a calculation value for performing error detection using the syndrome calculation table ROM 113, and the converted data is used as a syndrome for syndrome error calculation. It is set in the error register 115.

Next, by storing the data received from the transmission line by the FIFO memory 114, the FIFO memory 1
The error correction of the data is performed by the correction circuit 117 using the data delayed by one frame output from 14 and the value of the register 115. In parallel with this error correction operation, F
Serial operation is performed by the syndrome error calculator 116 on the data delayed by one frame by the IFO memory 114 and the data stored in the register 115. The calculation result is output to the syndrome error register 115.
Is stored in The stored value of the syndrome error register 115 is used as an error correction value for the next data, and this operation is repeated for one frame, and one frame of error-corrected code data is output.

[0025]

However, in the configuration of the above-described conventional image decoding apparatus, the synchronization detecting circuit 101,
Each of the error correction circuit 103 and the code restoration circuit 105 requires a buffer memory, specifically, a synchronization detection FIFO memory 102, an error correction FIFO memory 104, and a code restoration FIFO memory 106. Requires a syndrome calculation table ROM 113 as data for calculating a syndrome error. In other words, there is a problem that the use of a plurality of hard macros increases the circuit scale due to restrictions during layout design and an increase in memory capacity.

Accordingly, it is an object of the present invention to provide an image decoding apparatus which realizes the processing of a synchronization detecting section, an error correcting section, and a code restoring section with a single memory and can reduce the circuit scale. is there.

Another object of the present invention is to provide an image decoding apparatus capable of performing an operation for detecting a syndrome error without using a syndrome operation table ROM and reducing the circuit scale. That is.

[0028]

SUMMARY OF THE INVENTION The present invention utilizes a characteristic that a transfer rate of coded data from a transmission line is input at an extremely low rate as compared with an internal processing capability of a code recovery unit or the like, and uses a simple increment counter. By adding an address generation unit with a arbitration and arbitrating access to the memory in a time-sharing manner, the processing of the synchronization detection unit, error correction unit, and code restoration unit can be realized with a single memory. As for the section, data for detecting a syndrome error is obtained using a coefficient operation circuit and a serial operation circuit without using the syndrome operation table ROM.

The image decoding apparatus according to the first aspect of the present invention provides:
A synchronization detection unit for detecting a synchronization pattern inserted at regular intervals for frame synchronization, an error correction unit for detecting and correcting an error in received data, a code restoration unit for restoring code data, One storage means, utilizing the characteristic that the transfer rate of the code data from the transmission path is input at an extremely low rate compared to the internal processing capacity of the synchronization detection unit, the error correction unit and the code recovery unit, In order to process the code data of the error correction unit and the code restoration unit using a single storage unit, an address control unit that increments an address pointer only when writing and reading to the storage unit is provided, and is stored in a time-division manner. Mediating access to the means.

The arbitration of access to the storage means in a time-division manner means that read / write is controlled by providing a specific timing, and until the synchronization is detected, for example, the write, write, An access such as read, read, or read is performed, and thereafter, read or write is performed when there is a request from each of them at a timing at which error correction and code restoration can be performed, for example, at the timing shown in FIG.

According to this configuration, the transfer rate of the coded data from the transmission line is stored at a very low rate compared with the internal processing capability of the synchronization detection unit, the error correction unit, and the code restoration unit. An address control unit that increments the address pointer only when writing to and reading from the means, and arbitrates access to the storage means in a time-division manner, so that the synchronization detection unit, the error correction unit,
The processing of the code restoration unit can be realized, and the circuit scale can be reduced.

Further, the address pointer performs the increment operation only at the time of writing / reading to / from the storage means, so that the address generation can be performed only by all +1 operations, and the number of circuits can be reduced.

According to a second aspect of the present invention, in the image decoding apparatus of the first aspect, the synchronization detecting section is configured such that the storage capacity of the storage means is n bits (n is a positive integer) and is fixed. The number of frames of the synchronization pattern in the cycle is m
In the case of (m is a positive integer), a synchronization bit position detection unit for detecting the position of a synchronization bit using data of (n / m) +1, and a storage unit after the detection of the synchronization position by the synchronization bit position detection unit , And a synchronization bit determination unit that performs protection before and after every n / m.

The claim 2 corresponds to the configuration shown in FIG. 5. In particular, the synchronization bit determination section corresponds to the synchronization check circuit. The position of the synchronization bit is detected, for example, by reading data for each frame number m at the timing shown in FIG. 3 and performing pattern matching together with the input data. Of the preceding and following synchronization protections, the pre-protection is that the synchronization bit is not detected until the synchronization bit is found and determined, and then synchronization is not detected unless a certain number of frames have been confirmed. If an error occurs in a synchronization bit during the synchronization, synchronization is not immediately indicated. If there is a predetermined number of errors in several frames, synchronization is lost.

According to this configuration, since the synchronization protection is performed before and after every n / m by the synchronization bit determination unit without using the storage means, the error correction processing and the code restoration processing are performed by the storage means when the error correction processing and the code restoration processing are performed. The area used for synchronization detection can be used for error correction processing and code restoration processing, and the capacity of the storage means can be reduced as a whole.

According to a third aspect of the present invention, in the image decoding apparatus according to the first aspect, the error correction unit calculates a syndrome from the value of the syndrome calculated by the decoding-side syndrome calculating means. 3 without using the table ROM and using the coefficient calculating means and the serial calculating means.
A coefficient operation including a multiplication operation is performed to obtain a value for detecting a syndrome error.

According to this configuration, in the error correction unit,
Since a value for detecting a syndrome error is obtained by repeatedly performing a serial operation without using the syndrome operation table ROM, the circuit scale can be reduced.

[0038]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an image decoding apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a synchronization detection circuit as a synchronization detection unit that detects synchronization bits inserted at regular intervals in image data.

Reference numeral 4 denotes a memory as a single first storage means for storing the operation result.

Reference numeral 2 denotes a data control circuit for controlling time-division-processed data in order to use a single memory 4. The address of the data control circuit 2 is controlled as shown in FIGS. 3 and 4 which will be described in detail later, so that the data control circuit 2 is used for different roles (registers) every time (time).
Used for error correction and decoding.

Reference numeral 3 denotes an address control circuit as an address control unit for controlling an address by performing an increment operation necessary for each instruction in order to use a single memory 4.

Reference numeral 5 denotes an error correction circuit as an error correction unit for performing error correction after the synchronization is detected by the synchronization detection circuit 1.

Reference numeral 6 denotes a code restoration circuit as a code restoration unit for restoring the error-corrected code data into image data.

FIG. 2 is a block diagram showing a configuration of the address control circuit 3 in the image decoding apparatus according to the embodiment of the present invention. In FIG. 2, reference numeral 10 denotes an address pointer register for error correction read data and code recovery read / write data.

Numeral 11 is an upper address pointer register for synchronous detection read / write data.

Reference numeral 12 denotes a lower address pointer register for error correction write data and a synchronous detection read / write data.

A selector 13 selects a memory access address.

Reference numeral 14 denotes a selector for selecting data on which the increment operation is performed.

Reference numeral 15 denotes an increment operation unit for performing +1 increment.

FIGS. 3 and 4 are timing charts of address values to the memory 4 in the image decoding apparatus according to the embodiment of the present invention. 3 and 4, reference numeral 21 denotes a read signal (RD means read) which becomes active when reading from the memory 4.

Reference numeral 22 denotes a write signal (WT means writing) which becomes active when writing to the memory 4.

Reference numeral 23 denotes an address signal indicating an address value to the memory.

Reference numeral 24 denotes a synchronization determination signal indicating whether or not synchronization has been determined as a result of synchronization detection.

Reference numeral 25 denotes processing contents at the time of memory access performed at each timing.

FIG. 10 is a flowchart corresponding to the timing chart of FIG. 3, and FIG. 11 is a flowchart corresponding to the timing chart of FIG.

In the flowchart of FIG. 10, the current data (address (n-1)) is written. Then, the data (address n) four frames before is read and the register R
1 is stored. Next, the data (address (n + 512)) three frames before is read and stored in the register R2. Then, the data (address (n + 51) two frames before
2 × 2)) is read and stored in the register R3. Then, the data (address (n + 51) one frame before
2 × 3)) is read and stored in the register R4. Then, the new data and the four data in the registers R1 to R4 are used to check the synchronization bit with the total of five data. If not, the operation is repeated from the beginning. Become.

The flowchart of FIG. 11 is based on the write request, write data, read request, read data from the error correction circuit 5, the write request, write data, read request, and read data from the code restoration circuit 6. After the synchronization is determined in the flowchart of FIG. That is, it is determined whether or not there is an error correction write request. If there is a request, data write is performed, and the process proceeds to the next process. If there is no request, the process proceeds to the next process.

Next, it is determined whether or not there is an error correction read request. If there is a request, data read is performed, and the process proceeds to the next step. If there is no request, the process proceeds to the next process.

Next, the presence or absence of a code restoration write request is determined. If there is a request, data writing is performed, and the process proceeds to the next processing. If there is no request, the process proceeds to the next process.

Next, the presence / absence of a code restoration read request is determined. If there is a request, data read is performed, and the process proceeds to the next processing. If there is no request, the process proceeds to the next process.

Next, a synchronization bit check is performed. If the synchronization is still determined, the process returns to the beginning of FIG. If it is a synchronization error, the number of errors is counted. If the number n is 3 or less, the process returns to the beginning of FIG. If the number n exceeds 3, it is regarded as out of synchronization, and the process returns to the beginning of FIG.

FIG. 5 is a block diagram showing a configuration of the synchronization detecting circuit 1 in the image decoding apparatus according to the embodiment of the present invention. In FIG. 5, reference numeral 30 denotes a memory write data register for converting code data received from the transmission path into parallel data in accordance with the bit width of the memory 4 (8 bits in this example) and storing write data to the memory 4.

Numerals 31A, 31B, 31C and 31D are memory read data registers for storing data read from the memory 4 and delayed by k frames. Corresponding to the registers R1 to R4.

Reference numeral 32 denotes a synchronization check circuit for detecting synchronization based on data before k frames and data received from the transmission line.

Reference numeral 33 denotes a frame counter which counts one frame after the synchronization bit is detected by the synchronization check circuit 32 and counts synchronization determination and synchronization loss.

FIG. 6 is a block diagram showing the configuration of the error correction circuit 5 of the image decoding apparatus according to the embodiment of the present invention. In FIG. 6, reference numeral 41 denotes a syndrome register for accumulating code data from the transmission line for performing a syndrome operation and for accumulating a finally calculated syndrome value.

Reference numeral 42 denotes a syndrome calculator for performing a syndrome operation based on the data stored in the syndrome register 41 and the code data from the transmission line.

Reference numeral 43 denotes a coefficient operation circuit for coefficient operation for converting the value of the syndrome register 41 in which the finally calculated syndrome value is stored into data for error correction.

Reference numeral 44 denotes a serial operation unit for calculating a cube operation value by serial operation using the exclusive OR calculated by the coefficient operation circuit 43.

Reference numeral 45 denotes a syndrome error register for storing data calculated by the coefficient calculation circuit 43 and detecting a syndrome error by serial calculation.
Note that the syndrome error detection is to detect that there is no error when the remainder becomes 0 by serial operation (division).

Reference numeral 46 denotes a syndrome error calculator which performs a syndrome error operation using the syndrome error register 45. The calculation for the syndrome error means that when the remainder is other than 0,
Since there is an error in the sign bit, coefficient conversion (multiplication) is performed by serial operation based on the remaining data.

Reference numeral 47 denotes a correction circuit for performing error correction based on the transmission line data delayed by one frame by the memory 4 and the data of the register 45.

FIG. 7 is a timing chart showing the operation of the error correction circuit 5. In FIG. 7, reference numeral 61 denotes a syndrome calculation end signal for inputting one frame of code data received from the transmission path and notifying that the calculation has been completed.

Reference numeral 62 denotes a serial operation period signal indicating a period during which the serial operation of the cubic coefficient is performed by the syndrome register 41 of FIG.

Reference numeral 63 denotes an error correction start signal for setting data in the syndrome error (for both correction) register 45 after the completion of the serial coefficient calculation and for starting a correction operation.

Reference numeral 64 denotes the content of a conversion operation for syndrome error correction which is performed for each cycle.

The operation of the image decoding apparatus according to the present embodiment configured as described above will be described below.

Code data received from the transmission path is H.264. 26
In the case of encoded data that is an encoding method specified by 1 or the like, transmission data is divided into fixed lengths in order to reduce the influence of code errors. This is called a frame.
One frame is composed of 512 bits and includes a 1-bit frame synchronization signal and 511 bits of code data with error correction bits. The error correction method uses BCH, which is a type of error correction code that adds 18 parity bits, which are redundant bits. The frame synchronization signal is 8
This shows a multi-frame structure composed of frames, in which a frame synchronization pattern is repeated.

FIG. 12 shows a frame pattern in the multi-frame structure. Each frame has 1-bit frame synchronization bit Si (i = 1 to 8), 1-bit fill identifier Fi, and 492-bit image data, all of which are “1”.
And an 18-bit error correction code (parity). The frame sync pattern is
(S1 to S8) = (00011011) are repeated. When the fill identifier is “0”, the subsequent 492
The bits are all "1", indicating that no image data is transmitted. The error correction code is calculated for 493 bits of data including the fill identifier.

Here, a description will be given of a point that a memory capable of storing data for only four frames can detect a frame synchronization signal having a multi-frame structure composed of eight frames. In other words, the position of the synchronization pattern is estimated by 5 bits of 4 frames + new 1 bit, and the data of 512 bits after that is checked at the 6th bit and every 512 bits until the data deviates from the synchronization pattern. As pre-protection, synchronization is determined when this operation is confirmed several times (multi-frame) consecutively.

First, in the image coding apparatus shown in FIG. 1, since the synchronization bit position is detected by the code data received from the transmission line, if the size of the memory 4 is 256 × 8 bits, the data of a maximum of 4 frames is used. Is stored in the memory 4. In this case, the data control circuit 2 performs 8-bit packing of the serial data by the memory write data register 30 and writes the data into the memory 4.

Then, the data is read from the memory 4 and transferred to the synchronization detecting circuit 1 for four consecutive cycles from the next cycle in which the data is written.

In the synchronization detecting circuit 1 shown in FIG. 5, four cycles of read data are set in the memory read data registers 31A to 31D, respectively, and the synchronization check circuit 32 uses 5-bit data together with data received from the transmission line.
Detects a frame synchronization pattern having a multi-frame structure, and estimates a synchronization bit position in one frame. Even while this check is repeated, the serial data is packed into 8-bit data by the memory write data register 30 with the data received from the transmission path and written into the memory 4 via the data control circuit 4. Therefore, 8
Each time a bit is input, it is written into the memory 4 once and read out four times.

Here, a method of detecting the frame synchronization pattern will be described. Since the frame synchronization pattern is “00011011”, “00011”,
“00110”, “01101”, “11011”,
“10110”, “01100”, “11000”,
Check if it is "10001", and in that case,
The data after 512 bits is checked.

In this circuit, one or more frame synchronization patterns are detected while receiving one frame of received data. That is, since the synchronization pattern exists at least once during one frame, the frame synchronization pattern is detected at least once. Therefore, since a normal image code pattern may be erroneously recognized as a frame synchronization pattern, after detecting a synchronization bit position, the frame counter 33 counts 512 bits and checks the frame synchronization pattern again. As described above, when the check is repeated and the multi-frame structure is found three times, the synchronization determination signal is activated.

After outputting the synchronization determination signal, the memory 4 is not used because the synchronization check circuit 32 checks for loss of synchronization only with the data received from the transmission line. That is, 51
Synchronization bits are inserted at two-bit intervals, and the expected value (“0” or “1”) of the next synchronization pattern is compared with the input data. Here, synchronization protection means that the line is not error-free,
This means that even if one bit is deviated, it is assumed that synchronization is immediately deviated, so that a search for a synchronization bit is not started. The purpose is to reduce the frequency with which it takes time to detect the synchronization bit and discard valid data.

That is, out-of-synchronization is checked. As a result, in the case of out-of-synchronization, the external or control sequence is used as a sequence for detecting a synchronization pattern.

Here, the operation of the synchronization check circuit is shown in FIG.
This will be described with reference to the flowchart of FIG.

First, synchronization bit detection is performed by checking with 5-bit data, and if detection is not possible, the process returns to the first check with 5-bit data. If the synchronization bit can be detected, it is checked whether or not the data after 512 bits matches the synchronization pattern. If not, the process returns to the first 5-bit data check with n = 0. If they match, n = n + 1, that is, the value of n is increased by one.
Then, it is determined whether or not the value of n is larger than the number determined as the pre-protection. If the value is not larger, the process returns to the check as to whether the data after 512 bits further matches the synchronization pattern. If it is larger, the synchronization is determined.

Next, n is initialized to 0 and further 512
A check is made to see if the data after the bit matches the synchronization pattern to detect out-of-synchronism, and if so, the value of n is cleared at regular intervals, and the data after 512 bits matches the synchronization pattern. Return to check for match. If they do not match, n = n + 1, that is, the value of n is increased by one. Then, it is determined whether or not the value of n is larger than the number determined as the post-protection. If not, the process returns to the check as to whether the data after 512 bits further matches the synchronization pattern. If it is larger, it is determined that the synchronization has been lost, and the process returns to the first 5-bit data check.

When an error of 2 bits or more is found in one multi-frame structure data, the synchronization determination signal is made negative and the synchronization bit position is detected.

Note that the data of one multi-frame structure is a set of “000” consisting of 8 bits shown above.
11011 "(interval of 512 bits). It is assumed that there is an error in the line, so that synchronization cannot be lost immediately. Whether to change 2 bits to 3 bits depends on the system design. An error of 2 bits or more in the data of one multi-frame structure is checked in the same manner as the out-of-synchronization, is counted by a counter when an error occurs, and is reset at regular intervals.

In FIG. 2, the operation of the address control circuit 3 at the time of performing the synchronization detection is as follows. That is, the upper address pointer register 11 has 2 bits, the lower address pointer 12 has 9 bits,
The selector 13 keeps selecting the registers 11 and 12 and is used as an address of the memory 4 when performing synchronization detection.

When data is written to the memory 4, the selector 14 selects the register 12 and the increment operation unit 1
The value of the register 12 is incremented by one by 5 and data is set in the register 12. Next, when data is read from the memory 4, the selector 14 sets the register 1
1 is selected, incremented by 1 by the increment calculator 15, and data is set in the register 11. Hereinafter, this operation is repeated twice.

FIG. 3 shows the read and write operations of the memory at this time. In FIG. 3, data is written to the address n-1 by the write signal 22, and in the next cycle, the lower bits of the address signal are incremented, and the 11 bits indicate the address value of n. The data contained in this address is the oldest data remaining in the memory 4 and is the data four frames before. The data indicated by the address value is read by the read signal 21.

At this timing, the value of the register 11 is incremented by one, and the address value is 11 bits and n +
512 indicates the address value. The data contained in this address is data three frames before. The data indicated by the address value is read by the read signal 21.

This operation is repeated to read data two frames before and one frame before. At this time, the address value indicates n + 2048, that is, the address value of n, and then indicates the address value at which the data received from the transmission line is written.

Since the transfer rate of the transmission line is usually low-bit code data, it is input at a rate considerably lower than the internal operating frequency. Usually there is a rate difference of 20 times or more. In the embodiment, since one process is completed in five cycles for one write, under the condition that the internal process is performed by five times or more operation, it is possible to serially check synchronization detection bit by bit. .

The synchronization is thus determined, and the synchronization determination signal 24
Becomes active, the memory 4 and the address control circuit 3 start operating for error correction and code data restoration. In this case, the error correction is performed by the correction circuit 5 using the data delayed by one frame by the memory 4 and the data received from the transmission path, and the data is written into the memory 4 again. Also, data is read from the memory 4 for code data restoration to the code restoration circuit 6 at a timing necessary for restoration processing, and is restored to image data.

As described above, for error correction, the transfer rate from the transmission line is slower than the internal frequency, and the code data recovery device performs serial processing because the code data itself is a variable-length code. In the case where is a bandwidth of 8 bits, a characteristic is utilized that if the data can be read at least once every 8 cycles, the performance of the restoration processing is not reduced.

In this case, as shown in the processing content 25 in FIG. 4, the timing (WT, RD) at which the error correction data can be written and read and the timing (WT, RD) at which the code data restoring data can be written and read.
The read / write to the memory 4 is performed with four possible timings (RD). The memory 4 uses 512 bits out of the 2048 bits for error correction, and uses the rest as code data restoring memory. in this case,
Timing for writing and reading error correction data (WT, RD) and timing for writing and reading code data restoration data (WT, R
The four possible timings of D) can be provided for the following reasons. In order to process data serially, if data is packed with 4 bits or more, access is made only at a timing of 4 cycles or more. This utilizes the fact that the code amount is originally about 128 kbps and operates internally at several tens of MHz, so that it is not necessary to process the code data in one cycle per bit.

In FIG. 4, the processing contents 25 and RD
The relationship between (21) and the active period of the WT (22) is as follows. That is, a request signal is output when data is required by the error correction circuit 5 and the code restoration circuit 6, and only when there is a request at each timing, the read signal and the write signal become active.

In FIG. 4, address AD (2
3) The way of incrementing A, B, C, and D is not the same only when there is a read or write access.
This is because the address is incremented, and the request from each block is not the same.

In FIG. 2, the operation of the address control circuit when performing this error correction and code data restoration is as follows. Address pointer register 10 for error correction read data and code recovery read / write data
Is composed of two 11-bit registers and a 9-bit register, and indicates an address to the memory 4 together with the address pointer register 12 for error correction write data.

At the time of error correction and code data restoration, the memory 4
Works as a FIFO memory (reads the first written data and writes after the last written data), so error correction,
When a read or write operation is performed for restoring the code data, each address pointer is incremented by one. Therefore, the selector 13 and the selector 14 select the same address pointer register 10 or 12, and the increment operation unit 15 performs one increment. At this timing, when a read or write operation is performed for error correction and code data restoration, data is set in the registers 10 and 12 to prepare for the next address calculation process.

Note that the operation of the address control circuit 3 at the time of error correction and code data restoration and the operation of the address control circuit 3 at the time of synchronization detection are switched by a synchronization determination signal.

Next, the operation of the error correction circuit 5 shown in FIG. 6 will be described. In the BCH error correction code, two random errors can be corrected in one frame, and the 18-bit error correction code is (X ⁹ + X ⁴ +1), (X ⁹ + X
⁶ + X ⁴ + X ³ + X ¹ +1). The former of this arithmetic expression is S1, the latter is S3, and based on this arithmetic expression, a serial operation is performed on the received data (511 bits excluding the synchronization bit) from the transmission line by the syndrome register 41 and the syndrome arithmetic unit 42, Find the value of the syndrome.

Next, syndrome error detection data A1 = (S1 squared) and A2 = (S1 cubed × S3)
Need to ask. Conventionally, syndrome error detection data A1 = (2 of S1 = 2 × 18 bits) or two ROMs of 2 × 9 × 9 bits.
Power) and A2 = (S1 cubed × S3).

The above calculation is performed without carry, so
In the case of the operation of two numbers, it can be constituted by a very simple circuit.
Therefore, if the squaring operation of S1 can be easily performed, the value to be obtained can be configured by one exclusive OR (EXOR) for one bit.

A circuit for easily performing the cube operation of S1 is obtained by dividing S1 ³ into multiplication of S1 ² × S1, and
^This circuit realizes ² × S1 by 9-bit serial multiplication.

Therefore, as described above, for error correction, the transfer rate operates from the transmission line at a lower rate than the internal frequency. Therefore, as shown in the timing chart of FIG.
The power of S1 is raised to the third power by serial operation in nine cycles of the period 2, and (3 of S1
Multiplication) and S3 to perform the syndrome error register 4
A1 and A2 are set to 5. The register 45 and the syndrome error calculator 46 serially calculate the error location, correct the error of the data received from the transmission line delayed by one frame by the correction circuit 47, and write it to the memory 4 as 493-bit code restoration data. . The calculation of the square of S1 is performed in the cycle of the first coefficient calculation.

Thus, the characteristic that the transfer rate of the code data from the transmission line is input at an extremely low rate as compared with the internal processing capability of the synchronization detection circuit 1, the error correction circuit 5, the code restoration circuit 6, etc. is used. An address control circuit 3 having a simple increment counter (increment arithmetic unit 15) is added, and access to the memory 4 is arbitrated in a time-division manner, so that the synchronization detection circuit 1, the error correction circuit 5, the code The processing of the restoration circuit 6 can be realized.

The error correction circuit 5 is composed of nine serial operation registers and four counter registers for measuring timing by repeatedly performing serial operation without using the syndrome operation table ROM 113 to obtain an error correction syndrome value. And 20 for coefficient calculation
It can be realized by a single NAND or EXOR, and the circuit scale can be greatly reduced.

FIG. 14 is a circuit diagram for performing the above operation. In FIG. 14, reference numeral 100 denotes a shift register for serial operation, which is composed of nine D flip-flops 101 to 109. Reference numeral 200 denotes a circuit for performing a cubic operation, including nine NAND circuits 201 to 209 and nine exclusive OR circuits 211 to 21.
It is composed of 9, 9 D flip-flops 221 to 222.

[0116] coefficient computing expressions, S1, S3 is when a value determined by the syndrome calculation, calculation by dividing the ^{A = S1 3 × S3 B =} S1 2 to ^{A = S1 2 × S1 × S3} B = S1 2 Is carried out.

[0117] In this case, computing the S1 ² at the beginning of the coefficient operation cycle of FIG 7. Specifically, the following exclusive OR operation is performed. The symbol ＾ means exclusive OR.

B [8] = S1 [4] B [7] = S1 [8] ＾ S1 [6] B [6] = S1 [8] ＾ S1 [3] B [5] = S1 [7] ＾ S1 [5] B [4] = S1 [7] ＾ S1 [2] B [3] = S1 [6] B [2] = S1 [8] ＾ S1 [1] B [1] = S1 [5] B [0] = S1 [7] ＾ S1 [0] Next, in the cycle of the serial cube calculation, the circuit of FIG. 14 performs the calculation of B × S1. In this case, a cubic operation is performed by serial operation while shifting. The result is stored in register C.

In the last cycle of the coefficient calculation in FIG.
× to complete the calculation of S1 ^3. Specifically, it is an exclusive OR operation shown below.

A [8] = C [8] ＾ B [8] A [7] = C [7] ＾ B [7] A [6] = C [6] ＾ B [6] ... A [ 1] = C [1] ＾ B [1] A [0] = C [0] ＾ B [0]

[0121]

As described above, according to the image decoding apparatus of the first aspect of the present invention, the transfer rate of the coded data from the transmission path is extremely low as compared with the internal processing capacity of the code restoration unit and the like. By utilizing an input characteristic, an address control circuit for incrementing an address pointer only at the time of writing to and reading from the first storage means is added, and arbitration of access to the storage means in a time sharing manner makes it possible to provide a single storage means. Thus, it is possible to realize an image decoding process, prevent a restriction in layout design by using a plurality of hard macros, and prevent an increase in circuit scale due to an increase in the capacity of storage means, and provide an image decoding apparatus with a small circuit scale.

According to the image decoding apparatus of the second aspect of the present invention, since the synchronization protection is performed before and after every n / m by the synchronization bit determination unit without using the storage means, error correction processing and coding can be performed. When performing the restoration process, the area used for synchronization detection in the storage means can be used for error correction processing and code restoration processing,
The capacity of the storage means can be reduced as a whole.

According to the image decoding apparatus of the third aspect of the present invention, the error correction unit obtains a value for detecting a syndrome error by repeatedly performing a serial operation without using the syndrome operation table ROM.
The circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image decoding device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an address control circuit in the image decoding device according to the embodiment of the present invention.

FIG. 3 is a timing chart showing an operation of the image decoding device of FIG. 1;

FIG. 4 is a timing chart showing an operation of the image decoding device of FIG. 1;

FIG. 5 is a block diagram illustrating a configuration of a synchronization detection circuit in the image decoding device according to the embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of an error correction circuit in the image decoding device according to the embodiment of the present invention.

FIG. 7 is a timing chart showing an operation of the error correction circuit of FIG. 5;

FIG. 8 is a block diagram illustrating an example of a configuration of a conventional image decoding device.

FIG. 9 is a block diagram illustrating an example of an error correction circuit of a conventional image decoding device.

FIG. 10 is a flowchart corresponding to FIG. 3;

FIG. 11 is a flowchart corresponding to FIG. 4;

FIG. 12 is a schematic diagram showing frame data having a multi-frame structure.

FIG. 13 is a flowchart illustrating a procedure for detecting synchronization and detecting loss of synchronization.

FIG. 14 is a circuit diagram illustrating a configuration of an arithmetic circuit used in an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization detection circuit 2 Data control circuit 3 Address control circuit 4 Memory 5 Error correction circuit 6 Code restoration circuit 10 Address pointer register 11 Address pointer register 12 Address pointer register 13 Selector 14 Selector 15 Increment calculator 21 Memory read signal 22 Memory write signal 23 Memory Address Signal 24 Synchronization Determination Signal 25 Processing Contents at Memory Access 30 Memory Write Data Register 31A Memory Read Data Register 31B Memory Read Data Register 31C Memory Read Data Register 31D Memory Read Data Register 32 Synchronization Check Circuit 33 Frame counter 41 Syndrome arithmetic unit 42 Syndrome register 43 Coefficient arithmetic circuit 44 Serial arithmetic unit 45 Syndrome Error register 46 syndrome error calculator 47 correction circuit 61 syndrome calculation end signal 62 serial calculation period signal 63 error correction start signal 64 syndrome error correction conversion calculation processing contents 101 synchronization detection circuit 102 synchronization detection FIFO memory 103 error correction circuit 104 error Correction FIFO memory 105 Code recovery circuit 106 Code recovery FIFO memory 111 Syndrome register 112 Syndrome arithmetic unit 113 Syndrome arithmetic table ROM 114 FIFO memory 115 Syndrome error register 116 Syndrome error arithmetic unit 117 Correction circuit

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H04N 1/41 H04N 7/13 Z AF term (Reference) 5C059 KK08 KK09 KK34 MA00 RC02 RF05 UA05 UA34 UA36 5C078 CA25 CA34 CA45 DA01 DA02 5J065 AB03 AC03 AF03 AF04 AG02 AH07 AH17 AH18 5K014 AA01 AA05 BA05 EA01 EA07 5K047 AA16 CC02 DD02 HH01 HH12 HH42 MM14

Claims (3)

[Claims] 1. An image decoding apparatus for decoding an image signal, comprising: a synchronization detecting section for detecting a synchronization pattern inserted at a constant interval for frame synchronization; An error correction unit for detecting and correcting, a code restoration unit for restoring code data, a single storage unit, and a transfer rate of code data from a transmission line, wherein the synchronization detection unit, the error correction unit, and the code restoration Utilizing the characteristics that are input at a very low rate compared to the internal processing capacity of the
An address control in which an address pointer is incremented only at the time of writing / reading to / from the storage means in order to process the code data of the synchronization detection section, the error correction section and the code restoration section using the single storage means. And an arbitration unit for arbitrating access to the storage means in a time-sharing manner. 2. The image decoding apparatus according to claim 1, wherein the synchronization detection unit has a storage unit having a storage capacity of n bits (n bits).
A synchronous bit position detecting unit that detects the position of the synchronous bit using (n / m) +1 data when the number of frames of the synchronous pattern in a fixed period is m (m is a positive integer); An image decoding apparatus, comprising: a synchronization bit determination unit that performs synchronization protection before and after every n / m without using storage means after detecting the synchronization position by the synchronization bit position detection unit. 3. The image decoding apparatus according to claim 1, wherein the error correction unit calculates the coefficient calculation means and the serial calculation means from the syndrome value calculated by the decoding-side syndrome calculation means without using the syndrome calculation table ROM. An image decoding apparatus characterized in that a coefficient calculation including a cube operation is performed using the above and a value for detecting a syndrome error is obtained.