JP2001119295A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit which faithfully makes a PLL response to jitter included in an input clock by using a phase frequency comparator manufactured at a low production cost. SOLUTION: The PLL circuit is provided with a voltage controlled oscillator(VCO) 11, a phase comparison part 15, a loop filter 10, and a counter 12 used as a frequency divider. The phase comparison part 15 is the phase frequency comparator. The phase comparison part 15 is provided with a phase (frequency) comparator 5 which compares the phase difference between an input clock S1 and a frequency divided clock S2 and a phase (frequency) comparator 7 which compares the phase difference between the input clock S1 and a frequency divided clock S3 which has been delayed in a delay circuit 4 by a prescribed time. The delay circuit 4 shifts phases of dead zones in the vicinities of phase centers of two phase comparators 5 and 7. An output S4 of the phase comparator 5 and an output S5 of the phase comparator 7 are synthesized by a synthesizing circuit 9 to supply a phase comparison signal S8 having no dead zones to the VCO 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (hereinafter, referred to as a PLL) using a digital circuit, and more particularly, to a phase locked loop capable of faithfully responding to jitter contained in an input clock.

[0002]

2. Description of the Related Art In broadcasting station equipment, a digital video signal is converted into a serial signal, and the equipment is connected by one coaxial line. To obtain the serial signal, a parallel-serial conversion circuit is used. Have been done. For example, this parallel-serial conversion has a clock cycle of 14.3 MHz.
A serial signal with a clock cycle of 143 Mbps is generated from a 10-bit parallel signal obtained by sampling at z. In this case, a phase-locked output clock having a period of 143 MHz, which is ten times the clock period of 14.3 MHz, is required. Therefore, a PLL circuit using a digital circuit is generally used. In the case of HDTV (high resolution television), it is necessary to generate an output clock having a clock cycle of 1.485 GHz which is 20 times the clock cycle of 74.25 MHz. The jitter of the serial digital video signal needs to be 20% or less of the clock cycle. Further, it is inconvenient if the jitter of the parallel input clock signal directly becomes the jitter of the output serial clock signal, and it is desired that high frequency component jitter be attenuated by the loop filter of the PLL circuit.

A conventional PLL circuit of this type includes a phase-frequency comparator (phase-frequency comparator) operating in a wide frequency range for comparing the phase of a reference (input) clock with a voltage-controlled oscillator (hereinafter, VCO). Phase-Fre
frequency Comparator (PFC). The phase frequency comparator is not only a phase comparison,
Since the frequency error can be determined, the phase comparison can be performed up to the frequency pull-in range of the VCO. However, a general bidirectional shift register or an ECL-structured J
A phase frequency comparator using a -K flip-flop or the like has a dead zone (discontinuity) near the phase center, and thus has a disadvantage that large jitter occurs in the output clock near the phase center. If the phase frequency comparator has a discontinuity near the phase center as shown in FIG. 8D described later, within that range, the loop gain of the PLL circuit becomes the same as zero, and the output clock The cycle of the signal is undefined. This indeterminate state of the output clock signal increases the jitter of the output clock signal. Therefore, in order to faithfully respond to a PLL (phase synchronization) included in the input clock signal, the phase frequency comparator generates a phase comparison signal that changes almost linearly with a change in the phase difference between the two input signals. There is a need to.

Here, a PLL using a phase frequency comparator is used.
One of the circuits is disclosed in Japanese Patent Application Laid-Open No. H11-127076. Hereinafter, the disclosed PLL circuit (phase lock loop circuit) will be described with reference to the block diagram of FIG.
This will be described with reference to the characteristic diagram of the phase frequency comparator used in the PLL circuit of FIG.

In FIG. 7, a phase / frequency comparison circuit 5
0 is the first phase / frequency comparator 50a having substantially no dead zone Dz in the phase / frequency difference detection characteristic (see FIG. 8E) and the second phase / frequency difference detection characteristic is having the dead zone Dz.
And a phase / frequency comparator 50b (see FIG. 8D). The phase of a reference signal (reference clock) S1 from the input terminal 1 and a generated signal S2 obtained by dividing the output signal S10a of the VCO 11 by N by a divider (divider) 12B.
When the frequency difference is large, the first and second phase / frequency comparators 50a and 50b both detect the phase / frequency difference, but the phase / frequency difference cannot be detected by the second phase / frequency comparator 50b. When the difference is very small, only the first phase / frequency comparator 50a detects the phase / frequency difference. Therefore, the first and second phase / frequency comparators 5
Charge pump circuit section 5 for synthesizing outputs of 0a and 50b
1 to low-pass filter (LPF: low-pass filter) 1
0 is equal to the reference signal S1 and the generated signal S2.
Is large when the phase / frequency difference is large, and small when the phase / frequency difference is small (see FIG. 8 (f)). That is, the phase / frequency comparators 50a and 50b and the charge pump circuit section 51 increase the loop gain when the phase / frequency difference between the reference signal S1 and the generated signal S2 is large, and increase the PLL.
The time until the circuit is locked can be reduced.
The current S9 from the LPF 10 is equal to VC
O11 is phase-synchronized controlled.

[0006]

SUMMARY OF THE INVENTION The disclosed PLL circuit uses the first phase / frequency comparator having substantially no dead zone Dz to reduce the jitter of the output clock near the phase center of the phase / frequency comparator. Can be reduced, but two types of phase / frequency comparison of a first phase / frequency comparator having substantially no dead zone Dz and a second phase / frequency comparator having a dead zone Dz as phase / frequency comparators This requires not only a complicated structure, but also a high production cost due to a high unit purchase price of the equipment.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned drawbacks and to provide a phase-locked loop (PLL) capable of faithfully responding to jitter contained in an input clock using a phase frequency comparator having a simple structure and a low unit price. It is to provide a circuit.

[0008]

A PL according to one of the present inventions
The L circuit compares a phase of the input clock with a frequency-divided clock obtained by dividing the output clock by outputting a phase comparison signal, and outputs a phase comparison signal. In a PLL circuit including a phase comparison unit and a loop filter that generates the control voltage by limiting the band of the phase comparison signal to a loop band, the phase comparison unit may include a phase difference between the input clock and the divided clock. A first phase frequency comparator for comparing a phase difference between the input clock and the divided clock given a predetermined time delay, and a first phase frequency comparison And a synthesizing circuit for synthesizing an output of the phase comparator and an output of the second phase frequency comparator to output the phase comparison signal.

In one of the PLL circuits, the means for providing the delay of the predetermined time may be a time constant circuit.

[0010] Another one of the PLL circuits may be configured such that the means for giving the delay of the predetermined time is a transmission line.

According to another aspect of the present invention, there is provided a PLL circuit in which an output clock is phase-locked to an input clock by a control voltage, and a frequency divider which divides the output clock to generate divided clock information. And a decoder for generating a first comparison signal and a second comparison signal having a time difference from each other based on the divided clock information, and comparing a phase difference between the input clock and the first comparison signal. A first phase frequency comparator, a second phase frequency comparator for comparing the phase difference between the input clock and the second comparison signal, an output of the first phase frequency comparator and the second It is characterized by comprising a synthesizing circuit that synthesizes an output of a phase frequency comparator and outputs a phase comparison signal, and a loop filter that limits the band of the phase comparison signal to a loop band and generates the control voltage.

In one of the PLL circuits, the frequency divider includes:
The output clock may be a counter that converts the serial output clock to the parallel output clock and outputs the parallel divided clock information when the parallel output clock matches a predetermined number of clocks. it can.

Another one of the PLL circuits may be configured so that the decoder generates the first comparison signal and the second comparison signal at different times from each other based on the divided clock information.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a PLL circuit according to the present invention. FIG. 2 shows the PLL of FIG.
FIG. 7 is a diagram illustrating detection sensitivity with respect to a phase difference between the phase comparators 5 and 7 used in the circuit. FIG. 3 shows the phase comparators 5 and 7.
FIG. 4 is a diagram showing an example of input / output waveforms of FIG.

The PLL circuit shown in FIG. 1 includes a voltage-controlled oscillator (VCO) 10 in which the period of an output clock S10 is phase-locked to an input clock S1 by a control voltage S9, an input clock S1 supplied to an input terminal 1, and an output. Clock S
10 is compared with a frequency-divided clock S2 obtained by frequency-dividing the counter 10 by a counter 12 used as a frequency divider, and a phase comparison signal S
8 and a loop filter 10 that generates a control voltage S9 by limiting the band of the phase comparison signal S8 to a loop band. In many cases, the loop filter 10 has an amplifying function. The high-frequency component of the jitter included in the input clock S1 is obtained by setting the loop filter 10 to have a high-frequency gain reduction characteristic and controlling the control voltage S9 of the VCO 10.
It can be reduced by making the phase change between the clock and the output clock S10 respond in an integrated manner. While the control voltage S9 of the VCO 10 changes stepwise, the phase change of the output clock S10 from the VCO 10 is a change obtained by integrating the frequency difference and time.

Further, the phase comparison section 15 receives the input clock S
1 and a phase comparator 7 for comparing the phase difference between the input clock S1 and the divided clock S3 obtained by delaying the divided clock S2 by a predetermined time. And a combining circuit that combines the output S4 of the phase comparator 5 and the output S5 of the phase comparator 7 and outputs a phase comparison signal S8. Note that the phase comparators 5 and 7
Are phase frequency comparators having both dead zones and having substantially the same characteristics. Further, the output clock S10 and the frequency-divided clock S2 are supplied to output terminals 2 and 3 as clocks for another related device, respectively.

Here, the phase comparator 15 includes a counter 1
A delay circuit 4 for delaying the frequency-divided clock S2 from S2 by a predetermined time to generate a frequency-divided clock S3 is inserted. Of course, this delay circuit may be provided on the input clock S1 side. As the delay circuit 4, a CR time constant circuit is recommended when the divided clock S2 has a low frequency, and a transmission line such as a coaxial line is recommended when the divided clock S2 has a high frequency. A low-pass filter (LPF) 6 is inserted between the output terminal of the phase comparator 5 and one of the input terminals of the synthesizing circuit 9, and is connected between the output terminal of the phase comparator 7 and the input terminal of the synthesizing circuit 9. A low-pass filter (LPF) 8 is inserted between the other one. The LPFs 6 and 8 are provided for removing harmonic components in the outputs S4 and S5 of the phase comparator 5 and the phase comparator 7, respectively, and basically do not have a function of limiting a loop band. LPFs 6 and 8
May have the loop filter 10 replace its role.

The combining circuit 9 connects the output terminal of the LPF 6 and the output terminal of the LPF 8 with a resistor R1, as shown in the figure, and averages the output S4 of the LPF 6 and the output S5 of the LPF 8 from the middle point of the resistor R1. May be extracted (combined) and used as the phase comparison signal S8. Further, as shown in FIG. 1 of JP-A-11-127076, the outputs S4 and S4 of the phase comparator 5 and the phase comparator 7 are output as shown in FIG.
5 may be synthesized via a charge pump or the like.

In this PLL circuit, for example, in the case of the HDTV, the input clock S1 has a period of 74.25 MHz.
The output clock S10 is one of the bit parallel signals, and the output clock S10 is a 1.485 Gbps serial clock obtained by multiplying the input clock S1 by 20 with the VCO 11. On the contrary, the counter 12 converts a 1.485 Gbps serial clock into a clock S2 having a division ratio of 20 (that is, a clock having the same cycle as the input clock S1). Note that V
The output clock S10 from the CO 11 is a pulse signal, but may be a sine wave signal. In this case, the counter 12 may be shaped so that the sine wave signal looks like a pulse signal. In this example, the dead zones of the phase comparators 5 and 7 may be about 1% to 2% of the angle 2π. The dead zone may be larger when the number of multiplications of the output clock S10 is small or when the period is long.

The operation of the phase comparator 15 which is a major feature of the present invention will be described in detail with reference to FIGS. 1, 2 and 3.

The ideal characteristic of the phase comparator 5 (and 7), which is a frequency-phase comparator, is that the output S4 increases linearly when the phase difference between the input clock S1 and the divided clock S2 is from -π to + π ( If the frequency exceeds this range, the output S4 is fixed at -1 and +1 (or +1 and -1) up to the frequency pull-in range.
However, in the above-described general frequency phase comparator using the JK flip or the like, an operation error occurs when the input clock S1 and the divided clock S2 are applied almost simultaneously. This is the cause of producing a dead zone in the frequency phase comparator near the above-mentioned phase difference of 0 (Masayasu Hata et al., PLL
-How to use IC, p. 105, July 1981, Sanpo Publishing Co.).

Therefore, the phase comparator 15 uses two phase comparators 5 and 7 having a dead zone with different dead zone occurrence times (generation phases), and outputs the output S4 of the phase comparator 5 and the output S6 of the phase comparator 7 at different times. Are synthesized by the synthesizing circuit 9 to obtain the frequency / phase comparing unit 15 having no dead zone. That is, referring to FIG. 2, the phase comparator 5 directly compares the input clock S1 and the frequency-divided clock S2, and generates an output S4 having a dead zone d1 before and after the 01 phase of the input clock S1 (see (b)). ). On the other hand, the phase comparator 7 supplies the frequency-divided clock S3 to the other comparison clock input terminal at the 02 phase of the input clock S1 sufficiently delayed from the dead zone d1 (time difference t1) while the input clock S1 is the same. . Then, the phase comparator 6 generates an output S5 having a dead zone d2 before and after the 02 phase of the input clock S1 (see (c)).
This time difference t1 is given by the delay circuit 4. The output S4 is synthesized via the LPF 6 and the output S5 via the LPF 8 by the synthesizing circuit 9, and the output S8 has a dead-zone-free and substantially linearly changing phase comparison signal S8 (see (a)).

If the output linear ranges of the outputs S4 and S5 including the dead zones d1 and d2 of the phase comparators 5 and 7 are 2π (−π1 to + π1) and (−π2 to + π2), respectively, the phase comparator 15 Is more than 2π, which is the phase range of (−π1 to + π2) of the input clock S1. Since the phase difference detection unit 15 has lower phase difference detection sensitivity as compared with the case where one phase comparator is used,
It may be necessary to slightly increase the LL loop gain. When the loop gain of the PLL is very large, the phase of the frequency-divided clock S2 from the counter 12 is a phase advanced by half the delay time of the delay circuit 4 with respect to the input clock S1.

By shifting the phase (time) of the discontinuous portion of the phase difference detection characteristic between the phase comparator 5 and the phase comparator 7, the phase comparator 15 generates a phase comparison signal S8 that changes almost linearly. As a result, the PLL can obtain an output clock S10 that faithfully performs a PLL response to the jitter contained in the input clock S1. The high frequency component of the jitter included in the input clock S1 is obtained by setting the loop filter 10 to have a high frequency gain reduction characteristic and controlling the control voltage S of the VCO 10.
9 and the output clock S10 can be reduced by responding in an integrated manner to the phase change. While the control voltage S9 of the VCO 10 changes stepwise, the phase change of the output clock S10 from the VCO 10 is a change obtained by integrating the frequency difference and time.

Next, referring to FIG. 3, the phase comparator 5 of FIG.
Will be described as an example of the phase frequency comparator.

As shown in FIG. 5 of Japanese Patent Application Laid-Open No. H11-127076, the phase frequency comparator generally has a V (REFCLK) to which an input clock S1 is supplied.
R (DEVCL) to which the terminal and the divided clock S2 are supplied
K) terminal, and a U (UP) terminal and a D (DN) terminal serving as phase comparison output terminals. The phase comparator 5 of FIG. 3 combines the output of the U terminal and the output of the D terminal and outputs
It is expressed as The phase comparator 5 includes an input clock S1 input to an R terminal and a divided clock S input to a V terminal.
The pulse width of the output S4 changes in accordance with the phase difference from the output S2, and the DC component changes.

The phase of the input clock S1 is the divided clock S
When the phase is advanced from 2 by a phase corresponding to time t, a positive pulse having a time width t is generated at the U terminal, and "1" is generated at the D terminal. In FIG. 3, since the time difference t is small, the DC component output to the U terminal is about 0.2. U terminal output and D
The average DC voltage of the output S4 of the phase comparator 5 combined with the output of the terminal is about 1.2.

On the other hand, if the phase of the input clock S1 lags behind the divided clock S2 by a phase corresponding to the time t,
"0" is generated at the U terminal. At the same time width t as in the above figure, a pulse of time width (1-t) / 1 is generated at the D terminal,
In FIG. 3, since the time difference t is large, the DC component output to the U terminal is about 0.8. Therefore, the output of the U terminal and D
The average DC voltage of the output S4 of the phase comparator 5 obtained by combining the output of the terminal and the output of the terminal is about 0.8.

As described above, the output S4 of the phase comparator 5
Can vary from 0 to 2 around the output "1" due to the lead / lag of the phase relationship between the input clock S1 and the divided clock S2. If the midpoint is set to 0 V, the output S4 changes between -1 and +1 depending on the phase relationship between the input clock S1 and the divided clock S2 as shown in FIG. At the same time as the input clock S1 and the frequency-divided clock S2, a pulse may be output to both the U terminal and the D terminal, or neither pulse may be output. This state corresponds to a dead zone when the phase difference between the two clocks is near zero.

As described above, the PLL circuit according to the embodiment shown in FIG. 1 is provided with two phase comparators 5 and 7 having the same characteristic and having a dead zone, and thus a low-cost phase-frequency comparison unit having a simple configuration is provided. The input clock S1 or the divided clock S2 supplied to the phase comparators 5 and 7 is operated with a phase difference, and the outputs S4 and S5 are combined to linearly detect the phase difference between the two clocks. So we can do it
There is an effect that the dead zone can be eliminated and an output clock S10 can be obtained which has a PLL response faithfully to the jitter contained in the input clock S1.

FIG. 4 is a block diagram showing another embodiment of the PLL circuit according to the present invention.

In the PLL circuit shown in FIG. 4, the phase comparison section 15A operates on substantially the same operation principle as the embodiment shown in FIG. That is, a phase difference is provided between the frequency-divided clocks S3a and S3b supplied to the two phase comparators 5 and 7 having a dead zone. Loop filter 1 of this PLL circuit
0, VCO 11, input terminal 1, output terminals 2 and 3 are shown in FIG.
Performs the same configuration and operation as the PLL circuit of FIG. An input clock S1 is input from an input terminal 1, and an output clock S10 and a divided clock S2a are supplied to output terminals 2 and 3 as clocks for another related device, respectively. The LPF 6 between the phase comparator 5 and the synthesizing circuit 9 and the LPF 8 between the phase comparator 7 and the synthesizing circuit 9 are not shown.

The PLL circuit shown in FIG. 4 is characterized by a counter 12A having a frequency dividing function and a decoder 41 for providing a phase difference between the frequency-divided clocks S3a and S3b instead of the delay circuit 4. The counter 12A converts the serial output clock S10 from the VCO 11 into a predetermined count value, for example, a parallel count value S2a that repeats every count value 20. When the count value of the output clock S10 reaches the predetermined count value, the counter 12A counts the count value S.
2a is cleared, and the process returns to the initial state (count value S2a = 0). That is, the decoder 41 of this example uses the output clock S1
It has the function of dividing 0 by 20. The counter 12A supplies the count value S2a to the decoder 41. Count value S2a = 0
Are used as reference information (of phase or time) of the divided clock.

The decoder 41 receives the count value S2a of the output clock S10 from the counter 12A and receives the count value S2a from the counter 12A.
At different times from each other as the divided clock (reference) information.
Is generated. The frequency-divided clock S3a is used as a phase comparison signal replacing the frequency-divided clock S2 of the phase comparator 5 in FIG. 1, and the frequency-divided clock S3b is used as a phase comparison signal replacing the frequency-divided clock S3 of the phase comparator 7. Since all circuits in the PLL circuit shown in FIG. 4 can be constituted by digital circuits, there is an effect that it is suitable for miniaturization and mass production.

FIG. 5 is a detailed block diagram of the counter 12A and the decoder 41 used in the PLL circuit of FIG. FIG. 6 is a timing chart of the counter 12A and the decoder 41 of FIG.

Referring to FIGS. 5 and 6, the counter 12
A counts the serial format output clock S10 from 0 to 19 by the counter 121, and supplies a count value S2a, which is a 5-bit parallel format signal, to the decoder 122 from the D0 to D4 terminals. That is, the counter 1
21 is D as the count value S2a of the output clock S10.
0 terminal, output clock S10 divided by 2 clock, D1
A 4 divided clock from the terminal, a 8 divided clock from the D2 terminal, a 16 divided clock from the D3 terminal, and a 32 divided clock from the D4 terminal are supplied to the decoder 122, respectively. When the count value S2a becomes 19, the decoder 122
The clear signal S121 is output to the clear terminal of the counter 121. When the count is cleared by the clear signal S121, the counter 121 converts all outputs from the D0 terminal to the D4 terminal, that is, the count value S2a to "0". D4
The output from the terminal is originally 1/3 of the output clock S10.
Although the clock is a frequency-divided-by-2 clock, “1” is output before the output clock S10 is counted 32 times by clearing the counter 121.
Is converted to "0". The conversion timing of the output from the D0 terminal to the D4 terminal to "0" is determined by the output clock S10.
Is the reference timing at the start of counting, ie, divided clock information. Note that the counter 12A can be used as the counter 12 in FIG. 1, and in this case, the clear signal S
121 is used as the divided clock S2.

The decoder 41 changes the count value S2a from 0 to 1.
It includes a decoder 411 that outputs a divided clock S3a when counting to 3, and a decoder 122 that outputs a divided clock S3b when counting the count value S2a from 0 to 19. The starting point of the count values S2a of the decoders 411 and 122 is the time when the count values S2a are all "0", that is, the time when the divided clock information from the counter 12A is obtained.
In the example shown in FIGS. 5 and 6, the output (delay) time difference between the divided clock S3a and the divided clock S3b is six clocks of the output clock S10. This time difference can be freely changed from one clock of the output clock S10 to 19 clocks by appropriately setting the count numbers of the count values S2a of the decoders 122 and 411, respectively. In this example, the decoder 122 in the decoder 41
Is the same as the decoder 122 in the counter 12A, the decoder 122 in the decoder 41 is omitted, and the counter 12A
May be used as the frequency-divided clock S3b.

[0039]

As described above, the present invention provides a voltage controlled oscillator in which an output clock is phase-locked to an input clock by a control voltage, and the phase of the input clock and the divided clock obtained by dividing the output clock. In a PLL circuit comprising: a phase comparison unit that performs comparison and outputs a phase comparison signal; and a loop filter that limits the band of the phase comparison signal to a loop band and generates the control voltage. A first phase frequency comparator for comparing a phase difference between a clock and the divided clock; and a second phase frequency comparison for comparing a phase difference between the input clock and the divided clock given a predetermined time delay. And a combining circuit that combines the output of the first phase frequency comparator and the output of the second phase frequency comparator to output the phase comparison signal. , Even at high frequencies, there is an effect that it is possible to obtain an output clock structure faithfully by phase-synchronization response jitter included in the input clock with a phase frequency comparator which can cheaper simple and purchase unit price.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a PLL circuit according to the present invention.

FIG. 2 is a diagram showing detection sensitivity with respect to a phase difference between phase comparators 5 and 7 in FIG. 1;

FIG. 3 is a diagram showing an example of input / output waveforms of phase comparators 5 and 7.

FIG. 4 is a block diagram showing another embodiment of the PLL circuit according to the present invention.

FIG. 5 is a detailed block diagram of a counter 12A and a decoder 41 used in the PLL circuit of FIG. 4;

6 is a timing chart of the counter 12A and the decoder 41 of FIG.

FIG. 7 is a block diagram of a PLL circuit according to the related art.

8 is a diagram showing detection sensitivity to a phase difference of a phase / frequency comparison circuit unit 50 used in the PLL circuit of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2, 3 Output terminal 4 Delay circuit 5, 7 Phase comparator 6, 8 Low-pass filter (LPF) 9 Synthesis circuit 10 Loop filter 11 Voltage controlled oscillator (VCO) 12, 12A Counter 41 Decoder

Claims (6)

[Claims] A phase comparison signal is output by comparing a phase of a voltage-controlled oscillator whose output clock is phase-locked to an input clock by a control voltage and a frequency-divided clock obtained by dividing the output clock. And a loop filter that limits the band of the phase comparison signal to a loop band and generates the control voltage.
In the circuit, the phase comparison unit may include a first phase frequency comparator that compares a phase difference between the input clock and the frequency-divided clock, and a frequency-divided clock that is delayed from the input clock by a predetermined time. A second phase frequency comparator for comparing the phase difference,
A PLL circuit comprising: a combining circuit that combines an output of the first phase frequency comparator and an output of the second phase frequency comparator to output the phase comparison signal. 2. The PLL according to claim 1, wherein the means for delaying the predetermined time is a time constant circuit.
circuit. 3. The PLL circuit according to claim 1, wherein the means for giving a predetermined time delay is a transmission line. 4. A voltage-controlled oscillator in which an output clock is phase-locked to an input clock by a control voltage, a frequency divider that divides the output clock to generate divided clock information, and a reference to the divided clock information. A decoder that generates a first comparison signal and a second comparison signal having a time difference from each other, a first phase frequency comparator that compares a phase difference between the input clock and the first comparison signal, A second phase frequency comparator that compares the phase difference between the input clock and the second comparison signal, and combines the output of the first phase frequency comparator and the output of the second phase frequency comparator. A PLL circuit comprising: a synthesis circuit that outputs a phase comparison signal through a loop; and a loop filter that limits the band of the phase comparison signal to a loop band and generates the control voltage. 5. The frequency divider converts the serial format output clock to the parallel format output clock and, when the parallel format output clock matches a predetermined number of clocks, the parallel format divided clock information. 5. The PLL circuit according to claim 4, wherein the PLL circuit outputs a counter. 6. The PLL circuit according to claim 5, wherein the decoder generates the first comparison signal and the second comparison signal at different times from each other based on the divided clock information.