JP2001119025A - Semiconductor device and method of forming the same - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] An insulated gate semiconductor device formed by forming a trench structure on an α-SiC (0001) Si surface and oxidizing it can efficiently apply an electric field to a channel region while maintaining a high breakdown voltage. When an insulated gate semiconductor device including a planar type channel region is formed, damage due to ion implantation remains in the channel region, and high mobility cannot be realized. SOLUTION: An n-type layer 32 grown on an n-type SiC substrate 31 and a p-type layer 33 further grown thereon, and a part of the p-type layer 33 are subjected to, for example, ion implantation and heat treatment. An insulated gate semiconductor device characterized in that there is an n-type portion 34 whose semiconductor properties have been changed by, and at least a part of the n-type portion 34 is electrically continuous with the n-type layer 32. is there.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device using silicon carbide and, more particularly, to a vertical insulated gate semiconductor device suitable for high power applications having a high withstand voltage and a large current capacity. .

[0002]

2. Description of the Related Art A conventional insulated gate type semiconductor device such as Si described as Conventional Example 1 has an n-type epitaxial growth layer (n-type layer) 2 formed on an n-type substrate 1 as shown in FIG. Then, a p-type part 3 is formed by diffusing or ion-implanting an impurity which forms a p-type semiconductor such as B into a part of the p-type part.
Is diffused or ion-implanted to form an n-type portion 4. An oxide insulating film 7 is formed on the surface 6 of the p-type portion sandwiched between the portion 5 where the n-type layer 2 reaches the surface and the n-type portion 4, and a gate electrode 8 is further formed on the surface. Provide. The drain electrode 9 is formed on the back surface of the substrate, and the source electrode 10 is formed in contact with the n-type portion 4 and the p-type portion 3. In the insulated gate semiconductor element, the inversion layer formed on the surface 6 of the p-type portion by the bias to the gate electrode 8 functions as a channel. This channel region is required to have an interface with the insulating film 7 which has few crystal defects and has good crystallinity. In the above-described formation method, the channel region is basically formed by lateral diffusion, and no crystal defect due to ion implantation is introduced into the channel region. Even if the channel region has been subjected to ion implantation, in the case of Si, a heat treatment technology to be performed later is established, and a channel region with a low defect density can be formed.

Further, in the conventional silicon carbide insulated gate type semiconductor element described as a second conventional example, a silicon carbide surface is oxidized to form silicon oxide, thereby forming an insulating film. As shown in FIG. 2B, an insulated gate semiconductor device including a trench structure is first formed on an n-type substrate 11 of silicon carbide, which is electrically conductive.
A type epitaxial growth layer 12 is formed by CVD, and a p-type epitaxial growth layer (p-type layer) 13 is stacked on the surface to form a double-layered structure. Further, the surface is partially subjected to ion implantation and heat treatment to partially form the n + layer 14, thereby forming an n + / p / n laminated structure. A trench structure 15 is formed from the surface having the laminated structure by using photolithography technology and etching technology. The surface of the substrate having the trench structure is oxidized to form a silicon oxide insulating film 1.
6 is formed, and a gate electrode 17 is formed by laminating in a trench portion covered with a silicon oxide insulating film. Drain electrode 18
Is formed from the back surface of the n + type substrate 11 and the source electrode 19 is formed so as to be in contact with the n + layer 14 and the p type epitaxial growth layer 13 on the front surface. Thus, conventionally, an insulated gate semiconductor device having a trench structure has been formed. A channel region 20 which is turned on / off by a voltage applied to the gate electrode 17 is formed at an interface between the p-type epitaxial layer 13 corresponding to the trench wall surface and the insulating film 16. The contents of this prior art include, for example, Silicon Carbide; A Review of
FundamentalQuestions and Applications to Current D
evice Technology, edited by WJChoyke, H.Matsunam
i, and G. Pensl, Akademie Verlag 1997 Vol.II p
It is disclosed on pages 369-388.

[0004]

The insulated gate semiconductor device as in the first prior art shown in FIG.
Instead, consider the case of using silicon carbide. In the conventional example, the channel region is basically formed by lateral diffusion, and no crystal defect of ion implantation is introduced in the channel region.However, silicon carbide is the same as the case of Si described in the first conventional example. Since such diffusion of impurities does not occur, it is impossible to realize such a low-defect channel region forming process. In order to form a semiconductor device structure including the same p-type and n-type parts as in FIG. 2A, it is necessary to form a p-type part by ion implantation, and the surface of the p-type part must be formed by ion implantation. It will contain crystal defects. Furthermore, since silicon carbide has no liquid phase in the phase diagram under normal pressure and is stable up to a very high temperature of 2000 ° C. or more, it is difficult to remove crystal defects introduced by ion implantation by annealing through heat treatment. . Therefore, it is difficult to realize the structure of the insulated gate semiconductor device of FIG. 2A using silicon carbide by using the same process as the conventional example using Si.

It is known that silicon carbide forming the insulated gate semiconductor element described in the second conventional example is a directional crystal and has a different oxidation rate with respect to the crystal orientation. The α-SiC (0001) Si plane is the plane having the slowest oxidation rate, and the α-SiC (000-1) C plane obtained by rotating this plane by 180 degrees is the plane having the fastest oxidation rate. When a surface of a complex element structure including a surface corresponding to a plurality of different crystal orientations such as a trench structure is oxidized to form a silicon oxide insulation film, the thickness of the silicon oxide insulation film formed with respect to the crystal orientation is increased. Therefore, the oxide film thickness is unevenly distributed in the trench structure portion, and there are a portion where the electric field applied to the insulating film between the gate electrode and the silicon carbide semiconductor is strong and a portion where the electric field is weak.

For example, when the above-mentioned insulated gate semiconductor device is formed on the α-SiC (0001) Si surface from which an epitaxially grown layer having good crystallinity is obtained, as shown in FIG. A thin silicon oxide film 23 on the trench bottom surface 22 and a relatively thick silicon oxide film 16 on the trench wall surface 20
Is formed. Since the gate electrode 17 is also formed on the surface of the insulating film 23 on the trench bottom surface 22 over the entire trench structure, a larger electric field is applied to the insulating film 23 on the trench bottom surface 22 than the insulating film 16 on the channel portion of the trench wall surface 20. Will be applied. Such α-SiC
When a high-voltage insulated gate semiconductor element is formed on the (0001) Si surface, if an insulating film having a sufficient thickness is formed in consideration of the withstand voltage, a thicker insulating film 16 is formed as shown in FIG. There is a problem that the efficiency of the response of the device to the gate voltage is deteriorated because it is formed on the channel portion 20. When the thickness of the gate insulating film 16 on the channel portion 20 is kept at an optimum thickness, a thinner insulating film 23 is formed on the trench bottom surface 22, and the withstand voltage of this portion is reduced. For this reason, in the above prior art, α-S
It has been difficult to achieve high efficiency and high withstand voltage in a high withstand voltage power device having a trench structure formed on the iC (0001) Si surface.

In order to solve the problems in the first and second prior arts, at least n grown on a substrate is used.
A p-type layer grown thereon, further comprising a p-type layer, a part of the p-type layer includes an n-type part having semiconductor properties changed by ion implantation, for example, and the n-type An insulated gate semiconductor device in which at least a part of the portion is electrically continuous with the underlying n-type layer has been invented. By adopting this structure and the manufacturing method, a process in which ion implantation damage is not introduced into the channel region described in the above-described conventional example 1 is realized, and an insulated gate semiconductor element having excellent characteristics is realized by silicon carbide. Further, there is no need to form a trench structure as in the conventional example 2 in order to form a channel region in the p-type portion, and an insulated gate semiconductor device can be realized by a simple structure in which an insulated gate is formed on the surface. Further, there is no need to consider the problem of dielectric strength due to the formation of the trench structure described in the above-mentioned conventional example 2. in this way,
An object of the present invention is to realize a simple insulated gate semiconductor device using silicon carbide with a simple structure process.

[0008]

SUMMARY OF THE INVENTION The present invention comprises at least an n-type layer grown on a substrate and a p-type layer further grown on the n-type layer. Accordingly, there is an n-type portion whose semiconductor properties are changed, and at least a part of the n-type portion is electrically continuous with the underlying n-type layer.

In the semiconductor device, it is preferable that the substrate is a silicon carbide substrate, and both the n-type layer and the p-type layer are formed of a silicon carbide thin film.

In the semiconductor device, the silicon carbide substrate may be made of β-SiC (111) or α-SiC (0001) such as 6H, 4H or 15R-SiC.
C Si surface or off-cut surface within 10 degrees or β-
Α-SiC (0001) such as SiC (100) and β-SiC (110) or 6H, 4H and α-SiC (1-100) and α-SiC (11-20) or off-cut surface within 15 degrees It is preferred that

[0011] In the semiconductor device, another n-type portion surrounded by the p-type layer except for the surface portion is provided near the surface of the p-type layer. A source electrode in contact therewith, a drain electrode formed on the back surface of the substrate, an insulating film formed so as to cover at least the surface of the p-type layer sandwiched between the n-type part and another n-type part, A semiconductor element including at least a gate electrode provided on a film.

According to the method of forming a semiconductor device of the present invention, an n-type layer is grown on a silicon carbide substrate in at least a first process, and a p-type layer is further grown on the n-type layer in a second process. In the process, an n-type part obtained by changing a part of the p-type layer is ion-implanted so as to be electrically continuous with the underlying n-type layer.
The n-type part in which a part of the mold layer is changed and another n-type part discontinuous are ion-implanted, and a heat treatment is performed in a fifth process to activate the ion-implanted impurities and to form a p-type impurity. Forming the n-type portion and another n-type portion in the layer, and covering at least a surface of the p-type layer sandwiched between the n-type portion and another n-type portion in a sixth process; Forming an insulating film formed as described above,
In the above process, a gate electrode provided on the insulating film is formed.

In the method for forming a semiconductor device, the third
In addition, it is preferable that the energy of ions for ion implantation in the fourth process be 1 keV or more and 20 MeV or less.

In the method for forming a semiconductor device, the third
In addition, it is preferable to select two or more types of energy of ions for performing ion implantation in the fourth process and perform multiple implantation.

Further, in the third process, the energy of the ions for performing the ion implantation for forming the n-type portion so as to be electrically continuous with the underlying n-type layer is increased by the energy of the n-type portion in the fourth process. Is preferably larger than the energy of the ions to be implanted to form another n-type portion that is discontinuous.

In the third and fourth processes, the dose of ions for ion implantation is preferably 10 ¹⁴ cm ⁻² or more.

When ion implantation is performed in the third and fourth processes, it is preferable that the silicon carbide substrate is kept at 300 ° C. or higher.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a method for forming a semiconductor device according to the present invention comprises an epitaxially grown n-type layer 32, an epitaxially grown p-type layer 32 on an n + type silicon carbide substrate 31 which is, for example, an α-SiC (0001) Si plane. The mold layer 33 is grown and partially ion-implanted into a part of the p-type layer and heat-treated.
An n-type portion 34 was formed. In this case, the n-type portion 34
Was formed so as to penetrate through the p-type layer 33 and be electrically continuous with the n-type layer 32. Next, ion implantation was performed at a lower ion energy than when the n-type portion 34 was formed, thereby forming another n-type portion 35. In this case, another n-type portion 35 is formed in the p-type layer 33 in a state surrounded by the p-type layer 33 except for the surface 36, and both the n-type layer 32 and the n-type portion 34 are electrically connected. It is discontinuous.
By oxidizing the surface of the wafer, at least an n-type portion 3
An oxide insulating film 38 was formed so as to cover the surface 37 of the p-type layer sandwiched between 4 and another n-type portion 35. Further, a gate electrode 39 was formed on the surface of the oxide insulating film 38. A drain electrode 40 was formed on the back surface of the substrate, and a source electrode 36 was formed so as to extend over the surface of the p-type layer on the substrate surface and another n-type portion 35. The channel region controlled by the gate electrode of this MOSFET is the surface 37 of the p-type layer. The channel region 37 is a portion that has not been damaged by ion implantation, etching, or the like after the epitaxial growth of the p-type layer 33, and a low-damage, high-mobility channel was formed. Further, it is not necessary to form a complicated structure such as the trench structure as described in the conventional example 2, and a high-performance SiC MOSFET is realized with a simple structure. The oxide insulating film 38 under the gate electrode can be set to an ideal oxide insulating film thickness without having to consider the destruction due to electric field concentration as in the case of the oxidation of the trench structure. As described above, the semiconductor includes at least the n-type layer 32 grown on the substrate and the p-type layer 33 further grown thereon. A high-performance semiconductor device, characterized in that there is an n-type part 34 having changed physical properties, and at least a part of the n-type part 34 is electrically continuous with the n-type layer 32. I realized it.

In the above-described semiconductor device, a semiconductor device in which the substrate is a silicon carbide substrate and both the n-type layer and the p-type layer are formed of a silicon carbide thin film has been described.
Even if it is made of a semiconductor material such as Si, it functions as an excellent MOSFET.

In the semiconductor device, the silicon carbide substrate 3
1 is β-SiC (111) or α-SiC (0001) such as 6H, 4H or 15R-
Si surface of SiC or its off-cut surface within 10 degrees, or α-SiC (000) such as β-SiC (100) and β-SiC (110) or 6H, 4H
1) and α-SiC (1-100) and α-SiC (11-20) or an off-cut plane of 15 ° or less, good crystal growth by epitaxial growth of the n-type layer 32 and p-type layer 33 And a smooth surface is obtained.

In the semiconductor device, the p-type layer 33
Near the surface includes another n-type portion 35 surrounded by the p-type layer 33 except for the surface portion 36.
A source electrode 41 at least in contact with the mold part 35, a drain electrode 40 formed on the back surface of the substrate, and a surface 37 of the p-type layer sandwiched between the n-type part and another n-type part
Having at least the insulating film 38 formed so as to cover at least the gate electrode 39 provided on the insulating film, the insulated gate type MOSFET can be used for ion implantation or the like in the channel portion. It can be formed without introducing defects, and can achieve a MOSFET having a large channel mobility, which is preferable.

According to the method for forming a semiconductor device of the present invention, an n-type layer 32 is grown on a silicon carbide substrate 31 in at least a first process, and a p-type layer 33 is further grown on the n-type layer 32 in a second process. In the third process, the n-type part 34 obtained by changing a part of the p-type layer is replaced with the underlying n-type layer 3.
2 is ion-implanted so as to be electrically continuous with the second n-type portion 35 and another n-type portion 35 discontinuous with the n-type portion obtained by partially changing the p-type layer in the fourth process. Then, by performing heat treatment in the fifth process, the ion-implanted impurities are activated to form the n-type portion 34 and another n-type portion 35 in the p-type layer 33, and in the sixth process, An insulating film 38 is formed so as to cover at least the surface 37 of the p-type layer sandwiched between the n-type portion 34 and another n-type portion 35, and is formed on the insulating film 38 in a seventh process. In which the gate electrode 39 is formed. According to this forming method, a planar type MOSFET having a simple structure not including a trench structure or the like can be achieved, and the current flows through the electrode 36-another n-type portion 35-channel 37-n-type portion 3.
By flowing through the 4-n-type layer 32-substrate 31-electrode 40 and forming this basic structure on many surfaces, a power MOSFET that controls high current and high voltage was realized.

In the method for forming a semiconductor device, the third
If the energy of the ions for performing ion implantation in the fourth process is 1 keV or more and 20 MeV or less, an ion implantation apparatus can be used with a general object, and an n-type layer having a depth ranging from several microns to about 100 angstroms is formed. It can be formed and is preferable. In the case of an energy of 1 keV or less, the n-type part or another n-type part by ion implantation becomes very thin, and a MOSFET having a withstand voltage which is the object of the present invention.
Cannot be formed. It is difficult to form ions of 10 MeV or more, and it is difficult to implement the semi-invention.

In the method for forming a semiconductor element, the third
In addition, in the fourth process, it is preferable to select two or more types of ion energy for performing ion implantation and perform multiple implantation so that a box-type implantation layer having a small distribution with respect to the depth can be formed.

Further, in the third process, the energy of the ions for performing the ion implantation for forming the n-type portion so as to be electrically continuous with the underlying n-type layer is increased by the energy of the n-type portion in the fourth process. The n-type portion is formed deeper than the other n-type portion if the energy is greater than the energy of the ion implanted to form another n-type portion that is discontinuous. The electrical continuity between the n-type portion and the n-type layer is improved, and the withstand voltage due to the p / n junction between the other n-type layer and the p-type layer is preferably improved.

If the dose of ions to be ion-implanted in the third and fourth processes is 10 ¹⁴ cm ⁻² or more, a high-concentration n-type part and another n-type part Can be preferably formed. In this case, if the dose is less than 10 ¹⁴ cm ^-2 , the carrier concentration in the ion-implanted portion becomes small, and the resistance becomes high, which is not suitable for forming a power semiconductor element.

When ion implantation is performed in the third and fourth processes, if the silicon carbide substrate is kept at 300 ° C. or higher, ion bombardment lattice defects are annealed to some extent during ion implantation, and impurities after heat treatment are removed. Activation is promoted and preferred.

[0028]

EXAMPLE 1 Example 1 shows a first example of a method for forming a semiconductor device according to the present invention. As shown in FIG. 1, a substrate 31 having a nitrogen concentration of ³ × 10 ¹⁸ cm ^{−3 and} an n-type 6H-SiC (0001) Si surface [11-20] with a 4 ° off-cut is prepared. A 5 × 10 ¹⁵ cm ^-3 nitrogen ton type epitaxial growth layer 32 having a thickness of 6 μm is formed as a first process, and a 2 × 10 ¹⁷ cm ^-3 layer having a thickness of 2 μm is formed thereon as a second process.
An Al top p-type epitaxial growth layer 33 was formed.
A metal mask is formed on the surface of this p-type epitaxial growth layer, and seven steps of ion energies are selectively selected in the range of 0.9 to 7.0 MeV as a third process, each of which is 3 × 10 ¹⁴ cm ^−2.
N was ion-implanted at a dose of. By this process, an n-type portion 34 is formed to a depth of about 3 microns, and this depth reaches a portion deeper than the p-type layer 33. The n-type portion 34 is electrically connected to the underlying n-type layer 32. It becomes continuous continuously. Next, another metal mask is formed, and as a fourth process, ion implantation of nitrogen is performed at 5 × 10 ¹⁵ c with an energy of 20 keV.
Another n-type portion 35 was formed at a dose of m- ² . The temperature of the substrate during the ion implantation was 500 ° C. This ion-implanted substrate was heat-treated at 1500 ° C. as a fifth process to activate these ion-implanted layers to complete an n-type portion and another n-type portion.

Next, as a sixth process, the above 6H-SiC (0
001) The Si surface substrate was introduced into an oxidation treatment furnace, and wet oxidation was performed at 1100 ° C. for 3 hours. The surface of the SiC substrate is oxidized and
A silicon oxide film 38 having a thickness of 00 ° was formed.

A contact hole or the like is formed in the silicon oxide film by photolithographic etching, an ohmic electrode of Ni is deposited, and heat treatment is performed to form a source electrode 41 and a drain electrode 40. Further, as a seventh process, polysilicon is used. The gate electrode 39 was formed to form the insulated gate semiconductor device of FIG.

In this embodiment, the above 6H-SiC (0001)
Although a 4 ° off-cut substrate was used for the Si surface [11-20] direction, the silicon carbide substrate was β-SiC (111) or α-SiC (0001) such as 6H, 4H or 15R-SiC Si surface or its Off cut surface within 10 degrees, or α- such as β-SiC (100) and β-SiC (110) or 6H, 4H
At least an n-type epitaxial growth layer and a p-type epitaxial growth layer are grown on at least an n-type substrate on SiC (0001) and α-SiC (1-100) and α-SiC (11-20) or an off-cut surface within 15 degrees thereof. It has been confirmed that the present invention can be implemented if the multilayer structure is included. It has been confirmed that another n-type portion may be epitaxially grown without being formed by ion implantation as in this embodiment.

In this embodiment, the multi-stage implantation of seven steps and the case of 20 keV in which the energy of the ions for ion implantation is in the range of 0.9 to 7.0 MeV has been described.
The present invention can be realized within the following ranges. Also,
When two or more types were selected and the multiple implantations were performed in the above energy range, a box profile having a uniform torrent could be formed, and the present invention could be realized.

In this embodiment, when performing ion implantation, the silicon carbide substrate was kept at 500 ° C.
If the temperature is kept at not less than ℃, the irradiation damage is annealed to some extent during the ion irradiation, and the present invention can be realized.

In this embodiment, as the gate insulating film
6H-SiC (0001) Si surface substrate is introduced into oxidation treatment furnace and 1100
A silicon oxide film formed by performing wet oxidation at 3 ° C. for 3 hours was used. For example, a silicon oxide film formed by a CVD method, an insulating oxide film such as an aluminum oxide film, a ferroelectric film, an insulating nitride film, etc. Even when used, the present invention could be realized.

In this embodiment, the carriers running in the channel region are electrons, but the present invention can be realized also when the carriers are holes when the n-type and p-type semiconductor elements are exchanged.

The silicon carbide insulated gate semiconductor device formed by the method for forming a semiconductor device described in the above embodiment exhibited a withstand voltage of 400 V or more. According to the present example, a silicon carbide insulated gate semiconductor element, which is a high-voltage power element having a simple planar structure, was formed on the (0001) Si plane of silicon carbide. In particular, the channel mobility of the insulated gate semiconductor device formed in this embodiment is 20% or more of the channel mobility of the device formed of silicon carbide including the ion bombardment in the channel portion shown in the conventional example 1. It showed a large value, and it was confirmed that a channel 37 having a good silicon carbide semiconductor / silicon oxide insulator interface and a high mobility was formed.

[0037]

As described above, according to the present invention, an insulated gate semiconductor device can be realized by a simple structure in which an insulated gate is formed on a surface, and has a withstand voltage of 400 V or more.
A silicon carbide insulated gate semiconductor element can be formed. Also,
An insulated gate semiconductor device using silicon carbide, which is capable of forming a vertical insulated gate semiconductor device having a high withstand voltage and a large current capacity and suitable for large power use.

[Brief description of the drawings]

FIG. 1 is a conceptual explanatory sectional view of a semiconductor device of the present invention.

2A is a structural sectional view of an insulated gate semiconductor device of Conventional Example 1; and FIG. 2B is a structural sectional view of a silicon carbide insulated gate semiconductor device including a trench structure of Conventional Example 2.

[Explanation of symbols]

 Reference Signs List 1 n-type substrate 2 n-type epitaxial growth layer (n-type layer) 3 p-type part 4 n-type part 5 part where n-type layer reaches surface 6 channel region 7 oxide insulating film 8 gate electrode 9 drain electrode 10 source Electrode 11 n-type substrate 12 n-type epitaxial growth layer (n-type layer) 13 p-type epitaxial growth layer (p-type layer) 14 n + type layer 15 trench structure 16 oxide insulating film 17 gate electrode 18 drain electrode 19 source electrode 20 channel region 21 wafer Surface 22 Trench bottom 23 Thin oxide insulating film 31 n-type substrate 32 n-type epitaxial growth layer (n-type layer) 33 p-type epitaxial growth layer (p-type layer) 34 n-type part 35 another n-type part 36 another Surface of n-type portion 37 Channel region 38 Insulating film 39 Gate electrode 40 Drain electrode 41 Source electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Osamu Kusumoto, Inventor 1006 Kadoma Kadoma, Osaka Prefecture, Matsushita Electric Industrial Co., Ltd. 72) Kunikata Takahashi 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (10)

[Claims] 1. A semiconductor device comprising at least an n-type layer grown on a substrate and a p-type layer further grown thereon. A semiconductor element, wherein a changed n-type portion exists, and at least a part of the n-type portion is electrically continuous with the n-type layer. 2. The semiconductor device according to claim 1, wherein the substrate is a silicon carbide substrate, and both the n-type layer and the p-type layer are formed of a silicon carbide thin film. 3. The semiconductor device according to claim 2, wherein the silicon carbide substrate is made of β-SiC (111) or α-SiC (0001) such as 6H, 4H.
Or 15R-SiC Si surface or its off-cut surface within 10 degrees, or β-SiC (100) and β-SiC (110) or α- such as 6H, 4H
A semiconductor device characterized by SiC (0001), α-SiC (1-100) and α-SiC (11-20) or an off-cut surface of 15 degrees or less thereof. 4. The semiconductor device according to claim 1, further comprising, near the surface of the p-type layer, another n-type portion surrounded by a p-type layer except for the surface portion. a source electrode at least in contact with the n-type portion, a drain electrode formed on the back surface of the substrate, the n-type portion and another n
A semiconductor device comprising at least an insulating film formed so as to cover at least a surface of a p-type layer sandwiched between mold portions, and a gate electrode provided on the insulating film. 5. The method according to claim 5, wherein an n-type layer is grown on the silicon carbide substrate in the first process, a p-type layer is further grown on the second process, and the p-type layer is grown on the third process. The n-type part with a part changed is the base n
Ion implantation so that it is electrically continuous with the mold layer,
The above n obtained by changing a part of the p-type layer in the fourth process.
Another n-type portion that is discontinuous to the n-type portion is ion-implanted, and a heat treatment is performed in a fifth process to activate the ion-implanted impurity, and another n-type portion is added to the p-type layer in the p-type layer. Forming an n-type portion, and forming an insulating film formed so as to cover at least a surface of the p-type layer sandwiched between the n-type portion and another n-type portion in the sixth process; A method for forming a semiconductor device, comprising at least a process for forming a gate electrode provided on the insulating film in the seventh process. 6. The method for forming a semiconductor device according to claim 5, wherein the energy of the ions for performing the ion implantation in the third and fourth processes is 1 keV or more and 20 MeV or less. 7. The method according to claim 7, wherein two or more types of ions to be ion-implanted in the third and fourth processes are selected, and multiple ions are implanted. In the third process, n is electrically connected to the underlying n-type layer. The energy of the ions for performing the ion implantation for forming the mold portion is larger than the energy of the ions for performing the ion implantation for forming another n-type portion discontinuous with the n-type portion in the fourth process. 6. The method for forming a semiconductor device according to claim 5, wherein: 8. The method for forming a semiconductor device according to claim 5, wherein the dose of ions for performing ion implantation in the third and fourth processes is 10 ¹⁴ cm ⁻² or more. 9. The method according to claim 5, wherein the temperature of the silicon carbide substrate is kept at 300 ° C. or more when performing ion implantation in the third and fourth processes. 10. The method for forming a semiconductor device according to claim 5, wherein the p-type and the n-type of each component of the semiconductor are interchanged.