JP2001118856A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: In a lateral bipolar transistor formed on an SOI substrate, since an emitter diffusion layer is formed in single crystal silicon, a large amount of minority carriers are injected from the base to the emitter. High frequency response characteristics were degraded. An object of the present invention is to solve this problem. A base region is formed in single crystal silicon. Further, after the base region 10 is removed by etching using the sidewall material 12 of the base electrode as a mask, a polysilicon layer is deposited, and an N-type impurity is added.
An emitter polysilicon layer 14 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the manufacture of a lateral bipolar transistor on an SOI substrate.

[0002]

2. Description of the Related Art In recent years, analog LSIs have been developed for mounting in portable communication devices. However, in order to realize a longer standby reception time and a longer talk time, low power consumption of transistors is required. Is regarded as an important issue. Hereinafter, a method for manufacturing a bipolar transistor formed using a conventional technique as shown in the drawings will be described.
First, as shown in FIG. 10, on an SOI substrate including a silicon substrate 21, an oxide film 22, and a single crystal silicon layer 23,
After oxide film 24 is formed by thermal oxidation, N-type impurity ions are implanted to form single-crystal silicon layer 23 as N-type collector region 25. Next, as shown in FIG. 11, after removing the oxide film 24 on the surface using an HF-based solution, a polysilicon layer 26 of about 500 ° is deposited by LPCVD, and a P-type impurity is doped by ion implantation. Then, a nitride film 27 of about 200 ° is deposited. Next, as shown in FIG. 12, the nitride film 27 is formed by patterning by lithography and etching by RIE.
After processing into a predetermined shape, about 2
An oxide film 28 of 000 ° is deposited. Subsequently, the oxide film 28 is formed by using lithography patterning and RIE.
Is processed into a predetermined shape.

[0003] This oxide film etching is performed under the condition that the nitride film and silicon are hardly etched. Next, as shown in FIG. 13, using the nitride film 27 as a mask,
The polysilicon layer 26 and the N-type collector region 25 are etched by RIE. Next, as shown in FIG.
Using IE, the region exposed on the surface by the nitride film 27 is removed by etching. At this time, the oxide film 28 and the oxide film 22
The area exposed on the surface is also etched somewhat.
Then, continuously using RIE, the N-type collector region 2 is formed.
The region exposed on the surface is etched partway through the N-type collector region 25. Next, as shown in FIG.
After depositing an oxide film 29 of about 200 ° on the surface of the substrate, a diffusion layer serving as a base region 30 is formed by ion implantation using a resist pattern as shown as a mask.
The base region 30 is electrically connected to the P + polysilicon layer 26 by selecting appropriate ion implantation conditions. Next, as shown in FIG.
Is deposited, and a sidewall 31 is formed using RIE.
Using a resist pattern as a mask as a mask, a diffusion layer to be the emitter region 32 is formed by ion implantation.

Next, as shown in FIG. 17, after a collector diffusion layer 33 is formed by patterning by lithography and ion implantation, an interlayer insulating film 34 of about 10,000 ° is formed.
Is deposited, a predetermined photolithography is performed, a contact 35 for each electrode of the bipolar transistor is opened, and a predetermined wiring 36 is formed by using a metal such as Al and W.

[0005]

The transistor manufactured by the above method has a lower parasitic capacitance and lower power consumption than a normal bipolar transistor, but has the following problems. was there. That is, since the emitter portion is formed in the single-crystal silicon layer, the injection amount of minority carriers from the base to the emitter is large, causing deterioration of high-frequency response characteristics. Further, since the emitter portion is formed from above by ion implantation, the lower portion not formed as the emitter portion remains as a base portion as it is. Therefore, the base width is not uniform in the vertical direction, and particularly in the lower region near the oxide film 2, the base width is increased due to the base portion not formed as the emitter portion, causing deterioration of high-frequency characteristics. Was.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device which solves the above-mentioned problems and does not deteriorate high frequency response characteristics.

[0006]

The structure of the present invention comprises a first insulating film on a semiconductor substrate, a base portion provided on the first insulating film, and a first insulating film on the first insulating film. And a collector portion provided adjacent to a side surface on one side of the base portion;
A side surface on the other side of the base portion, an emitter portion provided substantially vertically adjacent to one side surface, and a first sidewall insulating film provided substantially vertically on a part of the surface of the base portion;
A second sidewall insulating film provided substantially vertically on a part of the collector surface, and a substantially perpendicularly spaced apart from the other side of the base portion on the first insulating film at a predetermined interval; A first interlayer insulating film provided, a second insulating film present in a part of an intermediate region between the first sidewall insulating film and the second sidewall insulating film, and a surface of the second insulating film A second interlayer insulating film provided substantially vertically on a part thereof, a side surface of the first interlayer insulating film, a part of a surface of the first interlayer insulating film,
A part of the surface of the second interlayer insulating film,
A side surface of the first sidewall insulating film, a part of a surface of the second insulating film,
An emitter electrode portion made of polycrystalline silicon having a constant thickness is formed on the other side surface of the emitter portion and on a part of the first insulating film.

According to the manufacturing method of the present invention, a first insulating film is formed on a semiconductor substrate of a first conductivity type, a single-crystal silicon layer is formed on the first insulating film, and Forming a second insulating film, forming a second conductivity type region using impurity ion implantation in the single crystal silicon layer, removing the second insulating film, Forming a polycrystalline silicon film on the two-conductivity type region, implanting impurities of the first conductivity type into the polycrystalline silicon film by impurity ion implantation, and forming a third insulating film on the polycrystalline silicon film. Forming a film, and removing the third insulating film, leaving only the region where the emitter portion is to be formed, the region where the base portion is to be formed, and the region where the collector portion is to be formed in the second conductivity type region. And a fourth step on a part of the surface of the nitride film. A step of forming an insulating film, a step of removing the polycrystalline silicon film and the second conductivity type region located other than below the third insulating film, and a step of removing the polycrystalline silicon film other than below the fourth insulating film. Removing the third insulating film, the polycrystalline silicon film, and the upper portion of the second conductivity type region; and removing the second conductive type region, the third insulating film, the polycrystalline silicon film, the fourth Forming a fifth insulating film on the exposed surface of the insulating film, and selectively forming a base region in the second conductivity type region by implanting impurity ions of the first conductivity type; Within the two conductivity type region,
Selectively ion-implanting impurities of the second conductivity type to form a collector region, removing the fifth insulating film, exposing the side surface of the third insulating film, the polycrystalline silicon film Forming a sixth insulating film on a side surface, the fourth insulating film side surface, a part on the base region, and a part on the second conductivity type region; Forming an interlayer insulating film on the second conductivity type region, the fourth insulating film, the base region, the collector region, and the sixth insulating film; and a selective removal method. Thereby, the interlayer insulating film is removed according to the region where the opening is to be formed, and a part of the fourth insulating film, a part of the sixth insulating film, a side surface of the interlayer insulating film, and a part of the base region are exposed. Through the step of forming the opening and the selective removal method. Removing the emitter region to be formed in the base region so that the side surface of the base region can be formed substantially vertically; and implanting a second conductivity type impurity into the emitter region and the opening. Injected
Forming an emitter electrode of a constant thickness made of polycrystalline silicon, and simultaneously forming a part of the base region adjacent to the emitter electrode as an emitter region.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, as shown in FIG. 2, an SO film comprising a silicon substrate 1, an oxide film 2, and a single-crystal silicon layer 3 is formed.
An oxide film 4 is formed on the I substrate by thermal oxidation. Thereafter, N-type impurity ions are implanted into the single crystal silicon layer 3 to form an N-type collector region 5. Next, FIG.
As shown in FIG. 5, after the oxide film 4 on the surface is peeled off using an HF-based solution, a polysilicon layer 6 having a thickness of about 500 ° is deposited by LPCVD, and a P-type impurity is doped by ion implantation. Is deposited.
Next, as shown in FIG. 4, after processing the nitride film 7 into a predetermined shape using lithography patterning and RIE etching, about 20 nm is formed by LPCVD.
An oxide film 8 of 00 ° is deposited. Subsequently, the oxide film 8 is processed into a predetermined shape using lithography patterning and RIE. This oxide film etching is performed under the condition that the nitride film and the silicon layer are hardly etched. Next, as shown in FIG. 5, using nitride film 7 as a mask, RI
By E, the polysilicon layer 6 and the N-type collector region 5 are sequentially etched. Next, as shown in FIG.
Using E, the nitride film 7 is removed by etching. At this time,
The regions of the oxide film 8 and the oxide film 2 which are exposed on the surface are also somewhat etched.

After that, the nitride film 7 is continuously formed by using RIE.
Is used as a mask, the region exposed on the surface of the polysilicon layer 6 and the N-type collector region 5 is replaced with the N-type collector region 5.
Etch halfway. Next, as shown in FIG.
After depositing an oxide film 9 of about 200 ° on the surface of the substrate, a base region 10 is formed by ion implantation using a resist pattern as shown as a mask. Further, Ge is ion-implanted, and a thermal process is performed to form a base region 1.
0 is converted to SiGe. Next, as shown in FIG. 8, an N-type impurity is ion-implanted to form a collector region 11, a nitride film of about 1000 ° is deposited, and a side wall 12 is formed around the base electrode using RIE. I do. Because of this,
The oxide film 9 other than the lower part of the side wall is removed. Further, the oxide film 1
3 and patterning by lithography and RIE
Then, an opening is formed in a predetermined shape by using, and the N-type collector region 5 in the exposed region is substantially vertically etched and removed by using SiRIE. Next, as shown in FIG. 9, a polysilicon layer of about 2000 ° is deposited by LPCVD or the like on the region where the N-type collector region 5 has been substantially removed by etching and on the opening.

After that, an N-type impurity such as As or P is ion-implanted, and a thermal process is performed to form N + -type polysilicon.
4 is assumed. At this time, the N-type impurity is slightly
And becomes the emitter region 15. As a result, the boundary between the base region 10 and the emitter region 15 becomes substantially vertical. Therefore, the base region 10 having a stable shape can be formed. Next, as shown in FIG. 1, an interlayer insulating film 16 of about 10000 ° is deposited, and predetermined photolithography is performed to open contact holes for each electrode of the bipolar transistor (a base contact hole is not shown). ,
A predetermined wiring 17 is formed using a metal such as Al and W. As described in detail above, in the present invention, when forming the emitter section, the polysilicon layer is formed after the base portion is etched substantially vertically. Accordingly, the uniformity of the base width in the depth direction is improved, and the variation in the base width is reduced between the upper portion and the lower portion of the base region, thereby improving the response characteristics. In addition, Ge is ion-implanted and a thermal process is applied to make the base region 10
Convert to iGe. As a result, the energy gap of the valence band increases at the boundary between the emitter and the base.

Therefore, the amount of diffusion of minority carriers from the base into the emitter is reduced, and the response characteristics can be improved.

[0012]

As described above in detail, in the present invention, when forming the emitter portion, the polysilicon layer is formed after the base portion is etched substantially vertically. Accordingly, the uniformity of the base width in the depth direction is improved, and the variation in the base width is reduced between the upper portion and the lower portion of the base region, thereby improving the response characteristics. Also,
Ge is ion-implanted and a thermal process is applied to convert the base region 10 into SiGe. As a result, the energy gap of the valence band increases at the boundary between the emitter and the base.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a completed view of a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2 is a cross-sectional view illustrating one step of a method of manufacturing a semiconductor device according to an embodiment.

FIG. 3 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an example.

FIG. 4 is a cross-sectional view showing one step of a method of manufacturing a semiconductor device according to an example.

FIG. 5 is a cross-sectional view showing a step of the method for manufacturing a semiconductor device according to the example.

FIG. 6 is a cross-sectional view showing a step of the method for manufacturing a semiconductor device of the example.

FIG. 7 is a cross-sectional view showing a step of the method for manufacturing a semiconductor device according to the example.

FIG. 8 is a cross-sectional view showing a step of the method for manufacturing a semiconductor device according to the example.

FIG. 9 is a cross-sectional view showing a step of the method for manufacturing a semiconductor device according to the example.

FIG. 10 is a cross-sectional view showing one process of a method of manufacturing a conventional semiconductor device.

FIG. 11 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device.

FIG. 12 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device.

FIG. 13 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device.

FIG. 14 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device.

FIG. 15 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device of a conventional example.

FIG. 16 is a cross-sectional view showing one step of a method of manufacturing a conventional semiconductor device.

FIG. 17 is a cross-sectional view showing a completed view of a method of manufacturing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Oxide film 3 Single crystal silicon layer 4 Oxide film 5 N type collector region 6 Polysilicon layer 7 Nitride film 8 Oxide film 9 Oxide film 10 Base region 11 Collector region 12 Side wall 14 Emitter polysilicon electrode 15 Emitter region 16 Interlayer insulating film 17 Wiring

Claims (4)

[Claims] A first insulating film is formed on a semiconductor substrate of a first conductivity type, a single-crystal silicon layer is formed on the first insulating film, and a second crystal film is formed on the single-crystal silicon layer. A step of forming an insulating film; a step of forming a second conductivity type region using impurity ion implantation in the single crystal silicon layer; a step of removing the second insulating film; Forming a polycrystalline silicon film, implanting a first conductivity type impurity into the polycrystalline silicon film by impurity ion implantation, and forming a third insulating film on the polycrystalline silicon film. Removing the third insulating film while leaving only the region where the emitter portion is to be formed, the region where the base portion is to be formed, and the region where the collector portion is to be formed in the second conductivity type region; Form a fourth insulating film on part of the film surface Removing the polycrystalline silicon film and the second conductivity type region located other than below the third insulating film; and removing the third conductive film region located below the fourth insulating film. Removing the insulating film, the polycrystalline silicon film, and the upper portion of the second conductivity type region; and removing the second conductive type region, the third insulating film, the polycrystalline silicon film, and the fourth insulating film. A step of forming a fifth insulating film on the exposed surface; a step of selectively forming a base region in the second conductivity type region by implanting impurity ions of a first conductivity type; the second conductivity type region Forming a collector region by selectively ion-implanting impurities of the second conductivity type therein; removing the fifth insulating film; exposing the side surface of the third insulating film; Side surface of the crystalline silicon film, the side surface of the fourth insulating film, the base region Forming the sixth insulating film on a part of the region, on a part of the second conductivity type region, and on the first insulating film, on the second conductivity type region, on the fourth conductivity type region. On an insulating film, on the base region, on the collector region,
Forming an interlayer insulating film on the sixth insulating film, and removing the interlayer insulating film according to a region where an opening is to be formed by a selective removal method, and forming a part of the fourth insulating film. Forming an opening exposing a part of the sixth insulating film, a side surface of the interlayer insulating film, and a part of the base region; Removing a region where the emitter section is to be formed so that the side surface of the base region can be formed substantially perpendicularly; and implanting a second conductivity type impurity into the opening where the emitter section is to be formed and the opening. Forming an emitter electrode having a constant thickness, and simultaneously forming a part of the base region adjacent to the emitter electrode as an emitter region. 2. The semiconductor device according to claim 1, further comprising a step of implanting Ge into said base region to form a Ge base region. 3. A first insulating film on a semiconductor substrate, a base portion provided on the first insulating film, and a side surface on the first insulating film and on one side surface of the base portion. A collector portion, a side surface on the other side of the base portion, an emitter portion provided substantially vertically adjacent on one side surface, and a portion provided substantially vertically on a surface of the base portion. A first sidewall insulating film, a second sidewall insulating film provided substantially vertically on a part of the surface of the collector portion, and a second sidewall insulating film on the first insulating film with respect to the other side of the base portion. A first interlayer insulating film provided substantially vertically at a constant interval; a second insulating film existing in a part of an intermediate region between the first side wall insulating film and the second side wall insulating film A second interlayer insulating film provided substantially vertically on a part of the surface of the second insulating film; Side surface of the interlayer insulating film, part of the surface of the first interlayer insulating film, side surface of the second interlayer insulating film, part of the surface of the second interlayer insulating film, the side surface of the first sidewall insulating film, the second A part of the surface of the insulating film, the other side surface of the emitter part, and an emitter electrode part made of polycrystalline silicon having a constant thickness and formed on a part of the first insulating film. Semiconductor device. 4. The semiconductor device according to claim 3, wherein Ge is implanted into said base portion.