JP2001117528A - Picture display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture display device capable of obtaining a state in which an error diffusion processing by an error diffusion processing circuit is not applied to a video signal by a very simple method without increasing the circuit scale. SOLUTION: An inverse gamma correcting circuit 2 has two inverse gamma correction characteristics optimum in a case that a processing for making the video signal to be multilevels is applied to the signal and in a case that the processing is not applied to the signal and subjects inputted R, G, B signals to an inverse gamma correction processing. Then, the inverse gamma correction characteristics of the circuit 2 are changed over according as the processing for making the video signal to be multilevels is to be applied to the signal by an error diffusion processing circuit 3 or not. When the processing for making the video signal to be multilevels is not applied to the signal, the circuit 3 is made to be substantially in-operative by making lower bits to be used in error diffusion all zero before the video signal is inputted to the circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an error diffusion method such as a plasma display panel display (PDP), a field emission display (FED), a digital micromirror device (DMD), and an electroluminescence display (EL). The present invention relates to an image display device that increases the number of visual gradations by performing a multi-gradation process using the same.

[0002]

2. Description of the Related Art Among image display devices for displaying video signals,
For example, in a PDP for displaying gradation by dividing one field into a plurality of subfields, an FED for displaying gradation by pulse width modulation (PWM), and a matrix type display device such as DMD, depending on the driving method, digital display is required. An image can be expressed only with a limited number of gradations.

In television broadcasting or the like in which a cathode ray tube (CRT) is usually used as a receiver, a gamma characteristic is given in advance on the transmitter side, and the inverse gamma characteristic of the CRT on the receiver side is used in advance. A linear gradation characteristic is set. However, in such a display device that displays an image with a digitally limited number of tones, the CRT
Unlike this, the display device itself has a linear gradation characteristic.
Therefore, in order to display an image with a gradation characteristic similar to that of a display device using a CRT that is commonly used, a 2.2-power inverse gamma correction process is performed on the input video signal of the display device to return to a linear gradation characteristic. It is necessary to display images.

On the other hand, in these display devices, the number of gradations (bit number) of the input signal may be larger than the number of gradations (bit number) that can be expressed by the display device. In some cases, the number of tones (bits) expressed by the display device is intentionally reduced from the number of tones (bits) of the input signal.

Further, when the inverse gamma correction is performed by the inverse gamma correction circuit to return to a linear gradation, the number of bits may be once higher than the number of bits that can be expressed by the display device. This is for the following reasons. When the inverse gamma correction process is performed to return to a linear gradation, the number of gradations at a low luminance level may be damaged, and image quality may often be disturbed due to loss of gradation continuity. In particular, PDP
In the case of (1), one field is composed of a plurality of subfields having different weights of the light emission amount, and the gradation is expressed by selecting a plurality of the subfields. Therefore, depending on the selection condition of the subfield, the visual luminance difference with respect to the adjacent gray scale becomes large, and as a result, a pseudo contour-like image quality disturbance may occur. Therefore,
In order to prevent the gradation from being impaired as much as possible, inverse gamma correction may be performed with a bit number higher than the bit number of the original signal, and the bit number may be increased for output.

As described above, the number of bits of the input video signal or the number of bits of the video signal output from the inverse gamma correction circuit (the first number of gray scales) corresponds to the number of bits expressed by the display device (the second number of gray levels). If it is larger than the number of gradations, the number of bits (the number of gradations) needs to be reduced.
If the number of bits is reduced, the gradation is impaired, so that the multi-gradation processing is performed by using the error diffusion method.

FIG. 6 is a block diagram showing an example of the configuration of an image display device provided with an inverse gamma correction circuit and an error diffusion processing circuit. Here, an image is expressed only with digitally limited gradations. The case where a PDP is used as a matrix type display device which cannot perform the operation is shown. FIG.
, Three video signals composed of R, G, and B signals are input to the video signal processing circuit 1. The video signal processing circuit 1 performs various video signal processes on these video signals and inputs the processed video signals to the inverse gamma correction circuit 2. The R, G, and B signals are 8-bit digital signals, for example, signals of 256 gradations.

The reverse gamma correction circuit 2 is composed of a reverse gamma correction circuit 2R for R, a reverse gamma correction circuit 2G for G, and a reverse gamma correction circuit 2B for B, and the R, G, and B signals are supplied to the respective reverse gamma correction circuits. Input to 2R, 2G, 2B. The inverse gamma correction circuits 2R, 2G, and 2B receive the input R, G,
An inverse gamma correction process is performed on each of the B signals, and as an example, a 12-bit digital signal, that is, a signal of 4096 gradations is output. At this time, the inverse gamma correction processing for the R, G, and B signals may have the same characteristics or different characteristics. The output of the 8-bit digital signal as a 12-bit digital signal is to prevent the number of gradations from being impaired by the inverse gamma correction processing as described above.

[0009] The R, G, B signals output from the inverse gamma correction circuits 2 R, 2 G, 2 B are input to an error diffusion processing circuit 3. The error diffusion processing circuit 3 includes an R error diffusion processing circuit 3R, a G error diffusion processing circuit 3G, a B error diffusion processing circuit 3B, an R delay circuit 5R, a G delay circuit 5G, and a B delay circuit 5B. Is done. Inverse gamma correction circuits 2R, 2
The R, G, and B signals output from G, 2B are respectively transmitted to error diffusion processing circuits 3R, 3G, 3B and delay circuits 5R, 5R.
G, 5B. Error diffusion processing circuits 3R, 3G,
A switching signal is input to 3B and the delay circuits 5R, 5G, and 5B. This switching signal is sent to the error diffusion processing circuits 3R, 3R.
This is for switching whether or not to perform error diffusion processing in G and 3B. When the error diffusion processing is performed, the outputs of the error diffusion processing circuits 3R, 3G, and 3B are enabled. When the error diffusion processing is not performed, the delay circuits 5R, 5G,
Enable 5B output.

The reason why the error diffusion processing circuits 3R, 3G, and 3B switch between performing and not performing error diffusion processing is as follows. When the image display device is used as a display monitor of a personal computer (PC) or used for displaying images such as fixed patterns,
Performing the error diffusion processing may cause image quality disturbance such as periodic pattern noise peculiar to the error diffusion processing, and may significantly impair the image quality. Therefore, when a personal computer signal, a fixed pattern, or the like is displayed on the PDP 4, an image may be displayed without performing error diffusion processing.

Therefore, when the error diffusion processing is performed, the outputs of the error diffusion processing circuits 3R, 3G, 3B are input to the PDP 4, and when the error diffusion processing is not performed, the delay circuit 5
The outputs of R, 5G, and 5B are input to PDP4. When the error diffusion processing is not performed, the inverse gamma correction circuits 2R, 2G,
The R, G, B signals output from 2B are delayed by delay circuits 5R, 5R.
The reason for delaying by G and 5B is to delay the R, G and B signals by the delay when the error diffusion processing is performed by inputting the R, G and B signals to the error diffusion processing circuits 3R, 3G and 3B. That is, the R, G, and B signals are converted into error diffusion processing circuits 3R, 3G,
The R, G, B signals are the same for the PDP 4 regardless of whether the signal is input to the PDP 4 via the 3D or the PDP 4 without passing through the error diffusion processing circuits 3R, 3G, 3B (through). It is for supplying at a timing. Note that the delay circuits 5R, 5G, and 5B may be provided outside the error diffusion processing circuit 3 instead of inside the error diffusion processing circuit 3.

The operation of the error diffusion processing circuits 3R, 3G, 3B will be described. Error diffusion processing circuits 3R, 3G, 3B
Performs error diffusion processing on each of the R, G, and B signals output from the inverse gamma correction circuits 2R, 2G, and 2B, and outputs the resulting signals. The multi-gradation processing by the error diffusion method is performed as follows as an example in order to obtain an image corresponding to the first number of gradations exceeding the digitally limited second number of gradations. In FIG. 7, P is one of the three dots constituting the target pixel, and is a dot having a gradation that cannot be expressed as it is with the second number of gradations. A is a dot on the right, B is a dot on the lower left, C is a dot on the lower right, and D is a dot on the lower right. As shown in FIG. 7, the difference between the first number of gradations and the second number of gradations that cannot be expressed in the target dot P (the first number of gradations−the second number of gradations) is set to a plurality of values. By multiplying the peripheral dots A to D with a certain weight and diffusing them, a multi-gradation process is performed so that the image becomes apparently equivalent to the first number of gradations.

For example, when the PDP 4 has only 8-bit gradation capability and performs gradation display using the upper 8 bits of the 12-bit dot data, the remaining lower 4 bits of dot data are weighted with a certain weight. By diffusing into the peripheral dots A to D, a gradation display equivalent to 12 bits is performed using a visual integration effect. In FIG. 7, 7/16, 3/16, 5/16, 1/1 added to the peripheral dots A to D.
6 is an example of an error diffusion coefficient indicating the degree of weighting. Note that a common error diffusion coefficient is used for the three primary color signals of R, G, and B.

As described above, the error diffusion processing circuit 3
R, G, B subjected to error diffusion processing by R, 3G, 3B
The signals or the R, G, B signals delayed by the delay circuits 5R, 5G, 5B without error diffusion processing are
Input to PDP4. The PDP 4 performs driving circuit processing such as subfield processing, and then displays R, G, B on the screen.
Display signals as images.

[0015]

In the conventional image display apparatus described above, the delay circuit 5R, 5R,
5G and 5B must be provided as separate circuits from the error diffusion processing circuits 3R, 3G and 3B, and there is a problem that the circuit scale is increased. Delay circuits 5R, 5G, 5
The circuit scale of B becomes larger as the circuit scales of the error diffusion processing circuits 3R, 3G, and 3B become larger, which is a major problem when trying to provide a smaller circuit scale, and improvement has been desired.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in an image display device having an error diffusion processing circuit, the error caused by the error diffusion processing circuit can be extremely simply increased without increasing the circuit scale. It is an object of the present invention to provide an image display device capable of obtaining a state in which diffusion processing is not performed.

[0017]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention provides: (a) a video signal having a first number of bits having a smaller number of bits than the first number of bits; In reducing the number of bits to the second number of bits, a lower bit of the first number of bits, which is a difference between the first number of bits and the second number of bits in each target pixel, is multiplied by a predetermined error diffusion coefficient. The image signal is input to the error diffusion processing circuit in an image display device including an error diffusion processing circuit (3) for performing multi-gradation processing by diffusing the error data to a plurality of peripheral pixels of the target pixel. A means (23) for making the error diffusion processing circuit substantially inoperable by previously setting all the lower bits of the video signal to 0 before performing the operation. Offer to (B) a second smaller number of bits than the number of the first bit of the video signal having a first number of bits
When reducing to the number of bits, an error obtained by multiplying a lower-order bit of the first number of bits, which is a difference between the first number of bits and the second number of bits in each target pixel, by a predetermined error diffusion coefficient. Error detection circuit for generating data (3
3) an image display device comprising: an error diffusion processing circuit (3) for performing a multi-gradation process by diffusing the error data to a plurality of peripheral pixels of the target pixel. Means for forcibly generating the error data as 0 irrespective of the state of the lower bits of the video signal, thereby providing means for substantially disabling the error diffusion processing circuit. (C) an inverse gamma correction circuit (2) that performs an inverse gamma correction process on an input video signal and outputs a video signal having a first number of bits; In reducing the video signal output from the gamma correction circuit to a second bit number smaller in bit number than the first bit number, the first bit number in each pixel of interest and the second bit number An error in which multi-gradation processing is performed by diffusing error data obtained by multiplying a lower-order bit of the first number of bits, which is a difference from the number of bits, by a predetermined error diffusion coefficient to a plurality of peripheral pixels of the target pixel. In an image display device provided with a diffusion processing circuit (3), first switching means (23) for switching whether or not to perform multi-gradation processing by the error diffusion processing circuit; A second switching means (23) for switching an inverse gamma correction characteristic in the inverse gamma correction circuit between a first state in which the gradation processing is performed and a second state in which the multiple gradation processing is not performed; The first switching unit sets all the lower bits of the video signal output from the inverse gamma correction circuit and input to the error diffusion processing circuit to 0, thereby substantially disabling the error diffusion processing circuit. Let it work To provide an image display device characterized by obtaining said second state,
(D) an inverse gamma correction circuit (2) for performing an inverse gamma correction process on the input video signal to output a video signal having a first bit number, and converting the video signal output from the inverse gamma correction circuit into In reducing the number of bits to a second number of bits smaller than the first number of bits, the first number of bits which is a difference between the first number of bits and the second number of bits in each pixel of interest And an error detection circuit (33) for generating error data obtained by multiplying the lower bits of the pixel by a predetermined error diffusion coefficient, and performing the multi-gradation processing by diffusing the error data to a plurality of peripheral pixels of the target pixel An image display apparatus comprising: an error diffusion processing circuit for performing a multi-gradation process by the error diffusion processing circuit; By A second state in which the reverse gamma correction characteristic of the reverse gamma correction circuit is switched between a first state in which the multiple gradation processing is performed and a second state in which the multiple gradation processing is not performed.
Switching means (23), wherein the first switching means comprises:
The error detection circuit is provided with means for forcibly generating the error data as 0 regardless of the state of the lower bit of the video signal, thereby making the error diffusion processing circuit substantially inoperative and It is an object of the present invention to provide an image display device characterized by obtaining a second state.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image display device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the image display apparatus of the present invention, FIG. 2 is a block diagram showing a specific configuration example of the inverse gamma correction circuit 2 in FIG. 1, and FIG. 3 is an inverse gamma correction in FIG. FIG. 4 is a characteristic diagram for explaining the inverse gamma correction characteristic of the circuit 2, FIG. 4 is a block diagram showing a specific configuration example of the error diffusion processing circuit 3 in FIG. 1, and FIG. 5 is an error diffusion processing circuit 3 in FIG. FIG. 9 is a diagram for explaining an operation of an error diffusion process according to FIG.

In this embodiment shown in FIG. 1, a case is shown in which a PDP is used as a matrix type display device capable of expressing an image only with a digitally limited number of gradations. Of course, as the display device of the present invention, a PD
It is not limited to P. In FIG. 1, R, G,
The three-system video signal composed of the B signal is input to the video signal processing circuit 1. The video signal processing circuit 1 performs various video signal processing on these video signals, and performs an inverse gamma correction circuit 2
To enter. The R, G, and B signals are 8-bit digital signals, for example, signals of 256 gradations.

The reverse gamma correction circuit 2 is composed of a reverse gamma correction circuit 2R for R, a reverse gamma correction circuit 2G for G, and a reverse gamma correction circuit 2B for B, and the R, G, and B signals are supplied to the respective reverse gamma correction circuits. Input to 2R, 2G, 2B. The inverse gamma correction circuits 2R, 2G, and 2B receive the input R, G,
An inverse gamma correction process is performed on each of the B signals, and as an example, a 12-bit digital signal, that is, a signal of 4096 gradations is output. At this time, the inverse gamma correction processing for the R, G, and B signals may have the same characteristics or different characteristics. The output of the 8-bit digital signal as a 12-bit digital signal is to prevent the number of gradations from being impaired by the inverse gamma correction processing as described above.

The R, G, B signals output from the inverse gamma correction circuits 2R, 2G, 2B are input to the error diffusion processing circuit 3. The error diffusion processing circuit 3 includes an error diffusion processing circuit 3R for R, an error diffusion processing circuit 3G for G, and an error diffusion processing circuit 3B for B, and the R, G, and B signals are respectively processed by the error diffusion processing circuits 3R, 3G. , 3B. The error diffusion processing circuits 3R, 3G, and 3B perform error diffusion processing on the input R, G, and B signals, and output the signals. That is, for example, the lower 4 bits of the 12-bit digital signal are weighted with a certain weight and then spread to the upper 8 bits.
Output as an 8-bit digital signal.

A switching signal is input to the inverse gamma correction circuits 2R, 2G, 2B. This switching signal is used to switch whether or not to perform error diffusion processing in the error diffusion processing circuits 3R, 3G, 3B, and to determine whether or not to perform error diffusion processing in the inverse gamma correction circuits 2R, 2G, 2B. This is for making the characteristics of the inverse gamma correction process different depending on whether or not it is determined. In the present invention, as will be described later, the error diffusion processing circuit 3 is substantially provided by devising the inverse gamma correction processing in the inverse gamma correction circuits 2R, 2G, and 2B.
A state in which R, 3G, and 3B do not operate can be selected. Error diffusion processing circuits 3R, 3G, 3
When the error diffusion processing is not performed by controlling B itself, the switching signal is also input to the error diffusion processing circuits 3R, 3G, and 3B as shown by the broken lines.

The R, G, B signals subjected to the error diffusion processing by the error diffusion processing circuits 3R, 3G, 3B, or the error diffusion processing circuits 3R, 3G,
The R, G, B signals that have passed through 3B are input to PDP4. The PDP 4 displays an R, G, B signal on a screen after performing drive circuit processing such as subfield processing.

Here, the inverse gamma correction circuit 2 will be described with reference to FIG.
Is described below. Inverse gamma correction circuit 2
R, 2G, and 2B all have the same configuration. In FIG. 2, for convenience, the input / output signals are R, G, and B signals, but this means that any one of the R, G, and B signals is input and output. 2, the 8-bit R, G, and B signals output from the video signal processing circuit 1 are input to inverse gamma correction units 21 and 22. The inverse gamma correction sections 21 and 22 are sections that actually perform inverse gamma correction on the R, G, and B signals and output the signals, and are configured by a ROM having an inverse gamma conversion table or a microcomputer that executes software processing.

The inverse gamma correction unit 21 generates an 8-bit R,
The G and B signals are inversely gamma-corrected by 12 bits to output 12-bit R, G and B signals. The R, G, and B signals are input to the terminal a of the selector 23. Inverse gamma correction unit 22
Outputs 8-bit R, G, and B signals by performing inverse gamma correction on the 8-bit R, G, and B signals with 8 bits. To the 8-bit R, G, and B signals, 4 bits, all of which are set to 0, are added as lower bits to form 12-bit R, G, and B signals. The R, G, and B signals are input to the terminal b of the selector 23. The inverse gamma correction unit 21 performs inverse gamma correction with optimal characteristics when performing error diffusion processing by the error diffusion processing circuit 3.
Is for performing inverse gamma correction with optimal characteristics when error diffusion processing is not performed by the error diffusion processing circuit 3.

The characteristics of the inverse gamma correction by the inverse gamma correction unit 21 and the characteristics of the inverse gamma correction by the inverse gamma correction unit 22 are different as follows. FIG. 3 shows the inverse gamma correction unit 2
Inverted gamma correction characteristics in 1 and 22 are shown, where the horizontal axis V is the input gray scale and the vertical axis L is the output gray scale. In FIG. 3, the characteristic is an optimal characteristic when the error diffusion processing is performed by the error diffusion processing circuit 3, that is, the inverse gamma correction unit 21.
Is the characteristic to be set. The characteristic is the error diffusion processing circuit 3
This is an optimal characteristic when no error diffusion processing is performed, that is, a characteristic set in the inverse gamma correction unit 22.

Comparing the characteristics with each other, at least in the low gradation region Vlow from gradation 0 (black level) to a predetermined gradation, the characteristic shows that the change ratio of the output gradation with respect to the input gradation is higher. I am large. Here, the characteristics,
Is shown as a simple parabola, but the curve of the inverse gamma correction characteristic is approximated by a straight line from gradation 0 (black level) to a predetermined gradation, and a parabolic curve is continuously formed on the straight line. May be connected. In such a case, the rate of change of the low gradation area Vlow can be said to be the slope from gradation 0 to the inflection point between the straight line and the parabolic curve.

With this setting, when displaying an image without performing the error diffusion process, the number of gradations is not significantly impaired in the low gradation area Vlow, so that the digital bit whose gradation continuity is significantly impaired is reduced. It is possible to realize high-quality image display regardless of whether error diffusion processing is performed or not, without causing an image like a drop.
On the other hand, it is useless in terms of circuit performance to make the characteristics even when the error diffusion processing is performed. From these points, the inverse gamma correction circuits 2R, 2G, and 2B are used depending on whether the error diffusion processing is performed by the error diffusion processing circuits 3R, 3G, and 3B.
Differentiating the characteristics of the inverse gamma correction processing in B has a very important meaning.

Returning to FIG. 2 again, the selector 23 receives the above switching signal. When the switching signal is, for example, 1 indicating that the switching signal is subjected to the error diffusion process, the selector 23
Is selected to indicate that no error diffusion processing is performed, for example, 0
, Terminal b is selected. The case where error diffusion processing is performed is a case where a normal video signal (television signal or the like) is displayed, and the case where error diffusion processing is not performed is a case where a personal computer signal or a fixed pattern is displayed. The R, G, and B signals output from the selector 23 are input to the subsequent error diffusion processing circuits 3R, 3G, and 3B, respectively.
The selector 23 operates as switching means for switching the inverse gamma correction characteristics in the inverse gamma correction circuits 2R, 2G, 2B depending on whether or not to perform the error diffusion process.

Next, a specific configuration of the error diffusion processing circuit 3 will be described with reference to FIG. Error diffusion processing circuit 3R,
3G and 3B have the same configuration. Also in FIG. 4, for convenience, the input / output signals are R, G, and B signals, but this means that any one of the R, G, and B signals is input / output.

In FIG. 4, the inverse gamma correction circuits 2R, 2R
The 12-bit R, G, and B signals input from G and 2B are output through adders 31 and 32, which will be described later, and the lower 4 bits of the 12-bit data output from the adder 32 are subjected to error detection. Input to the circuit 33. The lower 4 bits are used to convert a 12-bit digital signal (4096 gradations) into 8 bits.
This is equivalent to a difference in gradation lost by reducing the number of bits to a digital signal (256 gradations). The error detection circuit 33 generates error data by multiplying the input lower 4-bit data by an error diffusion coefficient corresponding to the peripheral dots A 'to D' shown in FIG.

From the terminals a to d shown in the error detecting circuit 33, the lower 4 bits of data are respectively added to the peripheral dots A '.
Error data multiplied by an error diffusion coefficient corresponding to .about.D 'is output. In the case of FIG. 5A, the lower 4 bits of data are respectively transmitted from terminals a to d.
Error data multiplied by / 16, 3/16, 5/16, 1/16 is output. Peripheral dots A′〜 shown in FIG.
The relationship between D 'and the peripheral dots A to D shown in FIG. 5B will be described later.

The error data output from the terminal a is input to the adder 32, the error data output from the terminal b is input to the adder 35, and the error data output from the terminals c and d are input to the adder 34. Is entered. The adder 34 adds the input error data from the terminals c and d and inputs the result to the adder 35. The adder 35 adds the error data output from the terminal b and the output of the adder 34 and inputs the result to the line memory 36. The line memory 36 inputs the output of the adder 35 to the adder 31 with a delay slightly shorter than one line.

The adder 31 adds the input R, G, B signals and the output of the line memory 36 and inputs the result to the adder 32. Assuming that the input R, G, and B signals are target dots P 'shown in FIG. 5A, the adder 31 provides a line memory, which is error data generated by approximately one line in the past with respect to the target dot P'. 36, ie, B '× 3/16 +
An operation of adding C ′ × 5/16 + D ′ × 1/16 is performed.

The adder 32 adds the output of the adder 31 and the error data output from the terminal a of the error detection circuit 33. That is, the adder 32 adds the error data generated substantially one line in the past to the target dot P ′.
An operation of adding A ′ × 7/16, which is error data generated one dot in the past, to the output of “1” is further performed. As described above, the error data obtained by multiplying the peripheral dots A 'to D' by the respective error diffusion coefficients are added to the target dot P 'shown in FIG. Of the 12-bit data output from the adder 32, the lower 4 bits are further input to the error detection circuit 33, and the above operation is repeated.

The upper 8 bits of the 12-bit data output from the adder 32 are input to the limiter 37. The limiter 37 restricts and outputs an amount (overflow) where the value of the data obtained by adding the error data to the target dot P ′ exceeds 8 bits.

As described above, the sequential addition of the error data to the target dot P 'is performed for each dot. As a result, as shown in FIG. 7/16, 3/16, 5 /
The peripheral dot A is multiplied by an error diffusion coefficient of 16, 1/16.
~ D. In this manner, the error diffusion processing circuits 3R, 3G, and 3B output the R, G, and B signals
At the pixel of interest composed of three dots, the R, G, and B signals are subjected to error diffusion processing to output 12-bit data as 8-bit data.

In such a configuration and operation, when the selector 23 shown in FIG. 2 selects the output of the inverse gamma correction unit 22, the 12-bit R, R, G, and B input to the error diffusion processing circuits 3R, 3G, and 3B. Since the lower 4 bits of the G and B signals are all 0, it can be seen that the error data output from the error detection circuit 33 is 0. That is,
This corresponds to the fact that the error diffusion processing circuits 3R, 3G, 3B have become substantially inoperative.

In this embodiment, the inverse gamma correction circuits 2R, 2R
The inverse gamma correction unit 22 constituting G and 2B is subjected to inverse gamma correction using 8 bits, and the lower 4 bits of all 0s are added to the output to generate a 12-bit signal. By making a selection, a state is created in which error diffusion processing is not performed by the error diffusion processing circuits 3R, 3G, and 3B. Therefore, in the case of the present embodiment, when the selector 23 selects the output of the inverse gamma correction unit 21, the error diffusion processing circuits 3 R, 3 G, and 3 B operate and the output of the inverse gamma correction unit 22 is selected. Since the error diffusion processing circuits 3R, 3G, and 3B do not operate, the selector 23 selects the error diffusion processing circuits 3R, 3G, and 3B.
It can be seen that B also operates as switching means for switching whether or not to perform error diffusion processing.

As described above, in this embodiment, the selector 23
Is a first method for switching whether or not to perform error diffusion processing (multi-gradation processing) by the error diffusion processing circuits 3R, 3G, and 3B.
Switching means. The selector 23 has a first state in which error diffusion processing (multi-tone processing) is performed by the error diffusion processing circuits 3R, 3G, and 3B and a second state in which error diffusion processing (multi-tone processing) is not performed. These are the second switching means for switching the inverse gamma correction characteristics in the inverse gamma correction circuits 2R, 2G, 2B. That is, the selector 2
Reference numeral 3 serves as both the first switching means and the second switching means. Of course, it is also possible to provide the first switching means and the second switching means separately.

In the example shown in FIG. 2, the inverse gamma correction section 22 performs inverse gamma correction using 8 bits, and the output thereof is added with the lower 4 bits of all 0s to generate a 12-bit signal. It is not something to be done. Inverse gamma correction unit 2
2 may be a 12-bit inverse gamma correction similarly to the inverse gamma correction unit 21, and the lower 4 bits may be switched to 0 in the inverse gamma correction unit 22 or another circuit part. In any case, the error diffusion processing circuit 3R,
Setting the lower 4 bits of the 12 bits to 0 at the stage of inputting to the 3G and 3B means that the error diffusion processing circuits 3R and 3B
This is an extremely simple means for disabling G and 3B.

As another configuration, the lower 4 bits of the 12-bit signal output from the inverse gamma correction unit 22 may be input to the error diffusion processing circuits 3R, 3G, and 3B without being set to 0. In this case, as shown by the broken line in FIG. 4, the above-mentioned switching signal is input to the error detection circuit 33, and when the value is, for example, 0 indicating that the error diffusion processing is not performed, the error detection circuit 33 outputs the input signal (lower order). A configuration may be employed in which 0 is forcibly output regardless of the state of the bit. In this case, the means for forcibly outputting the error data 0 regardless of the state of the lower bits of the R, G, and B signals provided in the error detection circuit 33 switches whether or not to perform the error diffusion processing.
1 is the switching means.

As described above, in the present invention, the lower bits used for error diffusion in the R, G, B signals input to the error diffusion processing circuits 3R, 3G, 3B are transmitted to the error diffusion processing circuits 3R, 3G, 3B. By setting all bits to 0 before inputting, it is possible to select a state in which the error diffusion processing circuits 3R, 3G, and 3B are disabled. Alternatively, the error detection circuit 33 in the error diffusion processing circuits 3R, 3G, 3B
In addition, by providing a means for forcibly generating error data 0 irrespective of the state of the lower bit, it is possible to select a state in which the error diffusion processing circuits 3R, 3G, 3B are inoperative. Therefore, unlike the related art, it is not necessary to provide the delay circuits 5R, 5G, and 5B as separate circuits inside or outside the error diffusion processing circuit 3. Therefore, the above-mentioned conventional problems can be satisfactorily solved.

[0044]

As described above in detail, the image display apparatus according to the present invention performs error diffusion processing by setting all lower bits of the video signal to 0 before inputting the video signal to the error diffusion processing circuit. The error diffusion processing circuit can be substantially disabled by making the circuit substantially inoperable or by providing the error detection circuit with means for forcibly generating error data as 0 regardless of the state of the lower bit of the video signal. Since the configuration is such that the operation is performed, it is possible to obtain a state where the error diffusion processing by the error diffusion processing circuit is not performed by an extremely simple method without increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration example of an inverse gamma correction circuit 2 in FIG.

FIG. 3 is a characteristic diagram for explaining an inverse gamma correction characteristic included in the inverse gamma correction circuit 2 in FIG.

FIG. 4 is a block diagram illustrating a specific configuration example of an error diffusion processing circuit 3 in FIG. 1;

FIG. 5 is a diagram for explaining an operation of an error diffusion process by an error diffusion processing circuit 3 in FIG. 1;

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a diagram for explaining multi-gradation processing by an error diffusion method.

[Explanation of symbols]

 Reference Signs List 1 video signal processing circuit 2 reverse gamma correction circuit 2RR reverse gamma correction circuit 2G G reverse gamma correction circuit 2B B reverse gamma correction circuit 3 error diffusion processing circuit 3R R error diffusion processing circuit 3G G error diffusion processing circuit 3B Error diffusion processing circuit for B 4 Plasma display panel display device (PDP) 21, 22 Inverse gamma correction unit 23 Selector (switching means) 33 Error detection circuit

Claims (4)

[Claims] When reducing a video signal having a first number of bits to a second number of bits smaller than the first number of bits, the first signal in each pixel of interest is reduced.
By spreading error data obtained by multiplying a lower bit of the first bit number, which is a difference between the number of bits of the first bit number and a predetermined error diffusion coefficient, to a plurality of peripheral pixels of the pixel of interest, An image display device comprising an error diffusion processing circuit for performing a gradation process, wherein the lower bits of the video signal are all set to 0 before inputting the video signal to the error diffusion processing circuit. An image display device comprising means for substantially disabling a diffusion processing circuit. 2. A method for reducing a video signal having a first number of bits to a second number of bits having a smaller number of bits than the first number of bits, wherein the first number of pixels in each pixel of interest is reduced.
And an error detection circuit that generates error data obtained by multiplying a lower-order bit of the first number of bits, which is a difference between the number of bits of the target pixel and the second number of bits, by a predetermined error diffusion coefficient. An image display device comprising an error diffusion processing circuit for performing a multi-gradation process by diffusing the error data to peripheral pixels of the image display device, wherein the error detection circuit is forcibly irrespective of the state of the lower bit of the video signal. An image display apparatus comprising: means for generating the error data as 0; and means for substantially disabling the error diffusion processing circuit. 3. An inverse gamma correction circuit for performing an inverse gamma correction process on an input video signal to output a video signal having a first bit number, and converting the video signal output from the inverse gamma correction circuit into the video signal. In reducing the number of bits to a second number of bits smaller than the number of bits of 1, the first number of pixels in each pixel of interest
By spreading error data obtained by multiplying a lower bit of the first bit number, which is a difference between the number of bits of the first bit number and a predetermined error diffusion coefficient, to a plurality of peripheral pixels of the pixel of interest, An image display device comprising: an error diffusion processing circuit that performs a gradation process; a first switching unit that switches whether or not to perform multi-gradation processing by the error diffusion circuit; and First to perform multi-gradation processing
A second switching means for switching an inverse gamma correction characteristic of the inverse gamma correction circuit between the state of the inverse gamma correction and the second state in which the multi-gradation processing is not performed; By setting all the lower bits of the video signal output from the correction circuit and input to the error diffusion processing circuit to 0, the error diffusion processing circuit is made substantially inoperable to obtain the second state. An image display device characterized by the above-mentioned. 4. An inverse gamma correction circuit that performs an inverse gamma correction process on an input video signal to output a video signal having a first bit number, and outputs the video signal output from the inverse gamma correction circuit to the video signal. In reducing the number of bits to a second number of bits smaller than the number of bits of 1, the first number of pixels in each pixel of interest
And an error detection circuit that generates error data obtained by multiplying a lower-order bit of the first number of bits, which is a difference between the number of bits of the target pixel and the second number of bits, by a predetermined error diffusion coefficient. And an error diffusion processing circuit for performing multi-gradation processing by diffusing the error data to peripheral pixels of the image display device. A first switching unit, and a first unit for performing a multi-gradation process by the error diffusion processing circuit.
A second switching means for switching an inverse gamma correction characteristic in the inverse gamma correction circuit between the state of (b) and the second state in which the multi-gradation processing is not performed; The circuit includes means for forcibly generating the error data as 0 irrespective of the state of the lower bit of the video signal, thereby making the error diffusion processing circuit substantially inoperable and providing the second signal. An image display device for obtaining a state.