JP2001117112A - Liquid crystal panel and manufacturing method thereof - Google Patents

Abstract

(57) Abstract: Provided is a liquid crystal panel and a method for manufacturing the same, which can prevent destruction of elements and changes in characteristics due to static electricity even after a scribe process. SOLUTION: Terminals 112a and 11 connected to an external circuit.
A low resistance pad 145 made of metal is formed in a region between 2b and the edge of the substrate, and these low resistance pads 145 are electrically connected by a high resistance pad 132 made of amorphous silicon. These low resistance pads 145 and high resistance pads 132 remain on the panel even after the scribe process. Static electricity generated during handling is distributed by the low-resistance pad 145 and the high-resistance pad 132.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a liquid crystal panel having a function of preventing destruction of elements due to static electricity even after a scribe process, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, liquid crystal panels have been used not only in displays of portable computers but also in various electronic devices such as displays of desktop computers, televisions, and displays of portable terminals. A general liquid crystal panel has a structure in which liquid crystal is sealed between two transparent substrates. Of the two surfaces of the transparent substrate facing each other, a counter electrode, a color filter, an alignment film, and the like are formed on one surface side, and a TFT (Thin Film Transistor) and a pixel are formed on the other surface side. An electrode, an alignment film, and the like are formed. Also,
A polarizing plate is attached to a surface of the transparent substrate opposite to the opposite surface. These two polarizing plates are arranged, for example, so that the polarization axes are orthogonal to each other. When no voltage is applied between the pixel electrode and the counter electrode, light is transmitted and a bright display is performed, and a voltage is applied. In this state, light is shielded and dark display is performed. When the polarization axes of the two polarizing plates are arranged in parallel to each other, dark display is performed when no voltage is applied between the pixel electrode and the counter electrode, and bright display is performed when a voltage is applied. Hereinafter, the substrate on which the TFT and the pixel electrode are formed is called a TFT substrate, and the substrate on which the color filter and the counter electrode are formed is called a counter substrate.

FIG. 20 is a plan view showing a TFT substrate of a conventional liquid crystal panel. However, in FIG. 20, illustration of TFTs and pixel electrodes formed for each pixel is omitted. Also, in the figure, the one-dot chain line indicates the position of the edge of the counter substrate joined to the TFT substrate, and the two-dot chain line indicates a scribe line. On the glass substrate 50, a plurality of gate bus lines 511 and a plurality of drain bus lines 54
1 is formed. Each gate bus line 511 is arranged in parallel with each other, and each drain bus line 541
Are arranged so as to intersect the gate bus line 511 at right angles.

[0004] TAB terminals 512a and 512b for connection to an external drive control circuit are provided at the edges (in this example, the left edge and the lower edge) of the glass substrate 50.
An end of the gate bus line 511 is connected to a TAB terminal 512a, and an end of the drain bus line 541 is electrically connected to a TAB terminal 512b via a reconnection portion 563. In the region between the TAB terminals 512 a, 512 b and the edge of the glass substrate 50, common wirings 514 a, 51
4b are formed, and each TAB terminal 512a, 512b is formed.
b is the common wiring 51 via the connection wirings 513a and 513b.
4a and 514b. Reference numeral 515 in FIG. 20 denotes a common pad (terminal) connected to a counter electrode provided on the counter substrate side.

Hereinafter, a conventional method for manufacturing a liquid crystal panel will be described. First, a method for manufacturing a TFT substrate will be described. A chromium (Cr) film is formed on the glass substrate 50 by a sputtering method. Then, the chromium film is patterned by the photolithography method, and the gate bus line 511, the TAB terminals 512a and 512b, the connection wiring 51 are formed.
3a and 513b and common wirings 514a and 514b are formed.

Thereafter, a first silicon nitride film (SiNx) serving as a gate insulating film and α-S serving as an active layer of the TFT are formed on the entire upper surface of the glass substrate 50 by a plasma CVD method.
An i (amorphous silicon) film and a second silicon nitride film serving as a channel protection film are continuously formed. Next, the second silicon nitride film is selectively etched to form a TFT.
The second silicon nitride film is left only on the channel region of FIG.

Next, an n ⁺ -type α-Si film serving as an ohmic contact layer is formed on the entire upper surface of the glass substrate 50, and Ti (titanium), Al (aluminum), and Ti
Is formed. And these α-
By patterning the Si film and the conductive film, a drain bus line 541 and a source electrode and a drain electrode of the TFT are formed.

Next, a third silicon nitride film is formed as a protective film over the entire upper surface of the glass substrate 50 by a plasma CVD method. Then, a contact hole is formed at a position matching the source electrode of the third silicon nitride film and a position matching the reconnection portion 563, and an opening for exposing the TAB terminals 512a and 512b is formed. Next, ITO (indium-tin) is formed on the entire upper surface of the glass substrate 50.
oxide (indium tin oxide) film is formed and its ITO
Pattern the film to form TAB terminals 512a, 512b.
An ITO cover film (not shown) covering the top, a reconnection portion 563, and a pixel electrode are formed. After that, an alignment film is formed on the entire upper surface of the glass substrate 50. This gives T
The FT substrate is completed.

Hereinafter, a method for manufacturing the counter substrate will be described. First, a chromium film is formed on a glass substrate by a sputtering method. Then, the chromium film is patterned by photolithography to form a black matrix. Thereafter, a color filter of any one of red (R), green (G), and blue (B) is formed for each pixel.

Next, an ITO film is formed on the entire upper surface of the glass substrate to serve as a counter electrode. After that, an alignment film is formed on the counter electrode. Thereby, the counter substrate is completed. The TFT substrate thus formed and the opposing substrate are joined. For example, a sealing material is applied along the edge of the counter substrate, spacers are scattered on the TFT substrate, the counter substrate is overlapped on the TFT substrate, and the two are joined. At this time, in order to inject liquid crystal between the TFT substrate and the opposing substrate in a later step, a liquid crystal injection port for connecting a space between the TFT substrate and the opposing substrate with an external space is provided. Also, TFT
The common pad 515 on the substrate side and the counter electrode on the counter substrate side are electrically connected by a conductive spacer.

Next, at the position shown by the two-dot chain line in FIG.
The FT substrate is cut, and the common wirings 514a and 514b are removed. Thereafter, liquid crystal is injected between the TFT substrate and the counter substrate, and the liquid crystal injection port is sealed with resin. Thereby, the liquid crystal panel is completed. In the above-described liquid crystal panel manufacturing process, static electricity may be generated during handling, and elements such as TFTs in the display area may be damaged or characteristics may be changed. In order to prevent this, the common wirings 514a and 514b are formed along the edge of the glass substrate 50 as described above.
Are formed, and the TAB terminals 512a and 512b are electrically connected to the common wires 514a and 514b. Thereby, for example, the TAB terminals 512a, 512b
Is applied to one of the TAB terminals 512a, 51b via the common wires 514a, 51b.
2b, so that destruction of the element and changes in characteristics can be avoided.

[0012]

As described above, in the conventional liquid crystal panel manufacturing process, the TAB terminals 512a,
512b is connected to the common wires 514a and 514b to prevent destruction of the element and change in characteristics due to static electricity generated during manufacturing. However, after the TFT substrate is scribed, the gate bus lines 511 and the drain bus lines 541 are in a floating state. Characteristics may change.

An object of the present invention is to provide a liquid crystal panel and a method of manufacturing the same, which can prevent the destruction of the element and the change in characteristics due to static electricity even after the scribe process.

[0014]

The liquid crystal panel of the present invention comprises:
2. A liquid crystal panel according to claim 1, wherein liquid crystal is sealed between a pair of substrates, wherein the liquid crystal panel is formed on one of the substrates and connected to an external circuit. A plurality of connection terminals 112a, 112b, the edge of the one substrate 10 and the connection terminals 112a, 112b.
b, and a plurality of conductive first pads 145 arranged along the edge of the substrate 10 in a region between the first pads 145 and the first pads 145, the first pads 145 having a higher resistance value than the first pads 145; Pad 1
45 and a second pad 132 for electrically connecting between the 45.

In the liquid crystal panel of the present invention, the plurality of conductive first pads 145 having a resistance value of, for example, several tens Ω or less are provided.
And a second pad 132 for electrically connecting between the first pads 145 are formed. These pads 145 and 132 are connected to the edge of the substrate 10 and the connection terminal 112.
a, 112b. The second pad 132 is formed of, for example, silicon, and has a resistance of several kΩ to several MΩ. When static electricity is generated during handling, the static electricity is dispersed by these pads 145 and 132, and destruction of the element and change in characteristics are prevented.

Further, since the second pad 132 has a high resistance value, even when the lead contacts the first pad 145 when the lead is connected to each of the connection terminals 112a and 112b, the second pad 132 exists between the leads. High resistance second pad 132
This prevents the occurrence of an electrical short circuit between the two leads. Further, the first pad 145 is connected to the drain bus line 1
By forming the second pad 132 together with the active layer of the TFT, an increase in the number of manufacturing steps is avoided, and an increase in manufacturing cost is prevented.

In this case, as shown in FIG.
0 is formed along the edge of the first pad 14.
The fifth and second pads 132 may form a closed loop circuit. The static electricity applied to the substrate 10 flows into the closed loop circuit and disappears in the closed loop circuit. As illustrated in FIG. 19, the first pad 145 and the second pad 132 may be electrically connected to a counter electrode (common electrode) of a counter substrate via a common pad 117.

[0018]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a plan view showing a state before scribing of a TFT substrate of a liquid crystal panel according to a first embodiment of the present invention, and FIG. 2 is an enlarged view showing a TAB terminal portion of the same. 3A is a sectional view taken along line AA in FIG.
FIG. 3B is a sectional view taken along line BB in FIG. 2. FIG. 4 is a plan view showing one of the pixel regions, and FIG.
It is sectional drawing by a line. Note that FIG. 1 shows the T
Illustration of the FT 5 and the pixel electrode 16 is omitted. Also,
In FIG. 1, a dashed line indicates the position of the edge of the opposing substrate joined to the TFT substrate, and a dashed line indicates a scribe line of the TFT substrate.

As shown in FIG. 5, the liquid crystal panel is composed of a TFT substrate 1 and a counter substrate 2 arranged to face each other, and a liquid crystal 3 sealed between them. TFT
The substrate 1 includes a glass substrate 10 and a gate bus line 111 formed on one surface (upper surface) of the glass substrate 10.
(See FIG. 1), drain bus line 141, pixel electrode 1
6 and an alignment film 17. The opposite substrate 2 includes a glass substrate 20 and a black matrix 2 formed on one surface (lower surface) of the glass substrate 20.
1, color filter 22, counter electrode 23 and alignment film 24
And the like.

Hereinafter, the TFT substrate 1 will be described in more detail. As shown in FIG. 1, a plurality of gate bus lines 111 and a plurality of drain bus lines 141 are formed on a glass substrate 10. Each gate bus line 1
11 are arranged in parallel with each other, and each drain bus line 141 is arranged so as to intersect the gate bus line 111 at right angles. These gate bus lines 11
A plurality of rectangular regions defined by one and the drain bus line 141 are each a pixel region.

As shown in FIG. 4, each pixel area has a TF
T5 and the pixel electrode 16 are formed. TFT5
Is an α-Si (amorphous silicon) layer 131 selectively formed above the gate bus line 111 and a source electrode 142 formed with the α-Si layer 131 interposed therebetween.
And the drain electrode 143. The source electrode 142 is electrically connected to the pixel electrode 16, and the drain electrode 143 is connected to the drain bus line 141.

In this example, as shown in FIG. 1, a TAB terminal 112 is provided at the left end of each gate bus line 111, respectively.
a is connected. These TAB terminals 112a are arranged vertically along the left edge of the glass substrate 10. These TAB terminals 112a and the glass substrate 1
A common line 114a is formed in a region between the left side of the line 0 and the common line 114a, and each TAB terminal 112a is connected to the common line 114a via a connection line 113a.

The lower end of each drain bus line 141 is connected to the reconnecting section 163, respectively.
These reconnection portions 163 are connected to the TAB terminals 11 respectively.
2b. These TAB terminals 112b are arranged side by side along the lower edge of the glass substrate 10. A common wiring 114b is formed in a region between the TAB terminal 112b and the lower edge of the glass substrate 10, and each TAB terminal 112b is connected to the common wiring 114b via a connection wiring 113b. The common wiring 114b is electrically connected to the common wiring 114a. Reference numeral 115 in FIG. 1 denotes a common pad that is electrically connected to a counter electrode of a counter substrate.

As shown in FIG. 2 and FIG.
A low resistance pad 145 having a resistance value of several tens of ohms or less is formed on the insulating layers 12a and 113b. The resistance value between each low resistance pad 145 is 1
A high resistance pad 132 of about 0 kΩ to 10 MΩ (practically, about several tens kΩ to several MΩ) is formed. As shown in FIG. 6, low resistance pads 145 and high resistance pads 132 are alternately arranged in a portion where the TAB terminals 112a and 112b are arranged (hereinafter, referred to as a TAB terminal connection portion 18) (FIG. 1). ), The glass substrate 1 between the TAB terminal connecting portions 18 and without the TAB terminal connecting portion 18.
Metal wires 19 are formed on the upper edge and the right edge of 0. In other words, the low-resistance pad 145, the high-resistance pad 132, and the metal wiring 19 form a closed loop circuit that goes around the edge of the glass substrate 10.

As shown in FIG. 3, TAB terminals 112a,
112b and the connection wirings 113a and 113b are patterns belonging to the first wiring layer on the glass substrate 10, and the gate bus line 111, the common wirings 114a and 114b, and the metal pattern film 116 also belong to the first wiring layer. That is, these gate bus lines 111 and TAB terminals 11
The reference numerals 2a and 112b, the connection wirings 113a and 113b, the common wirings 114a and 114b, the metal pattern film 116, and the like are formed by patterning the same conductive film.

These gate bus lines 111 and TAB
An insulating film 12 is formed on the terminals 112a and 112b, and a high resistance pad 132 and a low resistance pad 145 are formed on the insulating film 12. Low resistance pad 1
Reference numeral 45 denotes a pattern belonging to the second wiring layer, and includes a drain bus line 141, a source electrode 142, and a drain electrode 1.
43 and the like are also patterns belonging to the second wiring layer.

An insulating film 15 is formed on the drain bus line 141, the low resistance pad 145, and the like. The pixel electrode 16 is formed on the insulating film 15. The insulating film 15 has TAB terminals 112a and 112a.
An opening is provided at a position matching with the low resistance pad 145 and the TAB terminal 112 exposed at this opening.
a, 112b and the surface of the low resistance pad 145 are ITO
The cover films 161 and 162 cover.

FIGS. 7 to 14 are sectional views showing a method of manufacturing the above-mentioned TFT substrate in the order of steps. 7A to 14, (a) shows a cross section of a TFT forming portion,
(B) shows a cross section of the TAB terminal formation portion.
First, as shown in FIGS. 7A and 7B, a chromium (Cr) film is formed on a glass substrate 10 by sputtering to a thickness of 150 nm.
m, and pattern the chrome film.
Gate bus line 111, TAB terminals 112a, 112
b, connection wiring 113a, 113b common wiring 114a, 1
Each pattern of the first wiring layer such as 14b and the metal pattern film 116 is formed. Among them, the metal pattern film 116
Is a pattern that does not exist in the related art, but is formed in a region on the glass substrate 10 where the high resistance pad 132 is to be formed.

Then, as shown in FIGS. 8A and 8B, the insulating film 12 serving as the gate insulating film of the TFT 5 and the TF are formed on the entire upper surface of the glass substrate 10 by the plasma CVD method.
An α-Si film 131 serving as an active layer of T and an insulating film 135 serving as a channel protective film are continuously formed. In this case,
For example, the insulating films 12 and 135 are both formed of silicon nitride (SiNx), and the thickness of the insulating film 12 is 400
nm, and the thickness of the insulating film 135 is 120 nm. Also,
The thickness of the α-Si film 131 is 30 nm.

Next, a photosensitive resist (not shown) is applied on the insulating film 135, and is exposed from the back side of the glass substrate 10 (back side exposure). , And then subjected to development processing. Thereby, the resist is left at a predetermined position above the gate bus line 111. Then, the insulating film 135 is etched using the resist as an etching mask. Thus, as shown in FIGS. 9A and 9B, the channel protective film 136 is formed at a predetermined position on the α-Si film 131. Thereafter, the resist is removed, and etching is performed for about 10 seconds with dilute hydrofluoric acid in order to remove the natural oxide film on the surface.

Next, as shown in FIGS. 10A and 10B, an n ⁺ type α-Si film 133 serving as an ohmic contact layer is formed on the entire upper surface of the glass substrate 10 to a thickness of 28 nm. On top of that, Ti (20 nm) / Al (75 nm)
A conductive film 14 having a three-layer structure of / Ti (80 nm) is formed. Then, a resist film (not shown) is formed in a predetermined pattern on the conductive film 14, and the conductive film 14 and the α-Si films 133, 1 are formed using the resist film as an etching mask.
31 is etched. Thereby, as shown in FIG. 11A, the TFT 5 is completed and the high-resistance pad 132 is formed. At the same time, another pattern of the second wiring layer, that is, the data bus line 141,
The low resistance pad 145 and the metal wiring 19 are formed.

Next, as shown in FIGS. 12A and 12B, an insulating film 15 made of silicon nitride is formed as a protective film on the entire upper surface of the glass substrate 10 by a plasma CVD method.
It is formed to a thickness of 30 nm. Then, FIG.
As shown in FIG. 2B, a contact hole is formed at a position where the insulating film 15 matches the source electrode 142 and at a position where the reconnection portion 163 is formed, and the TAB terminal 112 is formed.
a and the low resistance pad 145 that exposes 112b
The opening which exposes is formed.

Next, as shown in FIGS. 14A and 14B, an ITO film having a thickness of 70 nm is formed on the entire upper surface of the glass substrate 10 by a sputtering method, and the ITO film is formed by a photolithography method. By patterning, the pixel electrode 16
, The reconnection unit 163, and the TAB terminals 112a and 112b.
An ITO cover film 162 covering the top of 2b and an ITO cover film 161 covering the high resistance pad layer 145 are formed. Thereafter, an alignment film 17 made of, for example, polyimide is formed on the entire upper surface of the glass substrate 10. Thereby, TF
The manufacture of the T substrate is completed.

On the other hand, the counter substrate 2 is formed as described below. That is, a chromium film is formed on the entire upper surface of the glass substrate 20, and the chromium film is patterned by a photolithography method to form a black matrix 21 (see FIG. 5). Thereafter, a color filter 22 of any one of red (R), green (G), and blue (B) is formed in each pixel region on the glass substrate 20.

Next, the entire upper surface of the glass substrate 20 is made of ITO.
Is formed to form a counter electrode 23. Thereafter, an alignment film 24 made of polyimide is formed on the counter electrode 23.
To form Thereby, the counter substrate 2 is completed. After forming the TFT substrate 1 and the counter substrate 2 in this manner,
The TFT substrate 1 and the opposing substrate 2 are bonded with a sealing material.
Thereafter, the TFT substrate 1 is scribed at the position shown by the two-dot chain line in FIG. 1 to cut off the common wirings 114a and 114b,
Liquid crystal 3 is injected between the TFT substrate 1 and the opposing substrate 2.
Then, when the liquid crystal injection port is sealed with a resin, a liquid crystal panel is completed.

In the liquid crystal panel of the present embodiment, a closed loop circuit including the high resistance pad 132, the low resistance pad 145, and the metal wiring 19 is formed along the edge of the glass substrate 10. Then, the IT covering the low resistance pad 145
The O cover film 171 is exposed on the surface of the edge of the glass substrate 10. For this reason, even if static electricity is generated when handling the panel, the static electricity is applied to the low-resistance pad 10.
And disappears by flowing through the closed loop circuit. This avoids applying static electricity directly to the TAB terminals 112a and 112b, thereby preventing destruction of elements in the display area and changes in characteristics. Therefore, the production yield of the liquid crystal panel is improved, and the product cost can be reduced.

In the present embodiment, as described above, the high resistance pad 132 is formed simultaneously with the α-Si film 131 serving as the active layer of the TFT 5, and the high resistance pad 145 is formed.
Since the metal wiring 19 is formed at the same time as the drain bus line 141, a closed loop circuit including the high resistance pad 132, the low resistance pad 145, and the metal wiring 19 can be formed without increasing the number of processes as compared with the related art. It is possible, and an increase in manufacturing cost is avoided.

When connecting each of the TAB terminals 112a and 112b to the TAB lead, the TAB lead may contact the low-resistance pad 145. Since the high-resistance pad 132 of kΩ to several MΩ is present, a short circuit does not occur between the TAB leads via the low-resistance pad 145, and a failure occurs due to the formation of the low-resistance pad 145 and the high-resistance pad 132. It does not occur.

(Second Embodiment) FIG. 15 is a plan view showing a TAB terminal of a liquid crystal panel according to a second embodiment of the present invention and its vicinity, and FIG. 16A is a line DD of FIG. FIG. 16B is a cross-sectional view of a junction between the TFT substrate and the counter substrate. In FIG. 15, a two-dot chain line indicates a scribe line of the TFT substrate. Further, the present embodiment is different from the first embodiment in that the position of the scribe line is different, and the other configuration is basically the same as that of the first embodiment. Description is omitted. Further, reference numeral 4 in FIG. 16B indicates a sealing material for joining the TFT substrate 1 and the counter substrate 2.

In this embodiment, the high resistance pad 1
32 and the low resistance pad 145 are connected to the common wiring 114a, 11
4b, these high-resistance pads 1
The common wirings 114a and 114b are separated by scribing the TFT substrate at the positions of the low resistance pad 32 and the low resistance pad 145. Therefore, as shown in FIG.
The low-resistance pad 145 is exposed on the end surface of the T substrate 1. As a result, static electricity applied to the end face of the TFT substrate 1 is applied to the low-resistance pad 145, and is dispersed and disappears in the closed loop circuit.

In this embodiment, it is possible to prevent the destruction of the element and the change in the characteristics due to the static electricity applied to the surface and the end face of the TFT substrate. (Third Embodiment) FIG. 17A is a plan view showing a TAB terminal of a liquid crystal panel according to a third embodiment of the present invention and the vicinity thereof, and FIG. FIG. 4 shows a cross-sectional view taken along line -E. 17, the same components as those in FIG. 1 are denoted by the same reference numerals.

In this embodiment, the low resistance pad 1
The width of 45 is set to be equal to or smaller than the width of the TAB terminals 112a and 112b. In the present invention, static electricity is applied to the high resistance pad 132 and the low resistance pad 14.
By dispersing through the element 5, destruction of the element and change in characteristics are prevented, so that at least one of the high resistance pad 132 and the low resistance pad 145 needs to be exposed on the substrate. In the present embodiment, the low-resistance pad 1
45 is exposed on the substrate, but the low-resistance pad 145 is exposed.
Is increased, as shown in FIG.
TAB lead 26 connected to B terminals 112a and 112b
May be simultaneously connected to two adjacent low-resistance pads 145 to cause a short circuit failure.

As in the present embodiment, the low resistance pad 145 is used.
18B is equal to or smaller than the width of the TAB terminals 112a and 112b, so that the TAB terminals 112a and 112b and the TAB leads 26 as shown in FIG.
Even if the position is shifted, the TAB lead 26 does not come into contact with the two low-resistance pads 145 at the same time, so that a short-circuit failure can be reliably avoided.

(Fourth Embodiment) FIG. 19 is a plan view showing a liquid crystal panel according to a fourth embodiment of the present invention. Note that the present embodiment is different from the first embodiment in that no metal wiring is formed on the upper edge portion and the right edge portion of the glass substrate 10, and the other basic configuration is the same as that of the first embodiment.
This is the same as the embodiment.

In the present embodiment, unlike the first embodiment, the metal wiring 19 is not formed on the upper edge and the right edge of the glass substrate 10. As shown in FIG. 1, TAB terminals 112a, 112a
b, a plurality of low resistance pads 14 arranged at positions matching
5 and high resistance pads 132 connecting between the low resistance pads 145 are formed. The metal wiring 19 connecting between the TAB terminal connecting portions 18 is connected to the common pad 117.
And is electrically connected to the counter electrode of the counter substrate via the common pad 117.

In this embodiment, the low resistance pad 1
Since the static electricity applied to 45 flows through the common pad 117, the same effect as that of the first embodiment is obtained in that the destruction of the element and the change in the characteristics are prevented even after the scribe step. In each of the above embodiments, TF
A method of forming a liquid crystal panel by injecting liquid crystal between the two substrates after bonding the T substrate and the counter substrate has been described. However, when the TFT substrate and the counter substrate are bonded together, There is also a method in which liquid crystal is sealed between substrates by dropping the liquid crystal. The present invention can be applied to such a method.

[0047]

As described above, according to the present invention,
In a region between the edge of the substrate and the connection terminal, a plurality of conductive first pads arranged along the edge of the substrate, and a high-resistance second pad connecting between the first pads. Since these pads are formed, it is possible to prevent destruction of the element and change in characteristics due to static electricity even after the scribing step. As a result, the production yield of the liquid crystal panel is improved, so that there is an effect that the product cost can be reduced.

Further, by forming the first pad at the same time as the drain bus line and forming the second pad at the same time as the TFT active layer, an increase in the number of manufacturing steps can be avoided.

[Brief description of the drawings]

FIG. 1 is a plan view showing a state before a scribe of a TFT substrate of a liquid crystal panel according to a first embodiment of the present invention.

FIG. 2 is a TAB of the liquid crystal panel according to the first embodiment;
It is an enlarged view which shows a terminal part.

3A is a cross-sectional view taken along line AA of FIG. 2, and FIG. 3B is a cross-sectional view taken along line BB of FIG.

FIG. 4 is a plan view showing one of the pixel regions.

FIG. 5 is a sectional view taken along line CC of FIG. 4;

FIG. 6 is a plan view showing a metal wiring connected to a TAB terminal connection part.

FIG. 7 is a sectional view (part 1) illustrating the method for manufacturing the liquid crystal panel of the first embodiment.

FIG. 8 is a sectional view (part 2) illustrating the method for manufacturing the liquid crystal panel of the first embodiment.

FIG. 9 is a sectional view (part 3) illustrating the method for manufacturing the liquid crystal panel of the first embodiment.

FIG. 10 is a sectional view (part 4) illustrating the method for manufacturing the liquid crystal panel of the first embodiment.

FIG. 11 is a sectional view (part 5) illustrating the method for manufacturing the liquid crystal panel of the first embodiment.

FIG. 12 is a sectional view (part 6) illustrating the method for manufacturing the liquid crystal panel of the first embodiment.

FIG. 13 is a sectional view (part 7) illustrating the method for manufacturing the liquid crystal panel of the first embodiment.

FIG. 14 is a sectional view (part 8) illustrating the method for manufacturing the liquid crystal panel of the first embodiment.

FIG. 15 is a plan view showing a TAB terminal of a liquid crystal panel according to a second embodiment of the present invention and the vicinity thereof.

16 (a) is a cross-sectional view taken along line DD of FIG. 15, and FIG. 16 (b) is a cross-sectional view of a junction between a TFT substrate and a counter substrate.

17A is a plan view showing a TAB terminal of a liquid crystal panel according to a third embodiment of the present invention and the vicinity thereof, and FIG. 17B is a view taken along line EE in FIG. 17A. FIG.

18A is a diagram showing a problem when the width of a high-resistance pad is larger than the width of a TAB terminal; FIG.
(B) is a diagram showing the effect when the width of the high resistance pad is made smaller than the width of the TAB terminal.

FIG. 19 is a plan view showing a liquid crystal panel according to a fourth embodiment of the present invention.

FIG. 20 is a plan view showing a TFT substrate of a conventional liquid crystal panel.

[Explanation of symbols]

1 TFT substrate, 2 counter substrate, 3 liquid crystal, 10, 20, 50 glass substrate, 111, 511 gate bus line, 112a, 112b, 512a, 512b TAB terminal, 113a, 113b, 513a, 513b Connection wiring, 114a, 114b, 514a, 514b common wiring, 115, 117, 515 common pad, 116 metal pattern film, 12, 15, 135 insulating film, 131 α-Si (amorphous silicon) film, 132 high resistance pad, 133 n ⁺ type α-Si film , 14 conductive film, 141,541 drain bus line, 142 source electrode, 143 drain electrode, 145 low resistance pad, 16 pixel electrode, 161,162 ITO cover film, 17,24 alignment film, 18 TAB terminal connection part, 19 metal Wiring, 21 black matrix, 22 color filter, 23 counter electrode.

Continued on front page F-term (reference) 2H092 GA50 GA51 JA26 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB52 JB57 JB63 JB69 JB79 KA05 KA07 KA16 KA18 KB25 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA32 MA35 MA41 PA05 AA42 AA43 AA46 AA60 BA03 BA43 CA19 CA24 DA12 DA13 DB01 DB02 DB04 DB05 EA04 EA05 EB02 EC04 ED03 FA01 FB02 FB12 FB14 GB01

Claims (5)

[Claims] 1. A liquid crystal panel having liquid crystal sealed between a pair of substrates, a plurality of connection terminals formed on one of the pair of substrates and connected to an external circuit, and the one substrate. A plurality of conductive first pads arranged along an edge of the substrate in a region between the edge of the connection terminal and the connection terminal; and a resistance value is higher than the first pad, A liquid crystal panel having a first pad and a second pad for electrically connecting between the first pads. 2. The liquid crystal panel according to claim 1, wherein the first pad is exposed on a surface of the one substrate, and the second pad is covered with an insulating film. 3. The plurality of first pads are respectively arranged at positions matching the plurality of connection terminals, and the width of the first pads is equal to or smaller than the width of the connection terminals. The liquid crystal panel according to claim 1, wherein: 4. The device according to claim 1, wherein the first pad and the second pad are electrically connected to an electrode provided on the other of the pair of substrates.
The liquid crystal panel according to 1. 5. A step of forming a first conductive film on a substrate, patterning the first conductive film, and arranging the plurality of gate bus lines along a first edge of the substrate. A plurality of first connection terminals respectively connected to the plurality of gate bus lines; a plurality of second connection terminals arranged along a second edge of the substrate; Forming a common wire disposed on the first edge and the second edge, and a connection wire connecting each of the first connection terminal, the second connection terminal, and the common wire; Forming a first insulating film over the entire upper surface of the substrate; forming a silicon film serving as an active layer of a transistor in a predetermined region above the gate bus line; A high resistance package made of silicon Forming a second conductive film on the first insulating film; patterning the second conductive film to intersect the gate bus line; A plurality of drain bus lines respectively connected to the two connection terminals, a source electrode and a drain electrode electrically connected to both ends of the silicon film, and a low resistance electrically connecting the high resistance pad. A step of forming a pad; a step of forming a second insulating film over the entire upper surface of the substrate; a contact hole reaching the source electrode in the second insulating film; and an opening reaching the low resistance pad. Forming a portion, forming a transparent conductor film on the second insulating film, patterning the transparent conductor film into a predetermined shape, and forming a portion of the substrate on which the common wiring is formed. Cut the first Method of manufacturing a liquid crystal panel; and a step of mutually electrically isolate the connection terminal and the second connecting terminal.