JP2001102388A - High voltage semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a high withstand voltage lateral bipolar transistor which suppresses a base width modulation effect and has a high early voltage. SOLUTION: A second conductivity type emitter region 5 and a second conductivity type collector region 7 selectively formed on a surface of a first conductivity type semiconductor region 3, a second conductivity type emitter region 5 and a collector region 7, A first conductive type base contact region 8 selectively formed on the surface of the first conductive type semiconductor region 3 at a distance and a second conductive type collector region 7 facing the second conductive type emitter region 5 A high breakdown voltage semiconductor device comprising: a second conductivity type semiconductor region having a lower concentration than the second conductivity type collector region formed in contact with and separated from the second conductivity type emitter region. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a lateral bipolar transistor.

[0002]

2. Description of the Related Art As one of conventional high breakdown voltage elements, there is a lateral bipolar transistor (lateral bipolar transistor), and it has been attempted to form it on a substrate such as SOI. A conventional example of this lateral bipolar transistor will be described by taking a PNP type lateral bipolar transistor as an example.

FIG. 5 is a cross-sectional view of a conventional PNP type lateral bipolar transistor. As shown in FIG. 5, an insulating film 10 made of a silicon oxide film is formed on a semiconductor substrate 101.
2 is formed, and an N-type semiconductor layer 1 is formed on the insulating film 102.
03 is formed. A P ⁺ -type emitter region 104 is formed on the surface of the N-type semiconductor layer 103, and the N-type semiconductor layer 103 is formed so as to surround the P ⁺ -type emitter region 104.
A P ⁺ type collector region 105 is formed on the surface of the substrate.
Further, an N ⁺ -type base contact region 106 is formed on the surface of the N-type semiconductor layer 103 outside the P ⁺ -type emitter region 104 and the P ⁺ -type collector region 105. P ⁺ type emitter region 104, P ⁺ type collector region 1
An emitter electrode 107, a collector electrode, and a base electrode 109 are provided in the base contact region 05 and the N ⁺ type base contact region 106, respectively. The N-type semiconductor layer 103 between the P ⁺ -type emitter region 104 and the P ⁺ -type collector region 105 functions as a base region.

In order to increase the breakdown voltage of such a conventional PNP type lateral bipolar transistor, the depletion layer is generally extended to the base side by lowering the impurity concentration of the base region, and the electric field is reduced. However, lowering the impurity concentration in the base region causes the following problem. That is, there is a problem in that the base width gradually decreases due to the electric field from the collector side, a base width modulation effect in which the gain changes appears, and the Early voltage decreases. For example, when an analog circuit is formed with transistors having a low Early voltage, the performance of the circuit is deteriorated. As an example, if a transistor with a low Early voltage is used for the comparator,
The gain may be reduced. Here, as shown in FIG. 3, when the voltage between the collector and the emitter is plotted on the horizontal axis and the collector current is plotted on the vertical axis as shown in FIG. This is the voltage value at the point where the axis intersects.

[0005]

As described above, conventionally, when the breakdown voltage of a lateral bipolar transistor is increased, the depletion layer is expanded toward the base side by lowering the impurity concentration of the base region to reduce the electric field. Was. However, when the impurity concentration in the base region is reduced, there is a problem that the base width gradually decreases due to the electric field from the collector side, the base width modulation effect appears remarkably, and the Early voltage decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a lateral bipolar transistor having a high early voltage and suppressing a base width modulation effect while maintaining a withstand voltage.

[0007]

(Structure) In order to solve the above problems, a first aspect of the present invention is to provide a second conductive type emitter region selectively formed on a surface of a first conductive type semiconductor region, and A second conductivity type collector region; a first conductivity type base contact region selectively formed on a surface of the first conductivity type semiconductor region apart from the second conductivity type emitter region and the collector region; A second conductivity type collector formed between the two conductivity type collector region and the second conductivity type emitter region, separated from the second conductivity type emitter region and formed in contact with the second conductivity type collector region; A high breakdown voltage semiconductor device comprising: a first second conductivity type semiconductor region having a lower concentration than the region.

In the first aspect of the present invention, the first second conductivity type semiconductor region has a portion provided between the second conductivity type collector region and the first conductivity type base contact region. Preferably, the portion is separated from the first conductivity type base contact region.

A second conductive type collector region is formed between the second conductive type collector region and the second conductive type emitter region so as to be separated from the second conductive type collector region and in contact with the second conductive type emitter region. It is preferable that the semiconductor device further includes a second second conductivity type semiconductor region having a lower concentration than the second conductivity type emitter region.

Furthermore, the second second conductivity type semiconductor region has a portion provided between the second conductivity type emitter region and the first conductivity type base contact region,
The portion is preferably separated from the first conductivity type base contact region.

A second aspect of the present invention is a second conductivity type emitter region and a second conductivity type collector region selectively formed on a surface of a first conductivity type semiconductor region, and the second conductivity type emitter region. A first conductivity type base contact region selectively formed on the surface of the first conductivity type semiconductor region apart from the collector region; and the second conductivity type collector region facing the second conductivity type emitter region. Formed in contact with the portion of the second conductivity type and separated from the second conductivity type emitter region.
A first second lower concentration than the second conductivity type collector region;
A high breakdown voltage semiconductor device including a conductive semiconductor region is provided.

In the second aspect of the present invention, the first second-conductivity-type semiconductor region is also formed in a portion of the second-conductivity-type collector region facing the first-conductivity-type base contact region. The second conductivity type semiconductor region is preferably separated from the first conductivity type base contact region.

Further, the second conductivity type emitter region is formed in contact with a portion of the second conductivity type emitter region facing the second conductivity type collector region and formed apart from the second conductivity type collector region. It is preferable to include a second second conductivity type semiconductor region having a lower concentration than that.

Further, the second second conductivity type semiconductor region is also formed in a portion of the second conductivity type emitter region facing the first conductivity type base contact region, and the second second conductivity type semiconductor region is formed. Preferably, the semiconductor region is separated from the first conductivity type base contact region.

Further, in each of the above-mentioned inventions, it is more preferable to have the following configuration.

(1) The dose of the second second conductivity type semiconductor region is 4.0 × 10 ¹² cm ⁻² or less.

(2) The dose of the first second conductivity type semiconductor region is not more than 4.0 × 10 ¹² cm ⁻² .

(3) On the surface of the first conductivity type active region provided on the same substrate as the first conductivity type semiconductor region, the second conductivity type source region and the second conductivity type source region selectively formed apart from each other are formed. A two-conductivity-type drain region and the second-conductivity-type source region are formed apart from and in contact with the second-conductivity-type drain region. A third second conductivity type semiconductor region having a lower concentration than the second conductivity type drain region,
A gate electrode formed on a surface of the first conductivity type active region interposed between the third second conductivity type semiconductor region and the second conductivity type source region via a gate insulating film; thing.

(4) The second conductivity type collector region is formed so as to surround the second conductivity type emitter region except for a portion between the first conductivity type base contact region and the second conductivity type emitter region. is being done.

(5) The semiconductor region of the first conductivity type is formed on an insulating region.

A third aspect of the present invention is a second conductivity type emitter region and a second conductivity type collector region selectively formed on a surface of a first conductivity type semiconductor region, and the second conductivity type emitter region. A first conductive type base contact region selectively formed on the surface of the first conductive type semiconductor region apart from the collector region; and a second conductive type collector region and the second conductive type emitter region. A region for adjusting a width of a base region on a surface of the semiconductor region of the first conductivity type between the collector region and a region for relaxing an electric field between the collector region of the second conductivity type and the emitter region of the second conductivity type. A high breakdown voltage semiconductor device characterized by the following.

It is preferable that the third aspect of the present invention also includes the constituent features of each of the above-described inventions.

(Function) According to the present invention, in a lateral bipolar transistor (for example, a PNP type), in order to maintain a breakdown voltage, a depletion layer is not extended to a base side but to a collector side, unlike a conventional one. The depletion layer is extended to reduce the electric field. For this purpose, a second conductivity type semiconductor region having a lower concentration than the second conductivity type collector region is formed.
In such a second conductivity type semiconductor region, a depletion layer extends from the interface with the base region, and a breakdown voltage can be ensured in the second conductivity type semiconductor region. Therefore, since the impurity concentration in the base region can be increased, the extension of the depletion layer in the base region can be suppressed, the base width modulation effect due to the decrease in the base width can be suppressed, and the early voltage can be increased.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a top view showing the structure of a first embodiment of the high breakdown voltage semiconductor device of the present invention. 2 (a) and 2 (b) are respectively
FIG. 2 is a cross-sectional view taken along line segments AA ′ and BB ′ of the high breakdown voltage semiconductor device of FIG.

As shown in FIGS. 1 and 2, this embodiment shows a PNP type lateral bipolar transistor.
First, an insulating film 2 made of a silicon oxide film is formed on a semiconductor substrate 1, and an N-type semiconductor layer 3 is formed on the insulating film 2. A P ⁺ -type emitter region 5 is formed on the surface of the N-type semiconductor layer 3, and a P ⁺ -type collector region 7 is formed on the surface of the N-type semiconductor layer 3 so as to surround the P ⁺ -type emitter region 5. (FIG. 1).

Further, the surface of the N-type semiconductor layer 3 is separated from the P ⁺ -type emitter region 5 and the P ⁺ -type collector region 7 by N
^{A +} type base contact region 8 is formed. N-type semiconductor layer 3 between P ⁺ -type emitter region 5 and P ⁺ -type collector region 7 functions as a base region. P ⁺ type collector region 7
Is formed so as to surround the P ⁺ -type emitter region 5 except for a portion between the N ⁺ -type base contact region 8 and the P ⁺ -type emitter region 5.

As described above, the N ⁺ type base contact region 8
The reason why the P ⁺ -type collector region 7 is not formed in the portion between the P ⁺ -type emitter region 5 and the P ⁺ -type emitter region 5 is as follows. That is,
N ⁺ type base contact region 8 to P ⁺ type emitter region 5
This is because a sufficient value of the base current can be obtained because the base current to the P is not affected by the potential barrier of the P ⁺ -type collector region 7. Such a structure is effective for a normal semiconductor substrate, but is particularly effective for SOI (Silicon).
In the case of an On Insulator substrate, it is not necessary to provide an N ⁺ -type buried region, which will be described later, and it is possible to secure a sufficient base current with a simple structure.

Further, as an important component of the present invention, low concentration P than the P ⁺ -type collector region 7 around the P ⁺ type collector region 7 ^- -type semiconductor region 6 is formed. The P ^- -type semiconductor region 6 is spaced apart is formed in contact with a portion of the P ⁺ -type collector region 7 facing the P ⁺ -type emitter region 5 and the P ⁺ -type emitter region 5.

Furthermore, also the emitter side, a P ⁺ type emitter region around it 5 P at a lower concentration than the P ⁺ -type emitter region 5 ^- -type semiconductor regions 4 are formed. The P ^-
Type semiconductor region 4 is opposed to the P ⁺ type collector region 7 P ⁺
It is formed in contact with the portion of the type emitter region 5 and is formed apart from the P ⁺ type collector region 7.

The P ⁺ -type emitter region 5, the P ⁺ -type collector region 7, and the N ⁺ -type base contact region 8 respectively have
Emitter electrode 9, collector electrode 10, and base electrode 1
1 is provided. In FIG. 1, as the collector electrode,
In addition to the collector electrode 10, collector electrodes 12 and 13 are shown. These collector electrodes 12 and 13 function to reduce the contact resistance.

As described above, the lateral bar of the present embodiment is
According to the bipolar transistor, P ⁺Mold collector area 7
And P⁺Each as an electric field relaxation layer in the respective emitter regions 5
P^-Semiconductor regions 6 and 4 are formed, and P⁺Type Emi
Area 5 and P⁺N-type semiconductor layer 3 between collector regions 7
The impurity concentration of the (base region) is increased.

A lateral bipolar transistor having such a structure
In this case, the impurity concentration in the base region is high and the depletion layer is mainly
As P^-Extending into the semiconductor regions 6 and 4.
You. For this reason, the base width that greatly affects the gain
As described above, the electric field relaxation layer is
Forming the two electric field relaxation layers (P
^-It is the distance between the type semiconductor regions 6 and 4). Accordingly
Base width is not affected by mask alignment accuracy.
Therefore, an element with less variation can be realized. In addition,
Ensures pressure resistance by the same principle as RESURF used in
Can be

Table 1 shows a comparison result obtained by simulating the structure of the high breakdown voltage device according to the present invention and the structure of the conventional device.

[0035]

[Table 1]

According to Table 1, the structure of the present invention improved the Early voltage from 21.3 V to 51.6 V as compared with the conventional structure. The breakdown voltage between the collector and the emitter is also 43.3.
V to 62.0V.

Where P⁺Mold collector region 7 and P⁺Type d
The surface concentration of impurities in the emitter region 5 is
Typically 1x10 each¹⁷cm^-3
That is all. Furthermore, P^-Type semiconductor regions 6 and 4 net
Impurity doses of 4.0 × 10¹²cm^-2Less than
It is preferable to set the lower range. 4.0 × 10¹²cm ^-2
If it is higher than^-Type semiconductor regions 6 and 4
It is difficult to provide sufficient withstand voltage because
It will be difficult. Also, P⁺Type emitter region 5 and P⁺Type collector
Net impurity of N-type semiconductor layer 3 (base region) between regions 7
The lower limit of the substance dose is the punch-through withstand voltage,
The upper limit is determined by the balance of the pressure and the gain, V
_cbo(Emitter open collector-base breakdown voltage.
Withstand pressure just below Kuta. ). For example, P^-Mold semiconductive
The net impurity dose of the body regions 6 and 4 is 2.0 × 10
¹²cm^-2Of the N-type semiconductor layer 3 (base region)
2.6 × 10¹²cm^-2And can
You. Here, the impurity dose of the N-type semiconductor layer 3 is set to P^-Type
Preferably, it is higher than that of the semiconductor regions 6 and 4.
(The same applies to other embodiments).

(Second Embodiment) FIG. 4 is a sectional view for explaining the configuration of a second embodiment of the high breakdown voltage semiconductor device according to the present invention. In the present embodiment, a double diffusion type P-channel lateral MOSFET (DMOSFE) shown in FIG.
T) is formed on the same substrate as the PNP type lateral bipolar transistor shown in the first embodiment.

As shown in FIG. 4, an insulating film 2 made of a silicon oxide film is formed on a semiconductor substrate 1.
An N-type semiconductor layer 3 is formed thereon. On the surface of the N-type semiconductor layer 3, the PNP type lateral bipolar transistor shown in the first embodiment is formed in the first region. On the surface (second region) of the N-type semiconductor layer 3 different from the first region, the following double diffusion type P-channel lateral MOSFET is formed.

That is, a P ⁺ -type source region 42 is formed on the surface (second region) of the N-type semiconductor layer 3, and is adjacent to the P ⁺ -type source region 42. Is N
^{A +} -type contact region 41 is formed. A P ⁻ type semiconductor region 43 is formed on the surface of the N type semiconductor layer 3 at a distance from the P ⁺ type source region 42, and a P ⁺ type drain region 44 is formed on the surface of the P ⁻ type semiconductor region 43. It is selectively formed.

P ⁻ type semiconductor region 43 and P ⁺ type source region 4
2 is provided on the surface of the N-type semiconductor layer 3 between the gate insulating film 4
6, a gate electrode 47 is formed. Also, P
LOCOS silicon oxide film 4 including the surface of P ⁻ type semiconductor region 43 between ⁺ type drain region 44 and N type semiconductor layer 3
5 are selectively formed. This silicon oxide film 45
Functions to reduce the electric field at the end of the gate electrode 47 on the drain side. The gate electrode 47 is a silicon oxide film 4
5 and is formed so as to extend above.

P⁺Mold source region 42 and N⁺Type contact
In the region 41, a source electrode 48 is provided. ⁺Type drain region 4
4 is provided with a drain electrode 49.

As described above, in the present embodiment, as described above, the P-channel lateral MOSFET and the PNP lateral bipolar transistor shown in the first embodiment are formed by being mounted on the same SOI substrate. ing.
According to the present embodiment, the P-channel type lateral MOSFE
Since the P ⁻ type semiconductor region 43 of T and the P ⁻ type semiconductor regions 4 and 6 (FIGS. 1 and 2) of the PNP type lateral bipolar transistor can be formed in the same process,
The P ⁻ -type semiconductor region 43 of the P-channel lateral MOSFET can be formed in a simple process without forming both in separate processes.

In FIG. 4, the electric field relaxation layer (corresponding to the P ⁻ type semiconductor region 43) in the drift region of the double diffusion type P channel type lateral MOSFET is a PNP type lateral bipolar transistor shown in the first embodiment. In order to maintain the breakdown voltage by the same principle as the transistor, they can be shared. While the function of the electric field relaxation layer of a lateral bipolar transistor is only to reduce the electric field on the surface, the double diffusion type MOSF
The electric field relaxation layer of the ET flows a current in addition to its function. Therefore, in the case of a double diffusion type MOSFET, the electric field relaxation layer (corresponding to the P ⁻ type semiconductor region 43) needs to have low resistance.

[0045] The principle of RESURF, in the off state P ^- -type by N-type semiconductor layer 3 below the semiconductor region 43 P ^- can easily deplete -type semiconductor region 43. Therefore, the net impurity dose of this electric field relaxation layer is 2 × 10 ¹² cm.
^-2 , maximum 4 × 1 for MOSFETs with low breakdown voltage
It can be increased to about 0 ¹² cm ^-2 , and a low resistance can be realized while maintaining the withstand voltage. Therefore, to form a lateral bipolar transistor having a high Early voltage and a double-diffusion MOSFET having a low on-resistance on the same semiconductor substrate, a net impurity dose of about 2 × 10 ¹² cm ⁻² is suitable.

As described above, a PNP-type lateral bipolar transistor having a high early voltage and a P-channel-type lateral DMOSFET having a low on-resistance without increasing the number of steps.
Can be formed on the same semiconductor substrate.

The present invention is not limited to the above embodiment. For example, in the above embodiment, a P ⁻ type semiconductor region is formed as an electric field relaxation layer in each of the collector region and the emitter region.
The effect of the present invention can be achieved even if such an electric field relaxation layer is provided only in the collector region.

An electric field relaxation layer is provided between the collector region and the base contact region and between the emitter region and the base contact region. This is V
_cbo (emitter open collector-base breakdown voltage), V
_{This is for obtaining ceo} (withstand voltage between the open base collector and the emitter), but it is not always necessary to provide the electric field relaxation layer in such a region depending on the withstand voltage design.

In the above embodiment, the P ⁺ type collector region 7 is formed surrounding the P ⁺ type emitter region 5 except for a portion between the N ⁺ type base contact region 8 and the P ⁺ type emitter region 5. However, the present invention is not limited to such a form, and the present invention is applicable to a structure in which the emitter region is completely surrounded by the collector region. In this case, (also under the P ⁺ -type emitter region 5 and the P ⁺ -type collector region 7.) N-type lower semiconductor layer 3 serving as a base region is provided an N ⁺ -type buried region, the N ⁺ -type buried Preferably, the region is connected to N ⁺ type base contact region 8 by a deep diffusion layer. When the N ⁺ type buried region is provided in this manner, the base current passes through the N ⁺ type buried region,
Since the power is supplied to the base region between the P ⁺ -type emitter region 5 and the P ⁺ -type collector region 7, a large amount of base current can be supplied. Even in such a case, the effects of the present invention can be sufficiently exhibited.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0051]

According to the present invention, it is possible to provide a high withstand voltage lateral bipolar transistor having a high early voltage and a suppressed base width modulation effect.

[Brief description of the drawings]

FIG. 1 is a top view showing a configuration of a first embodiment of a high breakdown voltage semiconductor device according to the present invention.

FIG. 2 is a line segment AA ′, BB of the high breakdown voltage semiconductor device of FIG. 1;
FIG.

FIG. 3 is a characteristic diagram showing Early voltage.

FIG. 4 is a cross-sectional view illustrating a configuration of a second embodiment of the high breakdown voltage semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a configuration of a conventional lateral bipolar transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Insulating film 3 ... N-type semiconductor layer 4 ... P ^- semiconductor region 5 ... P ⁺ -type emitter region 6 ... P ^- semiconductor region 7 ... P ⁺ -type collector region 8 ... N ⁺ -type base contact region 9 ... The emitter electrode 10 ... collector electrode 11 ... base electrode 12 ... collector electrodes 13 ... collector electrode 41 ... N ⁺ -type contact region 42 ... P ⁺ -type source region 43 ... P ^- -type semiconductor region 44 ... P ⁺ -type drain region 45 ... silicon oxide Film 46 gate insulating film 47 gate electrode 48 source electrode 48 49 drain electrode 49

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Tomoko Suedai, 1st Toshiba R & D Center, Komukai Toshiba, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Hirofumi Nagano Kobuka Toshiba, Koyuki-ku, Kawasaki-shi, Kanagawa No. 1 Toshiba Microelectronics Center, Inc. (72) Inventor Akio Nakagawa 1 Tokoba Toshiba, Komukai Toshiba, Kawasaki-shi, Kanagawa F-term (Reference) 5F003 AP06 AZ03 BC01 BE01 BG01 BJ15 BN01 5F110 AA13 BB12 CC02 DD05 FF12 GG02 HJ13 HM12 HM15

Claims (14)

[Claims] A second conductive type emitter region and a second conductive type collector region selectively formed on a surface of a first conductive type semiconductor region; and a second conductive type emitter region and a collector region. A first conductive type base contact region selectively formed on a surface of the first conductive type semiconductor region; and a second conductive type emitter region between the second conductive type collector region and the second conductive type emitter region. A second conductive type semiconductor region having a lower concentration than the second conductive type collector region, the first second conductive type semiconductor region being formed in contact with the second conductive type collector region and being separated from the type emitter region. High withstand voltage semiconductor device. 2. The semiconductor device according to claim 1, wherein the first second conductivity type semiconductor region has a portion provided between the second conductivity type collector region and the first conductivity type base contact region. 2. The high breakdown voltage semiconductor device according to claim 1, wherein the high breakdown voltage semiconductor device is separated from the one conductivity type base contact region. 3. The second conductivity type collector region and the second conductivity type collector region.
A second conductive type emitter region, which is formed between the conductive type emitter region and the second conductive type collector region, is spaced apart from the second conductive type collector region and is formed in contact with the second conductive type emitter region. 3. The high breakdown voltage semiconductor device according to claim 1, further comprising a second conductivity type semiconductor region. 4. The semiconductor region of the second second conductivity type has a portion provided between the emitter region of the second conductivity type and the base contact region of the first conductivity type. 4. The high breakdown voltage semiconductor device according to claim 3, wherein the high breakdown voltage semiconductor device is separated from the one conductivity type base contact region. 5. A second conductivity type emitter region and a second conductivity type collector region selectively formed on a surface of a first conductivity type semiconductor region, and separated from the second conductivity type emitter region and the collector region. A first conductive type base contact region selectively formed on a surface of the first conductive type semiconductor region; and a second conductive type collector region facing the second conductive type emitter region, and A high breakdown voltage semiconductor device, comprising: a first conductive type semiconductor region having a lower concentration than the second conductive type collector region and formed separately from the second conductive type emitter region. 6. The first conductivity type collector region of the first conductivity type.
The first second conductivity type semiconductor region is also formed in a portion facing the conductivity type base contact region, and the first second conductivity type semiconductor region is formed.
6. The high breakdown voltage semiconductor device according to claim 5, wherein the conductive type semiconductor region is separated from the first conductive type base contact region. 7. The second conductive type collector region, which is formed in contact with a portion of the second conductive type emitter region facing the second conductive type collector region and spaced apart from the second conductive type collector region.
7. The high breakdown voltage semiconductor device according to claim 5, further comprising a second second conductivity type semiconductor region having a lower concentration than the conductivity type emitter region. 8. The first conductivity type emitter region of the first conductivity type emitter region.
The second second conductivity type semiconductor region is also formed in a portion facing the conductivity type base contact region, and the second second conductivity type semiconductor region is formed.
8. The high breakdown voltage semiconductor device according to claim 7, wherein the conductive semiconductor region is separated from the first conductive base contact region. 9. The electric power according to claim 3, wherein the dose of the second second conductivity type semiconductor region is 4.0 × 10 ¹² cm ⁻² or less. For semiconductor devices. 10. The semiconductor device according to claim 1, wherein said first and second conductivity type semiconductor regions are doped.
Dose amount is 4.0 × 10 ¹²cm^-2Features are
The power semiconductor device according to claim 1, wherein: 11. A second conductivity type source region and a second conductivity type source region formed selectively on the surface of a first conductivity type active region provided on the same substrate as the first conductivity type semiconductor region. A conductive type drain region, formed between the second conductive type source region and spaced apart from the second conductive type source region, including between the second conductive type source region and the second conductive type drain region; And a third second conductivity type semiconductor region having a lower concentration than the second conductivity type drain region, and sandwiched between the third second conductivity type semiconductor region and the second conductivity type source region. 11. The high breakdown voltage semiconductor device according to claim 1, further comprising a gate electrode formed on a surface of said first conductivity type active region via a gate insulating film. 12. The second conductivity type collector region is formed so as to surround the second conductivity type emitter region except for a portion between the first conductivity type base contact region and the second conductivity type emitter region. The high withstand voltage semiconductor device according to claim 1, wherein: 13. The semiconductor device according to claim 1, wherein the semiconductor region of the first conductivity type is formed on an insulating region.
13. The high withstand voltage semiconductor device according to any one of claims 12 to 12. 14. A second conductivity type emitter region and a second conductivity type collector region selectively formed on a surface of a first conductivity type semiconductor region, and separated from the second conductivity type emitter region and the collector region. A first conductivity type base contact region selectively formed on a surface of the first conductivity type semiconductor region; and a first conductivity type between a second conductivity type collector region and the second conductivity type emitter region. A high withstand voltage semiconductor, comprising: a region for adjusting the width of a base region on the surface of the semiconductor region and relaxing an electric field between the collector region and the emitter region of the second conductivity type. apparatus.