JP2001102354A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a gate length of 0.1μm or smaller, as required, without using an advanced exposure technique and to restrain a short channel effect form occurring. SOLUTION: An element-forming layer 50 is formed on a semiconductor substrate 10. A V-shaped groove is provided to the element forming layer 50 through anisotropic etching, and metal is deposited for the formation of a gate 30. The V-shaped gate 30 is dug out as far as its tip, and the V-shaped gate 30 is made to serve as a point-contact Schottky gate. A source and a drain are formed through doping of impurities and deposition of an ohmic metal 80.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same. The present invention particularly relates to a semiconductor device having a gate and a method for manufacturing the device.

[0002]

2. Description of the Related Art Miniaturization of devices is one of the themes of semiconductor device manufacturing technology. A three-terminal semiconductor device having a gate, a source, and a drain electrode is one of the most basic devices at present, and the point of increasing the speed is to shorten the gate length. The shortening of the gate length is closely related to the exposure technique and the deposition technique for forming the gate electrode, for example, to shorten the exposure wavelength, use electron beam exposure, use the phase shift method, and perform oblique deposition. , And other methods are known, and improvements are being studied every day.

[0003]

However, even with such a method, the minimum value of the gate length which can be realized at present is about 0.1 μm. In order to realize a gate length smaller than this, further improvement such as an expensive exposure technique including a lens reduction projection exposure apparatus, that is, a stepper or the like is necessary, and the development cost and operation cost for that are generally large.

[0004] Even if the gate length is shortened, another problem of the short channel effect may occur. The short channel effect is caused by an overshoot of electrons, and the ratio Lg / a between the gate length Lg and the thickness a of the semiconductor operation layer, that is, the active layer, is expressed as

[0005] It becomes remarkable in the region of Lg / a <5. As a result, as an example, Vds (voltage between source and drain) -Id in the case of a common source.
In the s (drain current) characteristics, the gate voltage (Vg
The saturation characteristics of Ids for s) deteriorate.

Incidentally, Solid-State Electronics Vol. 41,
No. 10, pp. 1599-1604, 1997 (Elsevier Science Lt
d.) published in "HIGH POWER-ADDED EFFICIENCY AND L
OW DISTORTION GaAs POWER FET EMPLOYING SPIKE-GATE
STRUCTURE "discloses a GaAs power field effect transistor having a structure called a spike gate. The spike gate has a point called a spike recess on a part of the bottom surface of a normal gate metal called a fringe gate. According to this paper, the gate length can be reduced by providing spike recesses.
And However, in reality, the gate length is not defined by the spike recess tip, but rather by a wide fringe gate having a width of about 1.0 μm.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique for reducing a gate length without using an advanced exposure technique. Another object of the present invention is to provide a technique for suppressing a short channel effect. This object is achieved by a combination of features described in the independent claims. And the dependent
It defines specific and useful aspects of the present invention.

[0008]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step for preparing an element on a semiconductor substrate; and an opening in a region where a gate is to be formed on the semiconductor substrate. A second step of forming a protective film having a mask, a third step of forming a groove for forming a gate having a narrower tip by anisotropic etching using the protective film as a mask, and depositing a Schottky metal in the groove. And a fifth step of performing isotropic etching toward the tip of the gate.

In the first step, a semiconductor substrate may be simply prepared, or a layer for forming an element (hereinafter, referred to as an “element forming layer”) may be provided on the substrate.

The groove may be V-shaped, and the semiconductor active layer and the gate may be a point contact Schottky junction. The isotropic etching may be performed until the top of the V-shape is reached. The groove may be trapezoidal, and the isotropic etching may be performed until the bottom of the trapezoid is reached.

In the first step, a gate formation layer may be provided on the semiconductor operation layer. The gate forming layer may be a part of the above-described element forming layer. The gate forming layer is a layer for forming a gate, and has, for example, etching characteristics different from those of the semiconductor operation layer with respect to a predetermined etchant. Here, a material which is anisotropically etched by the etchant may be selected as a material of the gate forming layer, and a material of which etching by the etchant progresses slowly or does not progress may be selected as a material of the semiconductor operation layer. If the thickness of the gate forming layer is optimally set, a state where the tip of the groove comes into contact with the upper surface of the semiconductor operation layer as a result of the anisotropic etching is realized. Note that the upper surface of the semiconductor operation layer may be formed in a planar shape.

[0012] In the fifth step, the anisotropic etching may be further continued after reaching the semiconductor operation layer. In that case, the side etching proceeds, and the groove can be formed in a trapezoidal shape.

In the first step, an etching stop layer for stopping progress of the anisotropic etching may be formed between the semiconductor operation layer and the gate formation layer. This etch stop layer may be removed with a particular etchant or may remain.

In the first step, a thin layer having a high concentration of carriers may be formed in the semiconductor operation layer. This thin layer may be a 2DEG or a planar doping layer at the heterojunction.

In any one of the steps or another step to be added, a support structure for preventing the gate from falling down may be formed. This support structure can be realized, for example, by widening the opening of the gate region at a part of the gate, particularly at the end in the second step.

The present invention may further include the sixth and subsequent steps. For example, a protective film having openings in source and drain regions may be formed by photolithography, impurities may be implanted into the protective film, annealing may be performed, metal may be deposited, and source and drain electrodes may be formed.

On the other hand, a semiconductor device of the present invention includes a semiconductor operation layer having a planar surface, and a gate formed on the semiconductor operation layer. With this configuration, the gate is formed to have a thinner tip, and the tip is Schottky-joined to the surface of the semiconductor operation layer by point contact.

[0018] The semiconductor operation layer may include a thin layer in which carriers are present at a high concentration. In this layer, the semiconductor element of the present invention may further include a support structure for preventing the gate from falling down.

The above summary of the invention does not enumerate all the features required for the present invention, and it goes without saying that sub-combinations of these features can also constitute the invention.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the invention described in the claims, and all combinations of features described in the embodiments are indispensable for solving the invention. Not necessarily. First, the principle of the method for manufacturing a semiconductor device according to the embodiment will be described.

[0021]Basic principle  Semiconductor elements are often configured on a single crystal (100) plane.
No. One method of processing this surface is wet etching
There is a bug. Wet etching has no relation to plane orientation
Isotropic etching that progresses at a rate and plane orientation
There is anisotropic etching with different rates. Anisotropic edge
Chant is, by its nature, etching related to plane orientation.
The rate must be (100) plane ≫ (111) plane
You.

Further, as for the compound semiconductor, the anisotropic etchant has an etching rate (1
11) A surface {(111) B surface or (111) A surface}
It must be (111) B-plane. In either case,
It is desirable that the etching rate of the (111) plane be sufficiently low from the viewpoint of controllability.

By using such an anisotropic etchant, it is possible to form a V-shaped groove in the [110] direction. The plane of the V-shaped groove is the (111) plane, which forms an angle of 54.7 ° with the (100) plane.

[First Step] Preparation for forming an element on a semiconductor substrate is made. When an element is formed directly on a semiconductor substrate, this step is sufficient if a semiconductor substrate is simply prepared.

[Second Step] FIGS. 1A and 1B show the results obtained by the second step. In the second step, the (100) surface of the semiconductor substrate 10 is subjected to photolithography. As a result, as shown in FIG. 1A, a predetermined direction is set in the [011] direction, that is, perpendicular to the orientation flat 14, or in the [01-1] direction (-represents a bar on the number), that is, in parallel to the orientation flat 14. A photoresist pattern having an opening 16 having a width LG and a length Wg is provided. The predetermined width LG corresponds to the upper end, that is, the width of the widest part when a V-shaped groove or a trapezoidal groove is formed later. The length Wg corresponds to the gate width Wg. The photoresist is lifted off after depositing the Schottky metal later.

[Third Step] FIGS. 2 (a), 2 (b) and 2 (c)
Indicates the result obtained in the third step. In the third step, the semiconductor substrate 10 and the photoresist 1
For V, a V-shaped or trapezoidal groove 20 is formed by an anisotropic etchant. When the width LG of the opening 16 is 1 μm, the depth d to the top of the V-shaped groove 20 is about 0.70
6 μm. Both sides of the groove are (111) planes. If the anisotropic etching is completed before the groove 20 becomes V-shaped,
A trapezoidal groove 20 having a (100) bottom is formed. Since the width of the bottom surface (100) decreases with the elapse of the etching time, the gate length can be controlled. FIG.
(A) shows the complete V obtained by performing the etching to the end.
1 shows a U-shaped groove 20. 2B and 2C show trapezoidal grooves 20 obtained by stopping the etching at different timings.

[Fourth Step] FIGS. 3A and 3B and FIGS. 4A and 4B show the results obtained by the fourth step. FIGS. 3A and 3B show a state in the middle stage and the last stage of the fourth step, respectively, when the groove 20 is V-shaped. FIGS. 4A and 4B show a state in a middle stage and a final stage of the fourth step, respectively, when the groove 20 is trapezoidal. In a fourth step, a Schottky metal 22 is deposited on the photoresist 12. This allows
3A and FIG. 4A. Subsequently, the photoresist 12 is lifted off, and FIG. 3B and FIG.
State. This completes the preparation for forming the gate.

[Fifth Step] FIGS. 5A and 5B show the results obtained by the fifth step. FIG. 5A corresponds to the case where the groove 20 is V-shaped, and FIG. 5B corresponds to the case where the groove 20 is trapezoidal. In a fifth step, the (100) semiconductor surface is etched with an isotropic etchant. The amount of etching is up to the depth of the V-shaped or trapezoidal groove. Thus, a Schottky gate 30 is formed. In the case of FIG.
A point-contact Schottky gate whose gate length is considered to be substantially zero is formed. In the case of FIG. 5B, a desired gate length can be realized relatively easily.

The above is the outline of each step. The following changes are considered to further simplify the management of the anisotropic and isotropic etching rates. First, as a modification of the first step, a dedicated layer for forming an element on the semiconductor substrate 10, that is, an element formation layer is provided.

FIGS. 6A and 6B show the results obtained through the second and third steps after the element formation layer 50 is formed in the first step. FIG. 6A shows a case where the groove 20 is V-shaped.
FIG. 6B corresponds to the case of a trapezoid. An element formation layer 50 is provided on the semiconductor substrate 10.

As the element formation layer 50, the semiconductor operation layer 34
Then, a gate forming layer 32 specialized for the purpose of digging the V-shaped or trapezoidal groove 20 is further provided thereon by epitaxial growth. In this case, as the anisotropic etchant used in the third step, a material having an etching rate of “the gate formation layer 32 divided by the semiconductor operation layer 34” or a material not etching the semiconductor operation layer 34 is selected. At this time, if the etching is further advanced after the V-shaped groove 20 is formed, the (111) plane is side-etched, and the trapezoidal groove 20 is obtained.

As another modification of the first step, an etching stop layer may be further provided. FIGS. 7A and 7B show the results obtained after the etching stop layer 36 is formed in the element formation layer 50 in the first step and then the second step and the third step. FIG. 7A shows a case where the groove 20 is V-shaped.
Corresponds to the case of a trapezoid. An etching stop layer 36 is provided between the semiconductor operation layer 34 and the gate formation layer 32 by epitaxial growth. The etching stop layer 36 is located at a position where the apex of the V-shaped groove 20 or the bottom of the trapezoidal groove 20 is in contact therewith. In the fifth step, the entire surface is etched with a specific isotropic etchant. Etching stops at the etch stop layer 36. The introduction of the etching stop layer 36 makes it easier to control the etching rate or manage the etchant.

As a further modification of the first step, another layer is added to suppress the above-mentioned short channel effect. As described above, the short channel effect is caused by the ratio of the gate length Lg to the semiconductor active layer thickness (active layer thickness) a Lg /
This becomes significant as a becomes smaller. Therefore, the gate length L
As g decreases, the thickness a must also be reduced. However, reducing the thickness a reduces the current. If a high-concentration carrier layer is formed to compensate for this, high-speed operation is hindered due to a decrease in breakdown voltage and a decrease in carrier mobility.

In order to solve these problems, an LH junction by planar doping, also called δ doping, is realized in the semiconductor operation layer 34 in the first step. By the planar doping, a decrease in the Lg / a aspect ratio can be suppressed. That is, the mobility of the L region of the LH junction is high due to the low carrier concentration, and the mobility of the H region is low due to the high carrier concentration. However, exudation of carriers occurs from the H region to the L region by the Debye length, and the exuded carriers have high mobility and can maintain high-speed operation. In addition, HEMT
(High electron mobility transistor) satisfies this condition structurally, and the structure can be incorporated in the semiconductor element manufacturing stage of the embodiment.

[0035]Example  Each step will be described in more detail based on the above principle. This
Here, the GaAs Schottky gate FET of the present invention is used.
(MESFET: Metal Semiconductor Field Effect T
ransistor).

The information on the etching used in the embodiment is as follows. First, a citric acid-hydrogen peroxide system is used as an anisotropic etchant. The temperature of the etchant is set to about 5 ° C. using a cooler. The following values were obtained by preliminary experiments as the etching rate at this temperature.

GaAs (100) plane: 25 Å / sec GaAs (111) A plane: 10 Å / sec GaAs (111) B plane: 0.1 Å / sec Since the etching rate of the (111) B plane is extremely small, The etching of the (100) substrate is limited by the etching rate of the (111) B surface. As a result, this surface appears as an etched surface. Therefore, [011],
The etched section in the [011] direction becomes a V-shaped groove.

Note that AlAs is an example of a material that is not etched by a citric acid-hydrogen peroxide-based etchant. For this reason, this is used for the etching stop layer 36 in the embodiment. The AlAs layer itself can be removed with hydrofluoric acid.
A phosphoric acid-hydrogen peroxide-based etchant is used for isotropic etching. There was no need to control the temperature of this etchant.

[First Step] As the semiconductor substrate 10, semi-insulating GaAs (100) is used. Here, the semiconductor substrate 1
A layer for forming a target element, that is, an element formation layer 50 is provided on the element 0. The element formation layer 50 is formed on the semiconductor substrate 1.
0 is epitaxially grown. Crystal growth is performed by ordinary solid source molecular beam epitaxy (MBE).
Performed by

In the element forming layer 50, a substantially rectangular parallelepiped region where elements are actually provided (hereinafter referred to as an element region 50a)
Decide. Subsequently, portions other than the element region a are removed by photolithography by mesa etching until the semiconductor substrate 10 is exposed.

FIGS. 8A, 8B and 8C show the results obtained by the first step of this embodiment. FIG. 8A,
(B) and (c) show the configuration of the semiconductor substrate 10 and the element formation layer 50, the upper surface and the cross section of the element region 50a formed by mesa etching, respectively. Element region 50a
Are set to 200 × 100 μm.
The element forming layer 50 has the following material, carrier concentration, and film thickness in the order far from the semiconductor substrate 10, that is, in order from the top in the figure.

[0042]

[Table 1] The non-doped GaAs layer 40 and the Si planar doping layer 42 constitute the semiconductor operation layer 34. The thickness d1 of the gate forming layer 32 is about 54.7 ° and the width LG of the opening 16 for forming the gate = 1 μm to about 0.70 μm.
It is determined to be 6 μm.

A phosphoric acid-hydrogen peroxide system is used as an etchant for mesa etching for providing the element region 50a. The etching amount L3 is about 2 μm, and the measurement is performed using a stylus type step difference type.

[Second Step] An SiO insulating film is formed as a protective film. By plasma CVD (chemical vapor deposition)
SiO is deposited on the entire surface including the element region 50a. Subsequently, an opening is formed by etching so as to surround the element region 50a. FIGS. 9A and 9B show an upper surface and a cross section of the SiO insulating film 52 provided with the opening 56 and the element region 50a, respectively. The dimension L4 × L5 of the opening is 202 × 102 μ
m.

Next, a photoresist is applied to the entire surface,
The opening 16 is provided so that the longitudinal direction of the gate coincides with the [011] direction.

FIG. 10 shows the upper surface of the photoresist 12 provided with the opening 16. In the same figure, the shaded area on the lower left indicates the existence area of the photoresist 12, and the shaded area on the lower right indicates the existence area of the SiO insulating film 52 surrounding the element area 50a. In this example, the number of gates is two, the dimension LG × Wg of the opening 16 for forming the gate is 1 μm × 100 μm, and the gate interval Wa is 100 μm. The opening 16 in the photoresist 12 includes a pad portion 60 for an extraction electrode and a column portion 62 that supports a gate that will later become V-shaped.

[Third Step] In order to form the V-shaped groove 20, anisotropic etching is performed using a citric acid-hydrogen peroxide based etchant. The GaAs (10
Since the etching rate of the 0) plane is 25 angstroms / sec, the time for etching all the GaAs (100) of about 0.7 μm is less than 5 minutes. Here, GaA
Since the etching rate of the s (111) B surface is extremely slow and the etching stop layer 36 of AlAs stops the etching, a longer etching for 10 minutes was performed.

At this time, the column portion 62 of the V-shaped gate,
As shown in FIG. 10, the pad portion 60 for the extraction electrode is not etched by the underlying SiO insulating layer 52. Due to the pillar portion formed for that purpose, V
The U-shaped groove 20 can be supported. Subsequently, the etching stop layer 36 immediately below the gate is removed with hydrofluoric acid. FIG. 11 shows a cross section near the removed portion 62 of the formed V-shaped groove 20 and the etching stop layer 36.

[Fourth Step] The target is WSix (x =
0.6) Sputtering the entire surface as a eutectic alloy,
A Schottky metal 22 is deposited. Thereafter, the photoresist 12 is lifted off, leaving the Schottky metal 22 only at the V-shaped gate. FIG. 12 shows a cross section near the V-shaped gate thus formed.

[Fifth Step] The gate forming layer 32 is
Etching is performed using a hydrogen peroxide-based etchant. The etching is stopped at the etching stop layer 36 of AlAs. Subsequently, the etching AlAs layer 36 itself is removed with hydrofluoric acid.

FIGS. 13 (a) and 13 (b) show a cross section near the V-shaped gate 30 thus formed and a state in which the support portion 62 is viewed obliquely. However, in FIG. 13B, the pad portion 60 is omitted. As can be seen from this figure, the V-shaped gate can be supported by the support portion 60.

[Sixth Step] An SiO insulating layer 70 is deposited on the entire surface by plasma CVD, and an opening 72 is provided in the operating region of the element including the source and the drain by a photolithography step. FIG. 14 shows the opening 72 thus provided.
The upper surface of FIG. The opening 72 includes a rectangular area and an element operation area, and the dimension L6 × L7 of the rectangular area is 198 × 98 μm.

[Seventh Step] Si ions are implanted to form a source and a drain. The implantation conditions were an acceleration voltage of 20 kV and a dose of 1 × 10 ¹³ cm ⁻² . Thereafter, a heat treatment at 850 ° C. for 20 seconds (RTA: Rapid Ther
mal Annealing).

Next, AuGe / Ni / Au is deposited on the entire surface, and the photoresist provided in the sixth step is lifted off to form source and drain electrodes. After this, 400
An ohmic alloy layer is formed by performing heat treatment at a temperature of 1 minute.

FIG. 15 shows a cross section near the source / drain ohmic electrode 80 thus formed. The Si ion-implanted n ⁺ GaAs layer 82 is formed on the Si planar doping layer 42. Gate length Lg shown in the figure
Can be close to zero. Therefore, the original purpose of shortening the gate length is achieved.

On the other hand, a Si ion implanted n ⁺ GaAs layer 82
Corresponds to the L region of the LH junction, and the Si planar doping layer 42 corresponds to the H region. In this configuration, the thickness a of the semiconductor operating layer can be considered substantially as the thickness of the Si planar doping layer 42, and therefore the value of a is extremely small. Therefore, the aspect ratio Lg / a is reduced, and
The channel effect can be suppressed.

[Eighth Step] In order to protect the surface, SiO is deposited on the entire surface by plasma CVD to provide a passivation film. Further, contact holes are provided at predetermined positions on the source, the drain, and the gate by a photolithography process, and Ti / Au is deposited on the entire surface. Thereafter, lift-off, formation of bonding pads, and wiring are performed.

Although the embodiments have been described above, the technical scope of the present invention is not limited to these descriptions. It is understood by those skilled in the art that various changes or improvements can be made to these embodiments. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

[0059]

According to the present invention, 0.1 μm is relatively inexpensive.
A gate length of less than m is realized. According to an embodiment of the present invention, the short channel effect is suppressed.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing results obtained by a second step of the basic principle of the embodiment.

FIGS. 2A, 2B, and 2C are diagrams showing results obtained by a third step of the basic principle of the embodiment.

FIGS. 3 (a) and 3 (b) are diagrams showing results obtained by a fourth step of the basic principle of the embodiment, particularly for a V-shaped groove.

FIGS. 4A and 4B are diagrams showing the results obtained by a fourth step of the basic principle of the embodiment, particularly for trapezoidal grooves.

FIGS. 5A and 5B are diagrams showing results obtained by a fifth step of the basic principle of the embodiment.

FIGS. 6A and 6B are diagrams showing results obtained through a second step and a third step after forming an element formation layer in a first step.

FIGS. 7A and 7B are diagrams showing results obtained through a second step and a third step after forming an etching stop layer in addition to an element formation layer in a first step. .

FIGS. 8A, 8B, and 8C relate to the first step of the embodiment, showing the configuration of a semiconductor substrate and an element formation layer, the upper surface of an element region formed by mesa etching, and a cross section, respectively. FIG.

FIGS. 9A and 9B are a top view and a sectional view of an SiO insulating film and an element region provided with openings, respectively, in a second step of the embodiment.

FIG. 10 is a top view showing a relationship between a photoresist provided with an opening for forming a gate and a SiO insulating film formed before the photoresist in a second step of the example.

FIG. 11 is a cross-sectional view of a V-shaped groove formed in a third step of the example and a vicinity of an etched stop layer removed.

FIG. 12 is a view showing a state in which the Schottky metal is left only in the V-shaped groove portion by the fourth step of the example.

FIGS. 13A and 13B are a cross-sectional view of the vicinity of a V-shaped gate 30 formed in a fifth step of the embodiment and a perspective view of the V-shaped gate 30 and a column.

FIG. 14 is a top view of an opening provided in a sixth step of the example.

FIG. 15 is a sectional view showing the vicinity of an ohmic electrode provided in a seventh step of the example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Photoresist 16,56,72 Opening 20 Groove 22 Schottky metal 30 Gate 32 Gate formation layer 34 Semiconductor operation layer 36 Etch stop layer 40 GaAs layer 42 Si planar doping layer 44 GaAs buffer layer 50 Element formation layer 50a Element region 52, 70 SiO insulating film 60 Pad part for extraction electrode 62 Support part 70 SiO insulating layer 80 Source / drain ohmic electrode 82 Si ion implanted n ⁺ GaAs layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/417 H01L 29/50 J 29/812

Claims (14)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: a first step of preparing for forming an element on a semiconductor substrate; and a protection method having an opening in a region where a gate is to be formed on the semiconductor substrate. A second step of forming a film, a third step of forming a groove for forming a gate having a narrower tip by anisotropic etching using the protective film as a mask, and depositing a Schottky metal in the groove to form the gate. A fourth step of forming a gate; and a fifth step of performing isotropic etching toward the tip of the gate.
A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the groove has a V-shaped cross section, and the semiconductor active layer and the gate are formed as a point contact Schottky junction. 3. The method according to claim 2, wherein the isotropic etching is performed until the top of the V-shape is reached. 4. The method according to claim 1, wherein the groove has a trapezoidal cross section, and the isotropic etching is performed until the groove reaches the bottom of the trapezoid. 5. The method according to claim 1, wherein the first step comprises:
The layer for forming the gate, wherein a gate forming layer having an etching characteristic different from that of the semiconductor operation layer with respect to a predetermined etchant is formed. A method for manufacturing a semiconductor device. 6. A material that is anisotropically etched by the etchant is selected as a material of the gate forming layer,
6. The method according to claim 5, wherein the material of the semiconductor operation layer is selected so that the etching by the etchant progresses slowly or does not progress. 7. The thickness of the gate forming layer is set such that a tip of the groove contacts an upper surface of the semiconductor operation layer as a result of the anisotropic etching.
The method for manufacturing a semiconductor device according to any one of the above. 8. The method according to claim 5, wherein, in the fifth step, the groove is formed in a trapezoidal shape even after reaching the semiconductor operation layer. A method for manufacturing a semiconductor device according to the above. 9. The method according to claim 5, wherein in the first step, an etching stop layer for stopping progress of the anisotropic etching is formed between the semiconductor operation layer and the gate formation layer. The method for manufacturing a semiconductor device according to any one of the above. 10. The manufacturing of a semiconductor device according to claim 5, wherein in the first step, a thin layer having a high concentration of carriers is formed in the semiconductor operation layer. Method. 11. The method according to claim 1, further comprising a supporting structure for preventing the gate from falling down. 12. A semiconductor element, comprising: a semiconductor operation layer having a planar surface; and a gate formed on the semiconductor operation layer, wherein the gate has a thinner tip. A semiconductor element, wherein the tip forms a Schottky junction with the surface of the semiconductor operation layer by point contact. 13. The semiconductor operation layer according to claim 12, wherein the semiconductor operation layer includes a thin layer having a high concentration of carriers.
A semiconductor device according to item 1. 14. The apparatus according to claim 12, further comprising a support structure for preventing the gate from falling down.
The semiconductor device according to any one of the above.