JP2001101880A - Writing method for nonvolatile semiconductor memory device - Google Patents

Abstract

(57) Abstract: A self-boost technique is applied to a so-called AND-type memory cell array to reduce the number of bias application points higher than a power supply voltage as much as possible. A first voltage (0V) is set to a selected main bit line BL1, a second voltage (1.5V) is set to a non-selected main bit line BL2, and a first selection transistor S11,
With S21 turned on and the second selection transistors S12 and S22 turned off, a first intermediate voltage (4.5 to 7V) for forming a channel is applied to the memory transistors M11 and M21 connected to the selected word line WL1. Then, the second intermediate voltage (4.5 V) is applied to the non-selected word lines WL2, and the selected word line voltage is changed from the first intermediate voltage to a higher write voltage (11V). The second intermediate voltage is applied to the non-selected memory transistor M22 after the application due to the relationship between the potential of the sub-bit line SBL2 and the potential of the sub-source line SSL2 at the time of application.
ＭM2128 is set to a value at which no channel is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a writing method for a NOR type nonvolatile semiconductor memory device in which a common potential line connecting a source or a drain of a memory transistor is hierarchized.

[0002]

2. Description of the Related Art In a so-called NAND type nonvolatile memory, as a technique for eliminating the need for a high voltage to be applied to an unselected bit line at the time of writing and reducing the load on a booster circuit,
A so-called self-boost technique is known.

FIG. 10 is a diagram for explaining a write operation by a self-boost operation of a NAND nonvolatile memory.

In the NAND type nonvolatile memory of FIG. 10, between the bit line BLa and the supply line of the reference potential VSS, a large number of memory transistors MT1a to MT4 are shown via select transistors ST1a and ST2a.
a is connected in series. Similarly, a select transistor ST is provided between the bit line BLb and the supply line of the reference potential VSS.
Many, in the figure, four memory transistors MT1b to MT4b are connected in series via 1b and ST2b. Select transistors ST1a and ST1b are controlled by select gate line SL1, and select transistors ST2a and ST2b are controlled by select gate line SL2. Further, the memory transistors MT1a to MT4a and MT
1b to MT4b are controlled by word lines WL1 to WL4, respectively.

Next, in the NAND type nonvolatile memory shown in FIG. 10, when the page write is performed by selecting the word line WL2, the memory transistor MT must be written.
2a, and the operation in the case where the write should be inhibited is the memory transistor MT2b will be described. In addition,
The voltage condition here indicates a case where the memory transistor is of the FG type.

First, the power supply voltage V _{CC is} applied to the selection gate line SL1.
(3.3 V), the ground voltage GND is applied to the select gate line SL2.
(0 V) is applied to the selected memory transistor MT2a.
Is connected to the bit line BLa to which the ground voltage GND (0
V), the power supply voltage V _CC (3.3 V) is applied to the bit line BLb to which the unselected memory transistor MT2b is connected. Next, the write voltage Vpg is applied to the selected word line WL2.
m (for example, 18 V) is set to the unselected word lines WL1, WL
A pass voltage Vpass (for example, 10 V) is applied to 3-WL4.

As a result, the non-selected memory transistor MT
The channel portion of the transistor row to which 2a is connected is in a floating state, and the potential of the channel portion is boosted mainly by capacitive coupling with a pass voltage Vpass applied to an unselected word line, and a write inhibit voltage (for example, about 8 V at the maximum) ) To prohibit writing to the memory transistor MT2b. On the other hand, the channel portion of the transistor row to which the selected memory transistor MT2a is connected is set to the potential of the ground voltage GND (0 V),
The writing to the memory transistor MT2a is performed by the potential difference from the writing voltage Vpgm applied to the selected word line, and the threshold voltage shifts in the positive direction, for example, from -3V in the erased state to about 2V.

[0008] In this way using a self-boosting technique for automatically boosting the channel of the unselected transistors column until the write inhibit voltage separately from the bit line, can be advantageously reduced bit line voltage to the power supply voltage of about V _CC is there.

[0009]

However, when this self-boost technique is applied as it is to the writing of a parallel-connected NOR type memory cell array represented by an AND type in which source lines and bit lines are hierarchized, There is a problem that the voltage applied to a common potential line such as an unselected bit line cannot be reduced, and the benefit of applying the self-boost technique cannot be obtained much.

It is an object of the present invention to apply a self-boost technique to reduce the number of bias application points higher than the power supply voltage as much as possible.
An object of the present invention is to provide a writing method for an R-type nonvolatile semiconductor memory device.

[0011]

According to a first aspect of the present invention, there is provided a method of writing data in a nonvolatile semiconductor memory device, comprising the steps of:
And a second selection transistor; a sub-bit line connected to the main bit line via the first selection transistor; a sub-source line connected to the main source line via the second selection transistor; Nonvolatile memory having a plurality of memory blocks each including a plurality of memory transistors connected in parallel between a memory cell line and the sub-source line, and further having a plurality of word lines commonly connecting gates of the memory transistors between different memory blocks. A first voltage is connected to a main bit line to which a first memory block including a selected memory transistor to be written is connected, and a second memory block not including a selected memory transistor is connected to the main bit line. The main bit line
A second voltage higher than the voltage is set, and the selected memory transistor is connected in a state where the first selection transistor is turned on and the second selection transistor is turned off in the first and second memory blocks. Applying a first intermediate voltage for forming a channel to a memory transistor connected to the selected word line to a selected word line, and applying a second intermediate voltage to non-selected word lines other than the selected word line; The voltage applied to the selected word line is
The voltage is changed from the intermediate voltage to a higher write voltage.

Preferably, the second intermediate voltage applied to the gate of the non-selected memory transistor is related to the potential of the sub-bit line and the sub-source line at the time of the application, and after the application, the second intermediate voltage is The value is set so that no channel is formed in the memory transistor. Preferably, a voltage equal to or lower than the sum of the threshold voltage of the first selection transistor and the second voltage is applied to the gate of the first selection transistor.

Preferably, the second voltage is lower than a write inhibit voltage which is a final voltage after the sub-bit line and the sub-source line are boosted by application of the second intermediate voltage.
Preferably, the first intermediate voltage is lower than a write start voltage at which electrons start to tunnel-inject electrons in a gate direction from a channel formed by a memory transistor having the gate applied with the first intermediate voltage. Preferably, a voltage obtained by subtracting the write inhibit voltage from the write voltage is a write start voltage at which electrons start to be tunnel-injected in a gate direction from a source or a drain of a memory transistor connected to the selected word line in the second memory block. Lower than voltage.

In the writing method of the nonvolatile semiconductor memory device according to the first aspect, for example, when the memory transistor is a MONOS type, the main bit line to which the first memory block including the selected memory transistor is connected as described above. Is set to a first voltage (eg, ground potential), and a second voltage (eg, 1.5 V) is set to a main bit line to which a non-selected second memory block is connected, and a second selection transistor in each block is set. Is turned off, a first intermediate voltage (for example, 4.5 to 7 V) is applied to the selected word line. Then, the memory transistors in each block connected to the selected word line are turned on, and a channel is formed. Therefore, the sub bit line and the sub source line are maintained at the same potential thereafter. Note that the memory transistor is not written by the potential difference between the potentials of the sub-bit line and the sub-source line and the first intermediate voltage.

Next, second non-selected word lines are
An intermediate voltage (for example, 4.5 V) is applied. Then, the potentials of the sub-bit line and the sub-source line are boosted in the second memory block while the non-selected memory transistors remain in the off state. At the time when this boost starts or not, the first transistor in the second memory block is cut off and disconnected from the main bit line. Therefore, thereafter, the potentials of the sub-bit line and the sub-source line, which are capacitively coupled to the non-selected word lines having a large number, rapidly rise to reach a predetermined write inhibit voltage. Therefore, the selected word line is switched from the first intermediate voltage to a predetermined write voltage (for example, 11
Even when the voltage is increased to V), the non-selected memory transistor in the second memory block is not written.

On the other hand, by applying the write voltage, for the selected memory transistor in the first memory block, the write voltage is applied between the channel and the gate electrode, and electrons are charged from the entire surface of the channel to the charge storage means (carrier trap). ), And writing is performed.

In this writing method, since the voltage application to the selected word line is performed in two stages, the voltage of the non-selected main bit line can be set low, and accordingly, the gate application voltage of the first selection transistor can be reduced. In addition, since the non-selected memory transistor is boosted in the off state in the second memory block, the final write inhibit voltage can be set higher with higher efficiency than the boost after channel formation as performed in the NAND type. .

According to a second aspect of the present invention, there is provided a writing method for a nonvolatile semiconductor memory device, comprising: a first and a second selection transistor; and a sub-bit line connected to the main bit line via the first selection transistor. A sub-common potential line connected to the main common potential line via the second selection transistor;
A plurality of memory blocks each including a plurality of memory transistors connected in parallel between the sub-bit line and the sub-common potential line, and a word line commonly connecting the gates of the memory transistors between different memory blocks. A writing method for a nonvolatile semiconductor memory device having a plurality of nonvolatile memory devices, wherein a first voltage is applied to a main bit line connected to a first memory block including a selected memory transistor to be written, and a second memory block not including the selected memory transistor. Are set to a main bit line to which a second voltage higher than the first voltage is set, and a third voltage is set to the main common potential line, respectively, and the first voltage is set in the first and second memory blocks.
In a state where the selection transistor is turned off and the second selection transistor is turned on, a first intermediate of a value forming a channel with the memory transistor connected to the selected word line is connected to the selected word line connected to the selected memory transistor. Applying a second intermediate voltage to a non-selected word line other than the selected word line, changing the applied voltage of the selected word line from the first intermediate voltage to a higher write voltage, , The first selection transistor in the first memory block is turned on at the gate of the first selection transistor in the second memory block in accordance with the potential difference between the first and second voltages, and the first selection transistor in the second memory block is turned on. One selection transistor applies a voltage that maintains the OFF state.

Preferably, the second intermediate voltage applied to the gate of the non-selected memory transistor is related to the potential of the sub-bit line and the sub-source line at the time of the application, and after the application thereof, The value is set so that no channel is formed in the memory transistor.

Preferably, a voltage equal to or lower than the sum of the threshold voltage of the second selection transistor and the third voltage is applied to the gate of the second selection transistor. Preferably, the third voltage is lower than a write inhibit voltage which is a final voltage after the sub-bit line and the sub-source line are boosted by application of the second intermediate voltage.

In the second writing method, after setting the first and second voltages on the main bit line, similarly to the writing method (first method) according to the first aspect, the second writing method differs from the first method. A positive voltage (third voltage, for example, 1.5 V) is set in a main source line (here, a main common potential line).
Then, the second transistor is turned on, and the third voltage is applied to the sub-source line (here, referred to as a sub-common potential line) by the third voltage.
Is set to a predetermined potential (for example, 1 V).

Next, the predetermined potential is transmitted to the sub-bit line by turning on the memory transistor connected to the selected word line, as in the first method. In addition, self-boost is performed by applying the same voltage as in the first method. In the self boost, unlike the first method, the voltage is boosted not only in the second memory block but also in the first memory block.

Finally, first, the first
The electric charge of the sub-bit line and the sub-common potential line only on the memory block side is drawn to the main bit line side, and the potential is reduced to almost the ground potential. Specifically, the first selection transistor of the first memory block is turned on at the gate of the first selection transistor in accordance with the first set potential difference between the first and second voltages, and the first selection transistor of the second memory block is turned on. Is applied so as to maintain the OFF state. As a result, a predetermined write voltage (11 V) is applied to the select transistor on the first memory block side,
Writing is performed.

In the second method, since the voltage application to the selected word line is performed in two stages, the voltage of the main common potential line can be set small, and accordingly, the voltage applied to the gate of the second selection transistor can be reduced. Further, similarly to the first method, since the boost is performed while the unselected memory transistor is in the off state, the boost efficiency is high, and the final write inhibit voltage can be set high.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 shows a main circuit configuration of a nonvolatile memory device according to an embodiment of the present invention.

In this NOR type memory cell array, bit lines are hierarchized into main bit lines and sub-bit lines, and source lines are hierarchized into main source lines and sub-source lines. The sub-bit line SBL1 is connected to the main bit line MBL1 via the selection transistor S11, the sub-bit line SBL2 is connected to the main bit line MBL2 via the selection transistor S21, and the sub-bit line SBL2 is connected to the main bit line MBLn via the selection transistor Sn1. The bit line SBLn is connected. The sub-source line SSL1 is connected to the main source line MSL via the selection transistor S12, and the selection transistor S2
2, the sub-source line SSL2 is connected, and the select transistor Sn2 is connected to the sub-source line SSLn.

The sub bit line SBL1 and the sub source line SSL1
, The memory transistors M11 to M1m are connected in parallel, the memory transistors M21 to M2m are connected in parallel between the sub-bit line SBL2 and the sub-source line SSL2, and the sub-bit line SBLn and the sub-source line SSLn are Between them, the memory transistors Mn1 to Mnm are connected in parallel. These memory transistors are MONOS type memory transistors in which a gate electrode is formed on a semiconductor substrate or well via a three-layer insulating film of a tunnel insulating film, a nitride film, and a top insulating film, as described in detail later. . The n memory transistors connected in parallel to each other and two selection transistors (S11 and S12, S11
21 and S22 or Sn1 and Sn2) constitute a unit block (memory block) constituting the memory cell array.

Each gate of the memory transistors M11, M21,..., Mn1 adjacent in the word direction is connected to the word line WL.
1 connected. Similarly, the memory transistor M1
, M22,..., Mn2 are connected to the word line WL2, and the memory transistors M1n, M2n,.
, Mnm are connected to the word line WLn. Select transistors S11, S adjacent in the word direction
, Sn1 are controlled by a select gate line SG1, and select transistors S12, S22,..., Sn2 are controlled by a select gate line SG2.

Next, a writing method and operation of the NOR type memory cell array having such a configuration will be described. FIG.
The following shows an example of the bias setting in this writing method. Also,
FIG. 3 shows a waveform diagram of a voltage change of each signal line. here,
The case where the memory transistor M11 shown in FIG. 2 is written will be described as an example. A memory block including the selected memory transistor M11 is referred to as a “selected memory block”, and a memory block not including the selected memory transistor M11 is referred to as a “non-selected memory block”.

First, as shown in FIG. 3F, the main bit line MBL1 connected to the selected memory block is held at the ground potential (first potential), and the main bit line MBL2 connected to the unselected memory block is held. Is set to a second voltage of, for example, 1.5V. At this time, the select gate lines SG1 and SG2 and all word lines are held at the ground voltage. Therefore, the first and second selection transistors in each memory block are off.

Next, at the timing of t1 shown in FIG.
As shown in FIG. 2A, a voltage of, for example, 1.5 V (hereinafter, referred to as a first selection gate voltage) is applied to the selection gate line SG1, and the first selection transistors S11 and S21 are applied.
Turn on. This select gate voltage is a voltage equal to or lower than a voltage obtained by adding the second voltage to the threshold voltage of the first select transistor. This is a condition for determining whether or not the selection transistor can be cut off. That is, in the unselected memory block, the first selection transistor S21
The potential at the connection point with the sub-bit line is obtained by subtracting the threshold voltage (0.5 V) from the first selection gate voltage (1.5 V).
Cut off when it reaches V. On the other hand, in the selected memory block, the voltage obtained by subtracting the threshold voltage (0.5 V) from the first selection gate voltage (0 V) is negative, and the potential of the sub-bit line is boosted and changes only in the positive direction. Therefore, the first selection transistor S11 does not cut off. As shown in FIG. 3 (H), the first select transistor S11 causes the sub-bit line SBL2 to generate 1V due to the second voltage.
When the battery is fully charged, the transition to a boundary area (cutoff area) as to whether or not the cutoff is performed is maintained.

At substantially the same time t1 as the application of the first selection gate voltage, as shown in FIG.
1 is applied with a first intermediate voltage (for example, 4.5 to 7 V). Then, the memory transistors M11 and M21 in each block connected to the selected word line WL1 turn on,
A channel is formed. Therefore, at this point, the sub-bit line and the sub-source line are short-circuited, and a potential of 1 V is transmitted to the sub-bit line SBL as shown in FIG. The value of the first intermediate voltage is a condition that the memory transistors M11 and M21 are not written with a potential difference from the sub bit line SBL or the sub source line SSL. This is because the unselected memory transistor M21 is not erroneously written.

Thereafter, as shown in FIGS. 3C and 3D, at the timing of time t2, the unselected word line WL2
ＷＬWL128 to apply a second intermediate voltage (eg, 4.5 V) and change the potential of the selected word line WL from the first intermediate voltage to a write voltage (eg, 11 V). Then, the potentials of the sub-bit line SBL2 and the sub-source line SSL2 start to be boosted in the non-selected memory block.
After the start of the boost, the first transistor S21 in the non-selected memory block is completely cut off and disconnected from the main bit line MBL2. Therefore, thereafter, the potential of the sub-bit line SBL2 and the sub-source line SSL2 rises rapidly by capacitive coupling with the unselected word lines WL2 to WL128 having a large number, and reaches a predetermined write inhibit voltage (for example, about 5 V).

FIG. 4 is a schematic diagram showing the main coupling capacitance in the memory transistor that contributes to the boost. In FIG. 4, C _gs is the capacitance between the gate and the sub-source line, C _gd is the capacitance between the gate and the sub-bit line, C _SSL is the sub-source line capacitance per cell, and C _SSB is the sub-bit line per cell. Indicates the capacity. If the unselected word line voltage is VWL _unsel. , The boost efficiency is Br and the boosted voltage per cell Vboos
t is represented by the following equation.

[0035]

## EQU1 ## Br = (C _gs + C _gd ) / (C _gs + C _gd + C _SSL + C _SSB ) (1) Vboost = Br × VWL _unsel. (2)

While the boost efficiency of the FG type is about 0.8 at the maximum, the MONOS represented by the equation (1)
The boost efficiency Br of the mold can be relatively high, from 0.74 to 0.91. In this case, the boosted voltage Vbo per cell
ost is 3.3 to 4.1V. Assuming that the boosted voltage Vboost is about 4 V, the voltage of the sub-bit line SBL and the sub-source line SSL before the boost is 1 V, so that the write inhibit voltage is 5 V as shown in FIGS.

In the present embodiment, the value of the second intermediate voltage applied when performing the boost is set to a value that turns off the non-selected memory transistors M22 to M2128. This is because, when a channel is formed, the capacitance between the channel and the gate is added to the denominator of the above equation (1), and accordingly, the boost efficiency Br is reduced. In this regard, the so-called AND-type self-boosting method according to the present embodiment is superior to the NAND-type self-boosting method in which a channel is always formed before it is formed.

Note that even if the application of the second intermediate voltage and the application of the write voltage are performed simultaneously, the number of unselected word lines is large, so that boosting is performed rapidly, and the unselected memory transistor M21 connected to the selected word line is boosted. Is not erroneously written. If you are concerned about preventing erroneous writing,
The application of the write voltage may be slightly delayed from the application of the intermediate voltage.

On the other hand, by applying the write voltage, the write voltage is applied to the selected memory transistor M11 between the channel and the gate, and electrons are transferred from the entire surface of the channel to the charge storage means (carrier trap in the ONO film). Injected and written.

When the voltage application to the selected word line is not performed in two steps as in this writing method, the non-selected output word line M is selected from the viewpoint of preventing erroneous writing of the unselected memory cells.
It is necessary to set the setting voltage of WL2 to, for example, about 5 V and apply a correspondingly high voltage to the selection gate voltage SG1 to turn on the selection transistor S21.

On the other hand, in the writing method of the present embodiment, the set voltages of the unselected main bit line MBL2 and the selection gate voltage SG1 can be both reduced to 1.5 V, and the load on the booster circuit is reduced accordingly. The advantage is that
Further, since the boost is performed while the non-selected memory transistors are turned off in the non-selected memory block, there is an advantage that the boost efficiency is high and the write inhibit voltage that can be reached by the boost can be increased.

Finally, a NOR type memory cell array structure to which the write method of this embodiment can be suitably applied will be described. FIG. 5 is a plan view of the memory cell array, and FIG. 6 is a bird's-eye view as viewed from a cross-sectional side along the line BB 'in FIG. FIG. 7 is an enlarged sectional view of the memory transistor in the word line direction. In this fine NOR type memory cell array,
As shown in FIG. 6, a p-well PW is formed on the surface of a semiconductor substrate SUB. The p-well PW is insulated and separated in the word line direction by an element isolation insulating layer ISO in which an insulator is buried in a trench and arranged in parallel stripes.

Each p-well portion separated by the element isolation insulating layer ISO becomes an active region of the memory transistor. On both sides in the width direction in the active region, n-type impurities are introduced at a high concentration in parallel stripes spaced apart from each other, thereby forming a sub-bit line SBL and a sub-source line SSL. Sub bit line SBL and sub source line SS
L, the word lines WL1, W
L2, WL3, WL4,... Are wired at equal intervals.
Further, these word lines are formed on the p-well PW and the element isolation insulating layer S through an insulating film including a charge storage means therein.
It touches the OI.

As shown in an enlarged manner in FIG.
The intersection of the p-well between the BL and the sub-source line SSL and each word line becomes the channel formation region of the memory transistor. On the channel forming region, for example,
Tunnel insulating film 10 made of 5 nm silicon oxide film or oxynitride film, nitride film 21 made of 5-8 nm silicon nitride film, top insulating film 22 made of silicon oxide film formed by thermal oxidation or high temperature CVD, gate Electrodes (word lines WL) are sequentially stacked.

As shown in FIG. 6, a bit contact BC reaching the sub bit line SBL and a source contact SC reaching the sub source line SSL are formed for each memory block. Also, main bit lines MBL1, MBL2,... Contacting on bit contact BC and main source lines MSL1, MBL2,.
Are alternately formed in parallel stripes.

Since this NOR type cell array has almost no useless space as a pseudo contactless structure in which sub-bit lines and sub-source lines are constituted by impurity regions, 8F ²
A very small cell area close to (F: minimum line width) can be obtained. Further, since the selection transistor separates the parallel memory transistor group of the non-selected memory block from the main bit line, the capacity of the main bit line is significantly reduced, which is advantageous for high speed and low power consumption. Further, since the other select transistor separates the sub source line from the main source line, the capacity of the main source line is small.

In addition to these general advantages, in particular,
In this memory cell array structure, as shown in FIG. 7, the word line WL is formed on the sub-bit line SBL and the sub-source line SSL via the three-layer insulating films 10, 21 and 22 having an oxide film equivalent value of about 10 nm. Crossing. For this reason, the gate capacitances C _gs , C _gd and the sub-wiring capacitances C _SSL , C _gs in FIG.
There is an advantage that the ratio to _SSB can be made larger than that of other structures, and as a result, high boost efficiency can be obtained.

In order to reduce the capacitances C _SSL and C _SSB of the sub-wiring, the substrate may have an SOI structure. Also,
Not limited to MONO type, MNOS type, FG
The writing method of the present embodiment can be applied to a semiconductor memory device having various memory transistors, such as a semiconductor memory device such as a silicon nanocrystal type, a so-called finely divided FG type.

Second Embodiment FIG. 8 shows an example of setting a bias in the writing method according to the second embodiment . FIG. 9 shows a waveform diagram of a voltage change of each signal line.

First, as shown in FIG. 9F, the main bit line MBL1 to which the selected memory block is connected is held at the ground potential (first potential), and the main bit line MBL2 to which the unselected memory block is connected. Is set to a second voltage of, for example, 0.5V. Also, for example, 1..
A predetermined voltage of 5 V (hereinafter, referred to as a second selection gate voltage)
Set. At this time, the select gate line SG1 and all word lines are held at the ground voltage, and the main source line (referred to as a main common potential line in this embodiment) MSL is set to a third voltage of, for example, 1.5V. . Therefore, the selection transistors S11 and S21 are off, but the selection transistors S12 and S22 are on.

In the first embodiment, the first selection gate voltage is set so as to pinch off immediately when the potential of the sub-bit line SBL2 rises in relation to the voltage applied to the non-selected main bit line MBL2. In the present embodiment, a similar pinch-off condition is imposed on the second select gate voltage. That is, the second selection gate voltage is a voltage equal to or lower than a voltage obtained by adding the third voltage to the threshold voltage of the second selection transistor. In the present embodiment, since the main common potential line MSL is common, both the second selection transistors S12 and S22 are cut off when the potential of the sub-source line (referred to as a sub-common potential line in this embodiment) SSL1 or SSL2 rises to some extent. It will be. Therefore, the second selection transistors S12 and S22 enter and maintain the cutoff region when the sub-common potential lines SSL1 and SSL2 are charged to 1V by the third voltage.

Next, at time t1 shown in FIG. 9C, the first intermediate voltage (for example, 4.
5 to 7 V). Then, the memory transistors M11 and M11 in each block connected to the selected word line WL1.
M21 turns on and a channel is formed. Therefore, at this point, the sub-bit line and the sub-source line are short-circuited, and a potential of 1 V is transmitted to sub-bit line SBL as shown in FIG. Incidentally, the fact that the memory transistors M11 and M21 are not written by application of the value of the first intermediate voltage is the same as in the first embodiment.

Thereafter, as shown in FIGS. 9C and 9D, the non-selected word line WL2
ＷＬWL128 to apply a second intermediate voltage (eg, 4.5 V) and change the potential of the selected word line WL from the first intermediate voltage to a write voltage (eg, 11 V). Then, in both memory blocks, the potentials of the sub bit line SBL and the sub source line SSL start to be boosted. After the start of the boost, the second transistors S12 and S22 in both memory blocks are completely cut off and disconnected from the main common potential line MSL. Therefore, thereafter, in both memory blocks, the non-selected word lines WL2
The potential of sub-bit line SBL and sub-source line SSL coupled to WL128 via the capacitor shown in FIG. 4 rapidly rises and reaches a predetermined write inhibit voltage (for example, about 5 V). At this time, also in the present embodiment, similarly to the first embodiment, the unselected memory transistors M11 to M1128 are used.
And M22 to M2128 maintain the off state, and as a result, high boost efficiency Br is obtained.

Next, in the present embodiment, a predetermined low voltage, for example, 0.7 V is applied to the selection gate line SG1 at the timing of time t3 shown in FIG. 9A. This voltage is based on the potential difference between the main bit lines MBL1 and MBL2, and the first selection transistor S11 of the selected memory block is selected.
Are turned on, and the first selection transistor S21 of the non-selected memory block is set to a value that can maintain the off state. Therefore, the charges charged in the sub-common potential line SSL1 and the sub-bit line SBL1 in the selected memory block are rapidly drawn to the main bit line MBL1.
Therefore, for the selected memory transistor M11,
The applied voltage between the channel and the gate is expanded to the write voltage, and electrons are charged from all over the channel by the charge storage means (ONO).
The carrier is injected into a carrier trap in the film, and writing is performed. For the non-selected memory transistors M12 to M1128, the voltage between the gate and the source or drain is −
The voltage is increased from 0.5 V to 4.5 V, but no erroneous writing occurs at an applied voltage of 4.5 V. On the other hand, in the non-selected memory block, since the charge is not extracted, the write inhibition state is continuously maintained.

In the present embodiment, the same effects as in the first embodiment can be obtained. That is, the unselected main bit line MB
The set voltages of L2 and the second select gate voltage SG2 can both be reduced to 1.5V, and the first select gate voltage is also as low as 0.7V, which has the advantage of reducing the load on the booster circuit. . In addition, since the boost is performed while the non-selected memory transistors are turned off in the memory block, there is an advantage that the boost efficiency is high and the write inhibit voltage that can be reached by the boost can be set high.

[0056]

According to the writing method of the nonvolatile semiconductor memory device according to the present invention, the voltage applied to the gate of the non-selected main bit line and the selection transistor can be reduced, and the load on the booster circuit is correspondingly reduced. Further, since the boost is performed while the non-selected memory transistors are turned off in the memory block, the boost efficiency is high, and the write inhibit voltage that can be reached by the boost can be set high. As a result, it is possible to perform writing with high operation reliability, in which erroneous writing is difficult.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main configuration of a nonvolatile memory device according to first and second embodiments.

FIG. 2 is a circuit diagram of two memory blocks, together with a bias setting example of a writing method according to the first embodiment.

FIG. 3 is a waveform chart showing a voltage change of each signal line in the writing method according to the first embodiment.

FIG. 4 is a schematic diagram showing a main coupling capacitance in a memory transistor that contributes to self-boost in the write methods according to the first and second embodiments.

FIG. 5 is a plan view of a NOR type memory cell array in which the write methods of the first and second embodiments can be suitably performed.

FIG. 6 is a cross-sectional view of the NOR type memory cell array shown in FIG.
It is the bird's-eye view seen from the section side along the B 'line.

FIG. 7 is an enlarged cross-sectional view in the word line direction of the memory transistor shown in FIGS. 5 and 6;

FIG. 8 is a circuit diagram of two memory blocks, together with a bias setting example of a writing method according to a second embodiment.

FIG. 9 is a waveform chart showing a voltage change of each signal line in the writing method according to the second embodiment.

FIG. 10 is a plan view of a NAND-type memory cell array, together with a bias setting example in a conventional writing method using self-boost.

[Explanation of symbols]

10 tunnel insulating film, 21 nitride film, 22 top insulating film, SUB semiconductor substrate, PW p-well, ISO
Element isolation insulating layer, BC: bit contact, SC: source contact, M11, etc .: memory transistor, S1
1, S21... First selection transistor, S12, S22.
Second selection transistor, MBL1, MBL2... Main bit line, SBL, SBL1, SBL2.
L, MSL1, MSL2: Main source lines (main common potential lines), SSL, SSL1, SSL2: Sub source lines (sub common potential lines), WL, WL1, etc .: Word lines, SG1, SG
2. Select gate line.

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 24, 2000 (2000.1.2
4)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

As a result, the non-selected memory transistor MT
The channel portion of the transistor row to which the transistor 2b is connected is in a floating state, and the potential of the channel portion is boosted mainly by capacitive coupling with the pass voltage Vpass applied to the unselected word line, and the write inhibit voltage (for example, about 8 V at the maximum) ) To prohibit writing to the memory transistor MT2b. On the other hand, the channel portion of the transistor row to which the selected memory transistor MT2a is connected is set to the potential of the ground voltage GND (0 V),
The writing to the memory transistor MT2a is performed by the potential difference from the writing voltage Vpgm applied to the selected word line, and the threshold voltage shifts in the positive direction, for example, from -3V in the erased state to about 2V.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

Next, second non-selected word lines are
An intermediate voltage (for example, 4.5 V) is applied. Then, the potentials of the sub-bit line and the sub-source line are boosted in the second memory block while the non-selected memory transistors remain in the off state. At the time when this boost starts or not, the first select transistor in the second memory block is cut off and disconnected from the main bit line. Therefore, thereafter, the potentials of the sub-bit line and the sub-source line, which are capacitively coupled to the non-selected word lines having a large number, rapidly rise to reach a predetermined write inhibit voltage. Therefore, even if the selected word line is raised from the first intermediate voltage to a predetermined write voltage (for example, 11 V), the non-selected memory transistors in the second memory block are not written.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

In this writing method, the non-selected word line
Since the self-boost is performed by applying a voltage , the non-selected main bit line voltage can be set to a small value.
The gate applied voltage of the selection transistor can also be reduced. In addition, since the non-selected memory transistor is boosted in the off state in the second memory block, the final write inhibit voltage can be set higher with higher efficiency than the boost after channel formation as performed in the NAND type. .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

In the second writing method, after setting the first and second voltages on the main bit line, similarly to the writing method (first method) according to the first aspect, the second writing method differs from the first method. A positive voltage (third voltage, for example, 1.5 V) is set in a main source line (here, a main common potential line).
Then, the second selection transistor is turned on, and the third selection transistor is turned on.
A predetermined potential (for example, 1 V) is set to a sub-source line (here, a sub-common potential line) by a voltage.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

In the second method, a non-selected word line
Since the self-boost is performed by applying the voltage V.sub.1, the voltage of the main common potential line can be set low, and accordingly, the voltage applied to the gate of the second selection transistor can be reduced. Also,
As in the first method, boosting is performed while the non-selected memory transistors are turned off, so that the boost efficiency is high and the final write inhibit voltage can be set high.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0027

[Correction method] Change

[Correction contents]

The sub bit line SBL1 and the sub source line SSL1
, The memory transistors M11 to M1m are connected in parallel, the memory transistors M21 to M2m are connected in parallel between the sub-bit line SBL2 and the sub-source line SSL2, and the sub-bit line SBLn and the sub-source line SSLn are Between them, the memory transistors Mn1 to Mnm are connected in parallel. These memory transistors are MONOS type memory transistors in which a gate electrode is formed on a semiconductor substrate or well via a three-layer insulating film of a tunnel insulating film, a nitride film, and a top insulating film, as described in detail later. . The m memory transistors connected in parallel to each other and two selection transistors (S11 and S12, S
21 and S22 or Sn1 and Sn2) constitute a unit block (memory block) constituting the memory cell array.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

Each gate of the memory transistors M11, M21,..., Mn1 adjacent in the word direction is connected to the word line WL.
1 connected. Similarly, the memory transistor M1
, M22,..., Mn2 are connected to the word line WL2, and the memory transistors M1 m , M2 m ,
..., the gates of Mnm is connected to the word line WL m. Select transistors S11, S adjacent in the word direction
, Sn1 are controlled by a select gate line SG1, and select transistors S12, S22,..., Sn2 are controlled by a select gate line SG2.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0029

[Correction method] Change

[Correction contents]

Next, a writing method and operation of the NOR type memory cell array having such a configuration will be described. FIG.
The following shows an example of the bias setting in this writing method. Also,
FIG. 3 shows a waveform diagram of a voltage change of each signal line. here,
If no write the memory transistor M11 shown in FIG. 2 as an example. A memory block including the selected memory transistor M11 is referred to as a “selected memory block”, and a memory block not including the selected memory transistor M11 is referred to as a “non-selected memory block”.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction contents]

Next, at the timing of t1 shown in FIG.
As shown in FIG. 2A, a voltage of, for example, 1.5 V (hereinafter, referred to as a first selection gate voltage) is applied to the selection gate line SG1, and the first selection transistors S11 and S21 are applied.
Turn on. This select gate voltage is a voltage equal to or lower than a voltage obtained by adding the second voltage to the threshold voltage of the first select transistor. This is a condition for determining whether or not the selection transistor can be cut off. That is, in the unselected memory block, the first selection transistor S21
The potential at the connection point with the sub-bit line is obtained by subtracting the threshold voltage (0.5 V) from the first selection gate voltage (1.5 V).
Cut off when it reaches V. On the other hand, in the selected memory block , the first selection transistor S11 does not cut off. This first selection transistor S11 is
As shown in FIG. 3H, the sub-bit line S
When BL2 is charged to 1 V, it transitions to a boundary area (cutoff area) of whether or not to cut off, and maintains this.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0032

[Correction method] Change

[Correction contents]

At substantially the same time t1 as the application of the first selection gate voltage, as shown in FIG.
1 is applied with a first intermediate voltage (for example, 4.5 to 7 V). Then, the memory transistors M11 and M21 in each block connected to the selected word line WL1 turn on,
A channel is formed. Therefore, at this time, the sub-bit line and the sub-source line are short-circuited, and a potential of 1 V is transmitted to the sub-source line SSL as shown in FIG. The value of the first intermediate voltage is a condition that the memory transistors M11 and M21 are not written with a potential difference from the sub bit line SBL or the sub source line SSL. This is because the unselected memory transistor M21 is not erroneously written.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction contents]

The boost efficiency Br in the MONOS type of the formula (1) can be relatively high as from 0.74 to 0.91. In this case, the boosted voltage Vboost per cell is 3.3 to 4.1V. Assuming that the boosted voltage Vboost is about 4 V, the voltage of the sub-bit line SBL and the sub-source line SSL before the boost is 1 V, so that the write inhibit voltage is 5 V as shown in FIGS.

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction contents]

When the voltage application to the selected word line is not performed in two steps as in this writing method, the non-selected main bit line M is used from the viewpoint of preventing erroneous writing of the unselected memory cells.
It is necessary to set the set voltage of BL2 to , for example, about 5 V and apply a correspondingly high voltage to the select gate voltage SG1 to turn on the select transistor S21.

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction contents]

Each p-well portion separated by the element isolation insulating layer ISO becomes an active region of the memory transistor. On both sides in the width direction in the active region, n-type impurities are introduced at a high concentration in parallel stripes spaced apart from each other, thereby forming a sub-bit line SBL and a sub-source line SSL. Sub bit line SBL and sub source line SS
L, the word lines WL1, W
L2, WL3, WL4,... Are wired at equal intervals.
These word lines are formed on the p-well PW and the element isolation insulating layer I through an insulating film including a charge storage means therein.
In contact with SO .

[Procedure amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0048

[Correction method] Change

[Correction contents]

In order to reduce the capacitances C _SSL and C _SSB of the sub-wiring, the substrate may have an SOI structure. Also,
Not limited to MONOS type , MNOS type, FG
The writing method of the present embodiment can be applied to a semiconductor memory device having various memory transistors, such as a semiconductor memory device such as a silicon nanocrystal type, a so-called finely divided FG type.

[Procedure amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0051

[Correction method] Change

[Correction contents]

The first selection gate voltage in the first embodiment is set to a condition that the first selection gate voltage is immediately cut off by an increase in the potential of the sub-bit line SBL2 in relation to the voltage applied to the non-selected main bit line MBL2. It had been. In the present embodiment, similar mosquito
A cut-off condition is imposed on the second select gate voltage. That is, the second selection gate voltage is a voltage equal to or lower than a voltage obtained by adding the third voltage to the threshold voltage of the second selection transistor. In the present embodiment, since the main common potential line MSL is common, both the second selection transistors S12 and S22 are cut off when the potential of the sub-source line (referred to as a sub-common potential line in this embodiment) SSL1 or SSL2 rises to some extent. It will be. Therefore, the second selection transistors S12 and S22 enter and maintain the cutoff region when the sub-common potential lines SSL1 and SSL2 are charged to 1V by the third voltage.

[Procedure amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction contents]

Thereafter, as shown in FIGS. 9C and 9D, the non-selected word line WL2
ＷＬWL128 to apply a second intermediate voltage (eg, 4.5 V) and change the potential of the selected word line WL from the first intermediate voltage to a write voltage (eg, 11 V). Then, in both memory blocks, the potentials of the sub bit line SBL and the sub source line SSL start to be boosted. After the start of the boost, the second transistors S12 and S22 in both memory blocks are completely cut off and disconnected from the main common potential line MSL. Therefore, thereafter, in both memory blocks, the non-selected word lines WL2
The potential of sub-bit line SBL and sub-source line SSL coupled to WL128 via the capacitor shown in FIG. 4 rapidly rises and reaches a predetermined write inhibit voltage (for example, about 5 V). At this time, also in the present embodiment, similarly to the first embodiment, the unselected memory transistors M12 to M1128 are used.
And M22 to M2128 maintain the off state, and as a result, high boost efficiency Br is obtained.

[Procedure amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0055

[Correction method] Change

[Correction contents]

In the present embodiment, the same effects as in the first embodiment can be obtained. That is, the set voltages of the main source line MSL and the second select gate voltage SG2 are both set to 1.5
V, and the first selection gate voltage is as low as 0.7 V, which is advantageous in that the load on the booster circuit is reduced. In addition, since the boost is performed while the non-selected memory transistors are turned off in the memory block, there is an advantage that the boost efficiency is high and the write inhibit voltage that can be reached by the boost can be set high.

[Procedure amendment 18]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 5

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 F-term (Reference) 5B003 AA05 AB05 AB07 AC06 AC07 AD03 AD09 5B025 AA03 AB01 AC01 AD04 AD10 AE08 5F001 AA14 AC02 AD41 AD53 AE02 5F083 EP18 EP32 EP77 EP79 ER03 ER09 GA30 JA04 KA06 KA12 LA12 LA16 LA20 5F101 BA46 BC02 BD22 BD34 BE05

Claims (12)

[Claims] A first and second selection transistor; a sub-bit line connected to the main bit line via the first selection transistor; and a sub-bit line connected to a main source line via the second selection transistor. A plurality of memory blocks each including a source line and a plurality of memory transistors connected in parallel between the sub-bit line and the sub-source line; and further, the memory transistor gates are commonly connected between different memory blocks. A nonvolatile semiconductor memory device having a plurality of word lines to be written, wherein the first method includes a selected memory transistor to be written.
Applying a first voltage to the main bit line to which the memory block is connected;
A second voltage higher than the first voltage is set to a main bit line to which a second memory block that does not include a selected memory transistor is connected, and the first select transistor is turned on in the first and second memory blocks. Applying a first intermediate voltage for forming a channel to a memory transistor connected to the selected word line to a selected word line connected to the selected memory transistor in a state where the second selection transistor is turned off; A writing method for a nonvolatile semiconductor memory device, wherein a second intermediate voltage is applied to non-selected word lines other than the selected word line, and the applied voltage of the selected word line is changed from the first intermediate voltage to a higher writing voltage. . A second intermediate voltage applied to a gate of the non-selected memory transistor, the voltage being applied to the sub-bit line and the sub-source line at the time of application of the second intermediate voltage; 2. The method according to claim 1, wherein the value is set so that no channel is formed in the transistor. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a voltage equal to or lower than a voltage obtained by adding said second voltage to a threshold voltage of said first selection transistor is applied to a gate of said first selection transistor. Writing method. 4. The nonvolatile memory according to claim 1, wherein said second voltage is lower than a write inhibit voltage which is a final voltage after said sub-bit line and sub-source line are boosted by application of said second intermediate voltage. A writing method for a semiconductor memory device. 5. The write start voltage according to claim 1, wherein the first intermediate voltage is lower than a write start voltage at which electrons start to tunnel-inject in a gate direction from a channel formed by a memory transistor whose gate is applied with the first intermediate voltage. Writing method for a nonvolatile semiconductor memory device. 6. A voltage obtained by subtracting the write inhibit voltage from the write voltage starts tunnel injection of electrons from a source or a drain of a memory transistor connected to the selected word line in the second memory block in a gate direction. The method according to claim 4, wherein the voltage is lower than a write start voltage. 7. A first and a second selection transistor, a sub-bit line connected to a main bit line via the first selection transistor, and a main common potential line via the second selection transistor. A plurality of memory blocks each including a connected sub-common potential line, and a plurality of memory transistors connected in parallel between the sub-bit line and the sub-common potential line; What is claimed is: 1. A writing method for a nonvolatile semiconductor memory device having a plurality of word lines for commonly connecting gates of transistors, the method comprising:
Applying a first voltage to the main bit line to which the memory block is connected;
Setting a second voltage higher than the first voltage to a main bit line to which a second memory block not including a selected memory transistor is connected, and a third voltage to the main common potential line; In the block, in a state where the first selection transistor is turned off and the second selection transistor is turned on, a channel is connected to a selected word line to which the selected memory transistor is connected, and to a memory transistor connected to the selected word line. Applying a first intermediate voltage of a value to be formed, applying a second intermediate voltage to a non-selected word line other than the selected word line, and increasing the applied voltage of the selected word line to a higher write voltage than the first intermediate voltage The first memory is connected to the gate of the first selection transistor in the first and second memory blocks in accordance with the potential difference between the first and second voltages. A writing method for a nonvolatile semiconductor memory device in which a first selection transistor in a re-block is turned on and a voltage having a value that keeps the first selection transistor in a second memory block off is applied. 8. The non-selected memory transistor after the second intermediate voltage applied to the gate of the non-selected memory transistor is applied in relation to the potential of the sub-bit line and the sub-source line at the time of application. 8. The method according to claim 7, wherein the value is set so that no channel is formed in the transistor. 9. The nonvolatile semiconductor memory device according to claim 7, wherein a voltage equal to or lower than a voltage obtained by adding said third voltage to a threshold voltage of said second selection transistor is applied to a gate of said second selection transistor. Writing method. 10. The write inhibit voltage as a final voltage after the sub-bit line and the sub-source line are boosted by application of the second intermediate voltage.
3. The writing method for a nonvolatile semiconductor memory device according to item 1. 11. The write start voltage according to claim 7, wherein the first intermediate voltage is lower than a write start voltage at which electrons start to tunnel-inject in a gate direction from a channel formed by a memory transistor having the gate applied with the first intermediate voltage. Writing method for a nonvolatile semiconductor memory device. 12. A voltage obtained by subtracting the write inhibit voltage from the write voltage forms a tunnel between a source or a drain of a memory transistor connected to the selected word line in the first and second memory blocks in a gate direction. 11. A voltage lower than a writing start voltage at which injection is started.
3. The writing method for a nonvolatile semiconductor memory device according to item 1.