JP2001101864A - Synchronous semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous semiconductor memory simple in configuration, and capable of being easily manufactured and keeping its output in high impedances when a power is supplied. SOLUTION: This synchronous semiconductor memory, which has latch circuits and an output circuit for outputting the data latched in the latch circuits and keeps the output circuit in a high impedance when the power is supplied, is provided with an internal reset output means for resetting the latch circuits at the time when data are not inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronous semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, with the speeding up of systems using electronic circuits, there has been a demand for higher speeds of semiconductor memory devices.
In response to such a demand, for example, a synchronous semiconductor memory device has been proposed. This device performs a storage operation in synchronization with a clock signal (CLK) input from the outside, and a synchronous dynamic RAM (hereinafter, referred to as an SDRAM) is most frequently used.

A synchronous semiconductor memory device performs a storage operation in synchronization with a clock signal (CLK) input from the outside. The most frequently used device in such a device is shown in FIG. A main circuit configuration diagram of such an SDRAM is shown. The configuration of such a device will be briefly described.
Command decoder 302, mode register 303, row address buffer 304, column address buffer 305, row decoder 308, column decoder 309, memory cell array 307, sense amplifier 310, data control circuit 312,
It is composed of a latch circuit 314, an output circuit 315 and the like.

Next, the operation of such a synchronous semiconductor device will be described below. The internal operation of the SDRAM
This is performed in synchronization with a clock signal CLK input from the outside. At the rising time of the externally input clock signal, the electrical level of another external input signal, for example, C
Depending on the combination of the "H" level or the "L" level such as SB (chip select bar) input, RASB (row address strobe bar) input, CASB (column address strobe) input, WEB (write enable bar) input, etc. The operation content is determined as follows. Inputs based on these combinations are referred to as commands, and commands based on the "H" level or "L" level of these inputs determine whether a column address control operation, a row address control operation, a write operation, a read operation, or the like is performed. The operation content is determined.

An external input signal such as the CSB described above is input to a command decoder 302, and an internal operation control signal is output from the command decoder. When data is read, first, an active command is input, an externally input address signal is latched as a row address by a row address buffer circuit 304, and decoded by a row decoder circuit 308 to determine a row address. Then, a word line (not shown) of the memory cell 307 is selected, and data stored in the memory cell is read and amplified by a sense amplifier.

Next, a read command is input, an externally input address signal is latched as a column address in a column address buffer 305, and is decoded by a column decoder circuit 309 to determine a column address. The Y-switch is selected, the data amplified by the sense amplifier is passed through the read / write bus, latched by the latch circuit 314, and stored in synchronization with the internal latch signal ICLKOE generated in synchronization with CLK from the output circuit 315. Data is output. Finally, a precharge command is input, the word line selected by the active command is set to a non-selected state, and the circuit operation is set to a standby state.

FIG. 4 is a diagram illustrating the output circuit 315 shown in FIG. 3 in detail. OE (output enable)
The signal is a signal for enabling data output, and the latch signal ICLKOE is a signal for controlling the latch circuit 11 that latches data of the last stage. The logic of OE is before the latch circuit 11 because the data output hold time tOH and the data output high impedance time t
This is because there is an advantage that the HZ specifications can be easily realized. As shown in FIG. 5A, the PON signal causes the output circuit 315 to output high impedance (Hi-Z) when the power is turned on.
This is a signal which becomes "H" level only when the power is turned on. During standby, the latch signal ICLKOE is "
When the power is turned on, the PON signal goes to "H" level, the output of the gate 13 goes to "H" level, and the transistor 62 of the output circuit is turned on. , 63 are turned off to prevent erroneous data from being output to the output terminal DQ when the power is turned on.Thus, conventionally, the PON signal is turned on to turn the output to high impedance when the power is turned on. Was used.

However, in the conventional circuit described above,
If the data latch signal ICLKOE of the final stage is "L" during standby and is in the latch state, a PON signal for setting the output to high impedance may not be output when the power is turned on, as shown in FIG. 5B. As described above, the output circuit becomes low impedance, and in this case, there is a problem that a latched erroneous signal is output from the output terminal DQ.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to make sure that the output is made to have a high impedance at the time of turning on the power without relying on the internal signal for turning on the power, and to suppress the output of an uncertain signal. It is intended for.

[0010]

According to a first aspect of the present invention, there is provided a synchronous semiconductor memory device, comprising: a latch circuit; and an output circuit for outputting data latched by the latch circuit. Is a high-impedance synchronous semiconductor memory device, characterized in that the synchronous semiconductor memory device has internal reset output means for resetting the latch circuit except when data is input.

According to a second aspect of the present invention, in the synchronous semiconductor memory device according to the first aspect, the synchronous semiconductor memory device further comprises the step of setting the output circuit to a high level based on an external control signal via a first stage circuit. A control mechanism for controlling the impedance is provided.

According to a third aspect of the present invention, there is provided a synchronous semiconductor memory device according to the first or second aspect, further comprising a latch circuit and an output circuit for outputting data latched by the latch circuit, wherein the output is provided when power is turned on. A synchronous semiconductor memory device having a circuit with high impedance,
The semiconductor device further includes a selection unit that selects one of a signal for latching the latch circuit and a reset signal for resetting.

According to a fourth aspect of the present invention, there is provided a synchronous semiconductor memory device according to any one of the first to third aspects, wherein an internal signal for controlling the output circuit to high impedance is provided based on the external control signal. It is characterized in that an internal signal generating means for generating is provided.

According to a fifth aspect of the present invention, in the synchronous semiconductor memory device according to any one of the first to fourth aspects, when power is turned on, the latch circuit is turned on by a reset signal output from the internal reset means. It is characterized by being controlled by impedance.

According to a sixth aspect of the present invention, in the synchronous semiconductor memory device according to any one of the first to fifth aspects, the synchronous semiconductor memory device is a synchronous DRAM.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a synchronous semiconductor memory device according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment of a semiconductor memory device according to the present invention. A signal input from the external terminal DQM is input to the first-stage circuit 1. Output signal 1 from first stage circuit 1
02 and a READB signal which becomes “L” level at the time of reading are input to the NOR gate 2. The signal 100 output from the NOR gate 2 is connected to the NAND gate 3,
Input to NAND gate 4. The read data signal DATA is input to the NAND gate 3 and the inverter 6. Inverted DATA output from inverter 6
The signal 103 is input to the NAND gate 4. NAN
The signal 104 output from the D gate 3 is input to the inverter 7 and inverted, and the inverted output signal is input to the latch circuit 10.

The signal 105 output from the NAND gate 4 is input to the inverter 8 and inverted, and the inverted output signal is input to the latch circuit 11. The signal 102 output from the first stage circuit 1 and "L" at the time of reading
The READB signal which becomes the level is input to the NAND gate 5 and the signal 110 output from the NAND gate 5 is output.
Is input to the inverter 9 and inverted, and the inverted output reset signal 111 is input to the latch circuit 10 and the latch circuit 11. An internal latch signal ICLKOE generated in synchronization with CLK is input to latch circuits 10 and 11. Signal 10 output from latch circuits 10 and 11
8 and 109 are input to output transistors 12 and 13, respectively. The signal DQ output from the output transistor
Is output from the terminal DQ.

The operation of such a synchronous semiconductor memory device according to the present invention will be described. FIG. 2 is a timing chart for the operation of the first embodiment. At power on,
The external signal DQM is at “H” level, and the signal 102 output from the first-stage circuit 1 is at “H” level. Here, for example, when the DQM signal, which is a small signal of L = 0.8V and H = 2.0V, is input, the first-stage circuit has L = 0.0V.
And H are 3.3V and a circuit for amplifying the difference between L and H. DQM passing through such a first stage circuit
When a signal is input, the internal signal READB
The signal becomes "L" level. This READB signal and 1
The signal 100 outputted from the NOR gate 2 to which the signal 02 is inputted becomes the "L" level. Also DATA
The signal 104 and the permeation 104 signal output from the NAND gate 3 to which the 100 signal is input become “H” level,
The signal 106 output from the inverter 7 to which the signal 104 of this level is input becomes the “L” level,
The signal 108 output from the latch circuit 10 becomes "L" level.

On the other hand, the output signal 103 from the inverter 6 to which the DATA signal is input and the permeation 105 signal from the NAND gate 4 to which the 100 signal is input are "
The signal 107 output from the inverter 8 to which the signal 105 is input is "L".
Level and the signal 10 output from the latch circuit 11
9 becomes the "L" level. Therefore, the transistors 12 and 13 are not turned on, and the output from DQ becomes high impedance.

When not at the time of READ, the internal signal READ
B goes to the “H” level. When the power is turned on, the external signal DQM
Is at "H" level, and the signal 102 output from the first stage circuit 1 is at "H" level. 102 signal and internal signal R
The output signal 110 from the NAND gate 5 to which the EADB is input becomes the "L" level, and therefore, the reset signal 1 output from the inverter 9 to which the 110 signal is input.
11 goes to the "H" level. The latch circuit 10 and the latch circuit 11 to which the reset signal 111 is input are reset, and the signal 108 output from the latch circuit 10 and the signal 109 output from the latch circuit 11 are respectively "
Therefore, the transistor 12 and the transistor 13 are not turned on, and the output from the DQ becomes high impedance.

In the first embodiment, the external signal D
Utilizing the fact that QM becomes "H" level, the output from DQ became high impedance. In the second embodiment, the DQM signal goes to the “L” level without relying on the READB, so that “L” or “L” is output.
The synchronous semiconductor memory device according to the present invention can have a configuration having a circuit operating at H ". In the present invention, the DQM signal is used as an external signal. In this case, an external signal may be input via an input stage for simultaneously inputting the DQM signal and the PON signal. By using an external signal or an internal signal whose "H" level or "L" level is sometimes determined, the output signal can be made to have a high impedance when the power is turned on as in the case of using the READB. Can be generated by appropriately using known signal generation means.

[0022]

According to the present invention, as described above, in the conventional circuit system, the signal P which becomes "H" level when the power is turned on is obtained.
If the ON signal does not go to the “H” level, the output signal becomes low impedance, and it is possible to overcome the conventional drawback that may cause a malfunction. By utilizing the fact that the signal DQM is at the “H” level, the output can be made to have a high impedance when the power is turned on without relying on the PON signal. Such a synchronous semiconductor memory device according to the present invention has a simple configuration and can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a synchronous semiconductor memory device according to the present invention.

FIG. 2 is a timing chart illustrating the operation of the first embodiment of the synchronous semiconductor memory device according to the present invention.

FIG. 3 is a block diagram of a synchronous DRAM.

FIG. 4 is a block diagram showing a conventional technique.

FIG. 5 shows a timing chart for explaining a conventional technique, in which (a) is a timing chart in a normal state;
(B) is a timing chart showing a state in which erroneous data is output.

[Explanation of symbols]

 1 semiconductor memory device 2 power on 3 high impedance 4 power on

Claims (6)

[Claims] 1. A synchronous semiconductor memory device having a latch circuit and an output circuit for outputting data latched by the latch circuit, wherein the output circuit is set to high impedance when power is turned on, wherein Type semiconductor memory device, except during data input,
A synchronous semiconductor memory device having an internal reset output means for resetting the latch circuit. 2. The synchronous semiconductor memory device further comprises:
2. The synchronous semiconductor memory device according to claim 1, further comprising a control mechanism for controlling the output circuit to have a high impedance based on an external control signal via a first-stage circuit. 3. A synchronous semiconductor memory device having a latch circuit and an output circuit for outputting data latched by the latch circuit, wherein the output circuit is set to high impedance when power is turned on, 3. The synchronous semiconductor memory device according to claim 1, further comprising a selection unit that selects one of a signal for latching a circuit and a reset signal for resetting. 4. An apparatus according to claim 1, further comprising an internal signal generating means for generating an internal signal for controlling said output circuit to high impedance based on said external control signal. 10. The synchronous semiconductor memory device according to claim 1. 5. The synchronous circuit according to claim 1, wherein at the time of power-on, said latch circuit is controlled to a high impedance by a reset signal output by said internal reset means. Semiconductor storage device. 6. The synchronous semiconductor memory device according to claim 1, wherein said synchronous semiconductor memory device is a synchronous DRAM.