JP2001194679A - Liquid crystal device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: In an electronic device using a liquid crystal device, a wiring around an input / output terminal of a liquid crystal panel is protected to prevent poor connection between the input / output terminal and the FPC. SOLUTION: A peripheral portion of an input / output terminal including a routing wiring is covered and protected by a transparent insulating film. The input / output terminals are cut out by thickening the transparent insulating film, and an ITO film is provided inside to make the input / output terminals. The transparent insulating film is hollowed out in a tapered shape to form a mortar, and a dent is formed around the input / output terminals to capture debris generated during rubbing or cutting the substrate. The input / output terminals and the peripheral transparent insulating film are formed simultaneously with the formation of the thin film transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal device, and more particularly to a means for preventing a connection failure of an input / output terminal of an active matrix substrate.

[0002]

2. Description of the Related Art In recent years, large-capacity matrix liquid crystal devices have been used for personal computer displays and the like. Among them, as high-quality, large-capacity liquid crystal display device,
An active matrix type liquid crystal display device in which a thin film element having a switching function is introduced between a pixel electrode and a signal wiring is mainly used. The active matrix substrates of these active matrix type liquid crystal display devices include:
A thin film transistor (ThinFilm T) is used as a pixel switching element or a switching element constituting a driving circuit.
ransistor: hereinafter abbreviated as TFT). In order to improve the withstand voltage of the TFT or reduce the off-leak current in the active matrix substrate, a technique of using the TFT with an offset gate structure or an LDD structure is often used.

An active matrix substrate has the above-mentioned TFT.
In addition, an input / output terminal for exchanging a signal current with the TFT is provided. The flexible printed circuit board (Frexible Print Cercuit: hereafter, FPC)
) Is connected, and exchanges signals with external devices. FIG. 8 shows an outline of the FPC. FIG. 8A is a view showing the appearance of the FPC, in which an insulating synthetic resin layer 41 is formed around metal conductors 42 arranged in a straight line.
It is configured to be flat and flexible as a whole. FIG. 8B shows a cross-sectional structure of the terminal portion of the FPC. At the connection portion at the end of the FPC 9, the synthetic resin layer 41 on the lower surface of the metal conductor 42 is peeled off, and an adhesive tape 45 in which metal particles 43 such as copper are dispersed in an adhesive 44 is attached.

FIG. 9 shows a state in which the FPC thus configured is mounted on the active matrix substrate 2. FIG. 9A is a cross-sectional view of the input / output terminal portion of the active matrix substrate 2.
1 is arranged. Input / output terminal 81 having such a structure
FIG. 9 is a cross-sectional view showing a state in which the FPC 9 is connected to FIG.
(B). When the metal wires 42 of the FPC 9 are superimposed on predetermined input / output terminal positions on the active matrix substrate 2 and heated and pressed, the adhesive 44 of the FPC 9 protrudes sideways, and the input / output terminals 81 on the active matrix substrate 2 and the metal wires of the FPC 9 42 come into contact with each other via the metal particles 43. If a sufficient number of the metal particles 43 are completely in contact, the contact resistance between the input / output terminal 81 and the metal conductor 42 of the FPC 9 becomes low, and good bonding can be achieved. However, if dust or the like of the insulator enters during this time, the contact resistance increases or insulation failure occurs. If there is no transparent insulating film between the terminals, the terminals are short-circuited by the metal particles.

On the other hand, in such a liquid crystal display device, it is necessary to align liquid crystal molecules in a specific direction. After forming data lines, signal lines, and TFTs on a substrate, a substrate having alignment properties in a specific direction is formed on the substrate surface. Means for providing a kimono or a groove to physically regulate the long axis direction of the liquid crystal molecules is employed. The main means is to apply an oriented film such as a polyimide resin, or to apply a flaw in a specific direction to the surface of the oriented film to give the orientation.
Means for imparting directionality by scratching the alignment film include:
There are an oblique deposition method, a rubbing method, and the like. Since the oblique deposition method has disadvantages such as low production efficiency and insufficient image contrast, the rubbing method is widely used. In general, as the rubbing method, a rubbing method of rubbing an alignment film such as a polyimide resin with a cloth or a rotary rubbing method of rubbing with a rotating brush having a brush having a diameter of 10 to 20 μm has been put to practical use.

[0006]

In the rubbing process, a rubbing process is generally performed on the entire surface of the substrate after applying an alignment film to a predetermined display area. In addition, the rubbing process is not performed for each substrate, but for simultaneously processing the entire surface of a substrate preform in which several substrates are continuous. After completion of the rubbing process, the substrate base material is cut into several single substrates and sent to the next mounting step. Also in this cutting step, chips made of an insulating material such as a transparent insulating substrate, an alignment film, an interlayer insulating film, and a flattening film are generated.

[0007] However, during the rubbing process, the scraps of the alignment film shaved off by the brush and the insulating material such as chips generated when cutting the substrate are carried to the input / output terminal portion of the active matrix substrate and are mounted. FPC metal wire 4
2 may result in an increase in connection resistance and poor connection. In addition, the routing wiring pattern around the input / output terminal portion is exposed and is not provided with any protective means, and is generated in a cutting process of the alignment film generated during the rubbing process when the substrate is mounted or in the cutting process. Insulating material such as chips may damage the wiring pattern around the input / output terminals,
There was a problem that this would cause a product defect. An object of the present invention is to provide a means for protecting the routing wiring pattern around these input / output terminal portions and preventing a connection failure at the input / output terminal portions during mounting.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned drawbacks, and a transparent resin film is provided around an input / output terminal portion of an active matrix substrate, and a routing wiring pattern is formed in a mounting process. Means of protection were adopted. In addition, a transparent resin film is provided so as to surround the periphery of the input / output terminals, and the insulating resin debris generated in the cutting step or the rubbing step of the substrate base material is captured by the transparent resin film. Means for preventing poor connection was adopted. Also,
A means is provided in which a dent is provided between the transparent resin film provided around the input / output terminal portion and the input / output terminal, and debris of the insulator is captured by the dent. By providing such a transparent resin film around the input / output terminals, the routing wiring around the input / output terminals is protected in the mounting process, and the effect of preventing poor connection between the input / output terminals and the FPC is exhibited.

Further, in the method of manufacturing a liquid crystal device according to the present invention, means for forming the input / output terminals and the transparent resin film around the input / output terminals simultaneously with the formation of the TFTs on the active matrix substrate is employed. According to this manufacturing method, the input / output terminals and the transparent resin film can be formed without increasing the number of special steps, so that the manufacturing can be performed without lowering the production efficiency. Electronic equipment using the active matrix substrate according to the present invention,
There is no connection failure in the input / output terminal portion, and the reliability is high.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, a structure of a liquid crystal display panel of a liquid crystal device according to the present invention will be described with reference to FIG.
0 is a block diagram schematically illustrating the configuration of the electro-optical device. As shown in FIG. 10, data lines 90 and scanning lines 91 are formed on an active matrix substrate 2 for an electro-optical device. The scanning line 91 is connected to the gate of the pixel TFT 10 connected to the pixel electrode in each pixel, and the data line 90 is connected to the source of the pixel TFT 10. Each pixel has a liquid crystal cell 94 to which an image signal is input via the pixel TFT 10. Data line 90
, The shift register 48, the level shifter 85,
A data line driving circuit 60 including a video line 87 and an analog switch 86 is formed on the active matrix substrate 2. For the scanning line 91, a scanning line driving circuit 7 including a shift register 88 and a level shifter 89
0 is formed on the active matrix substrate 2.

The scanning line driving circuit 70 and the data line driving circuit 60 are composed of an N-type driving circuit TFT and a P-type driving circuit.
It is constituted by a TFT for a driving circuit of a type. These T
The FT employs an LDD structure. Each pixel has a storage capacitor 40 (capacitance element) between the capacitance line 92 and the gate electrode.
May be formed, and the storage capacitor 40 has a function of improving the charge retention characteristics of the liquid crystal cell 94.
Incidentally, the storage capacitor 40 may be formed between the scanning line 91 and the preceding stage.

The active matrix substrate 2 configured as above constitutes an electro-optical device as shown in FIGS. FIG. 11 and FIG. 12 are a plan view of the electro-optical device and a cross-sectional view taken along line HH ′, respectively. In these figures, the electro-optical device 1 includes an active matrix substrate 2 and a transparent insulating substrate 300 such as a quartz substrate or a high heat resistant glass substrate.
And a counter substrate 3 on which a matrix-shaped light-shielding film 98 for separating the display area is formed, and a liquid crystal 6 sealed and sandwiched between these substrates.
The active matrix substrate 2 and the opposing substrate 3 are bonded to each other with a predetermined gap by a sealing layer 80 using a sealing material containing a gap material, and a liquid crystal 6 is sealed between these substrates. For the seal layer 80, an epoxy resin, various ultraviolet curable resins, or the like can be used. Also,
As the gap material, inorganic or organic fibers or spheres of about 2 μm to about 10 μm can be used.

The opposing substrate 3 is an active matrix substrate 2
The peripheral portion of the active matrix substrate 2 is bonded so as to protrude from the outer peripheral edge of the counter substrate 3. Therefore, the scanning line driving circuit 70 and the data line driving circuit 60 of the active matrix substrate 2
Is located outside. The scanning line driving circuit 70 and the data line driving circuit 60 are connected to the input / output terminal 81 via the routing wiring 75. Further, since the input / output terminals 81 on the active matrix substrate 2 are also located outside the counter substrate 3, the flexible printed circuit board 9 can be connected to the input / output terminals 81 by wiring. Here, since the seal layer 80 is partially interrupted, the liquid crystal injection port 83 is formed by the interrupted portion. For this reason, after the opposing substrate 3 and the active matrix substrate 2 are bonded to each other, if the inside area of the seal layer 80 is set in a reduced pressure state, the liquid crystal 6 can be injected under reduced pressure from the liquid crystal injection port 83. The liquid crystal injection port 83 may be closed with the sealant 82.

In the present invention, the peripheral portions of the input / output terminals 81 and the routing wirings 75 of the active matrix substrate 2 shown in FIGS. 11 and 12 are protected by being covered with a transparent resin film. The transparent resin used for the transparent resin film is not particularly limited as long as it is a transparent and insulating material such as an acrylic resin, a polyamide resin, a polyimide resin, and a phenol resin. The one used as a flattening film or an interlayer insulating film used in manufacturing a thin film transistor on an active matrix substrate can be used as it is.

FIG. 1 is an enlarged plan view of the peripheral portions of the input / output terminal 81 and the routing wiring 75 according to the present invention. In FIG. 1, an input / output terminal 81 is arranged at one end of the active matrix substrate 2, and a wiring 75 extending from the input / output terminal 81 to a scanning line driving circuit and a data line driving circuit. The transparent resin film 403 may be only the peripheral portion of the routing wiring 75 in FIG. 1 (that is, 28 portion in FIG. 1) or may include the periphery of the input / output terminal 81 (that is, 29 portion in FIG. 1). In the former case, the routing wiring 7 is mainly used in the mounting process.
5 can be protected. In the latter case, the effect of preventing a poor connection between the input / output terminal 81 and the FPC is further achieved.

FIG. 2 shows an example of a cross-sectional structure along the line AA 'in FIG. In FIG. 2, a wiring 75 is formed on the insulating film 14 of silicon oxide. This routing wiring 75
The space between them is filled with the transparent resin film 403. As shown in FIG. 2, the thickness of the transparent resin film 403 is
Thicker than the height. As shown in the plan view of FIG. 1, if the routing wiring 75 is covered with the transparent resin film 403, the routing wiring 75 can be protected.

FIG. 3 shows an example of a cross-sectional structure along the line BB 'in FIG. In FIG. 3, the input / output terminals 81 are formed on the silicon oxide insulating film 14 by the first conductive film 81a and the second conductive film 8 respectively.
1b. This input / output terminal 81
The space between them is filled with the transparent resin film 403. As shown in FIG. 3, the thickness of the transparent resin film 403 is
Thicker than the height. Then, the upper portion of the input / output terminal 81 of the transparent resin film 403 is removed to form an opening 84, and the inner surface of the opening 84 is coated with an ITO (Indium Tin Oxide) film 4.
And the input / output terminal 81. At this time, the opening 84 of the transparent resin film 403 becomes wider toward the upper portion by etching and forms a mortar shape.

Here, the first conductive film 81a is made of the same material as the gate electrode of the TFT, and the second conductive film 81b is made of a source material.
If the drain electrode is made of the same material, an input / output terminal can be formed at the same time as the TFT is formed, which is extremely convenient in manufacturing. By configuring the peripheral portion of the input / output terminal as described above, the insulating debris generated in the rubbing step of the alignment film or the cutting step of the substrate is trapped on the side wall of the transparent resin film 403. Does not reach the insulation waste, FP
It does not hinder the connection with C. In the mounting process, F
The adhesive of the PC does not protrude between the terminals and does not short-circuit due to metal particles contained in the adhesive.

FIG. 4 shows another embodiment of the peripheral portion of the input / output terminal of the present invention. In this embodiment, in the structure of the transparent resin film shown in the embodiment of FIG. 3, the vicinity of the conductive films 81 a and 81 b for the input / output terminals 81 is over-etched to provide a depression 406. Of course, the surface of the depression 406 is also covered with the ITO film 4 to form the integrated input / output terminal 81. By providing the recess 406 around the metal pattern for the input / output terminal 81 in this manner, the insulating debris generated in the rubbing process of the alignment film or the cutting process of the substrate can be reliably captured by dropping into the recess 406.
This has the effect of preventing contact failure and increase in contact resistance during connection with the PC.

Next, a method of manufacturing a transparent resin film around an input / output terminal according to the present invention will be described. In the present invention, the input / output terminals and the transparent resin film are preferably formed in accordance with the manufacturing process of the TFT of the active matrix substrate 2. The description will be made with reference to the drawings in the order of steps. An example of an active matrix substrate including three types of TFTs according to an embodiment of the present invention will be described. For example, in the electro-optical device shown in FIG. 10, an N-type pixel switching TFT having an LDD structure and an N-type drive circuit TFT having an LDD structure
And P-type drive circuit T having self-aligned structure
Three types of TFTs, FT, are used. The active matrix substrate 2 of the present invention can be manufactured, for example, by the following method. In the following description, each impurity concentration is represented by the impurity concentration after activation annealing.

First, as shown in FIG. 5A, a base protective film 201 made of a silicon oxide film is formed on a surface of an insulating substrate 200 such as a quartz substrate or a glass substrate. Next, I
After the amorphous silicon film 202 is formed by a CVD method, a plasma CVD method, or the like, crystal grains are grown by a laser annealing method or a rapid heating method to form a polysilicon film.

Next, as shown in FIG. 5B, the polysilicon film is patterned by photolithography to form a pixel TFT, an N-type drive circuit TFT, and a P-type drive circuit TFT. Island-like silicon film 1 in region
Leave 0a, 20a and 30a.

Next, TEOS-CVD, ICVD,
An insulating film 14 made of a silicon oxide film having a thickness of about 300 angstroms to about 2000 angstroms is formed on the entire surface of the silicon film by a plasma CVD method, a thermal oxidation method, or the like (first gate insulating film forming step). Here, when the insulating film 14 is formed by using the thermal oxidation method, the silicon films 10a, 20a, and 30a are also crystallized, and these silicon films can be used as a polysilicon film. When channel doping is performed, for example, boron ions are implanted at this timing at a dose of about 1 × 10 ¹² cm ⁻² . As a result, the silicon films 10a, 20a, 30a
Becomes a low-concentration P-type silicon film having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ .

Next, as shown in FIG.
A conductive film 150 for forming a gate electrode, such as a doped silicon, a silicide film, a metal film such as an aluminum film, a chromium film, or a tantalum film, is formed on the entire surface of the substrate 4. The thickness of the conductive film 150 for forming a gate electrode is about 2000 Å. Next, a mask 551 for patterning is formed on the surface of the conductive film 150 for forming a gate electrode, and patterning is performed in this state, and as shown in FIG. Formed (first gate electrode forming step). At this time, N
The gate electrode forming conductive film 150 is not patterned because the gate electrode forming conductive film 150 is covered with the patterning mask 551 on the side of the TFT for the pixel and the TFT for the N-type driving circuit. . Also, the input / output terminal formation region is not patterned.

Next, as shown in FIG. 5E, the gate electrode 35 on the side of the P-type driving circuit TFT and the side of the N-type pixel TFT and the N-type driving circuit TFT are left. Using the conductive film 150 for forming a gate electrode as a mask, boron ions (second conductivity type / P type) are ion-implanted at a dose (high concentration) of about 1 × 10 ¹⁵ cm ⁻² (doping of high concentration second conductivity type impurities). Process). As a result, the impurity concentration becomes 1 × 10 ²⁰ c
Source / drain regions 31 and 32 having a high concentration of m ⁻³ are formed in self-alignment with the gate electrode 35. Here, the portion covered with the gate electrode 35 becomes the channel formation region 33.

Next, as shown in FIG. 6A, the P-type driving circuit TFT is completely covered, and the N-type pixel TFT and the N-type driving circuit TFT-side gate are completely covered. A patterning mask 552 made of a resist mask covering an electrode formation region is formed. At this time, the input / output terminals 8
A patterning mask 553 made of a resist mask covering the formation region of No. 1 is also formed.

Next, as shown in FIG. 6B, the gate electrode forming conductive film 150 is patterned using the patterning masks 552 and 553, and the N-type pixel TFT is formed.
And gate electrodes 15 and 25 of N-type drive circuit TFT
Then, a first conductive film 81a for the input / output electrode 81 is formed (second gate electrode forming step, see FIG. 6C). At the time of this patterning, a patterning mask 552,
Lateral etching (side etching) occurs in the gate electrode forming conductive film 150 covered with 553. Therefore, the first conductive film 81a of the gate electrodes 15, 25 and the input / output terminal 81 becomes smaller than the patterning mask 552 in both the width direction and the length direction. In the second gate electrode forming step, from the viewpoint of actively performing side etching on the gate electrode forming conductive film 150, the second gate electrode forming step includes wet etching, plasma etching, and the like. An isotropic etching method is preferred.

Next, patterning masks 552 and 55
3 and leave phosphorus ion (1st conductivity type / N type)
Ion implantation is performed at a dose (high concentration) of 10 ¹⁵ cm ^-2 (first high concentration first conductivity type impurity introduction step). As a result, impurities are introduced into the patterning mask 552 in a self-aligned manner, and high-concentration source / drain regions 112, 122, 212, 222 are formed in 10a, 20a. Here, a region of the silicon films 10a and 20b into which high-concentration phosphorus is not introduced is the gate electrode 1
It is wider than the area covered by 5, 25. That is, the gate electrodes 15, 25 of the silicon films 10a, 20a
Are formed between the high-concentration source / drain regions 112, 122, 212 and 222 on both sides of the region opposite to the region 111, 121, 211 and 221 where high-concentration phosphorus is not introduced.

Next, as shown in FIG. 6C, the patterning masks 552 and 553 are removed, and in this state, phosphorus ions are implanted at a dose of 1 × 10 ¹³ cm ^-2 (low concentration) ( Low concentration first conductivity type impurity introduction step). As a result, the gate electrodes 1 are formed on the silicon films 10a and 20a.
Low-concentration impurities are introduced into the low-concentration source / drain regions 111 and 12 in a self-alignment manner with respect to 5 and 25.
1, 211 and 221 are formed. The gate electrode 1
Channel formation regions 13 and 23 are provided in regions overlapping with regions 5 and 25.
Is formed. At this time, the first conductive film 81a of the input / output terminal is formed.

Next, as shown in FIG. 6D, a lower interlayer insulating film 401 is formed on the surface side of the gate electrodes 15, 25, 35 and the input / output terminals 81, and then patterned by photolithography. Predetermined source electrode position,
A contact hole is formed at the position of the drain electrode and the position of the input / output terminal. Next, from above, an aluminum film,
Using a metal film such as a chromium film or a tantalum film, a source / drain formation conductive film 160 to be the second conductive film of the source electrodes 16, 26, 36, the drain electrodes 17, 27, and the input / output terminal 81 is formed. The thickness of the conductive film 160 for forming source / drain is approximately 2000 to 3000 angstroms. Source electrodes 16, 26, 36,
After patterning masks 554 and 555 are formed on the surfaces of the drain electrodes 17 and 27 and the input / output terminals 81, patterning is performed in this state, and the source / drain electrodes 16, 17, and 26 shown in FIG. , 27, 3
6 and the second conductive film 81b of the output terminal are formed.

Next, as shown in FIG. 7A, after an upper interlayer insulating film 402 made of silicon nitride or the like is formed, TF
In the T formation region, a flattening film 404 made of a transparent resin film is formed in order to reduce the influence of the unevenness of each element and protect the element. On the other hand, at the same time,
A transparent resin film 403 is formed as shown in FIG. The thickness of the transparent resin film 403 is preferably about 1 to 2 μm. Next, the upper interlayer insulating film 402 and the transparent resin film 4 on the drain electrode portion are formed.
03 is removed by photolithography to form a contact hole. At this time, the upper interlayer insulating film 402 and the transparent resin film 403 of the input / output terminal are also removed to provide an opening 84 in the input / output terminal (see FIG. 7B). When the transparent resin film 403 is removed and the opening 84 is opened, the second conductive film 81b remains when over-etching is performed, and only the periphery of the second conductive film 81b is etched deeply to form a depression 406 as shown in FIG. It is formed. Thereafter, a pixel electrode 8 connected to the drain electrode is formed in the TFT region by sputtering of ITO or the like. On the other hand, at the same time, the ITO film 4 is formed on the inner wall of the opening 84 and the upper surface of the second conductive film 81b also in the input / output terminal portion, thereby completing the input / output terminal (see FIG. 7C).

Thereafter, an alignment film is applied to the TFT region, and the process proceeds to a rubbing process. As described above, when the input / output terminals and the transparent resin film around the input / output terminals are simultaneously formed along with the formation of the TFTs on the active matrix substrate, the reliability is improved without reducing the production efficiency without adding any special process. A high active matrix substrate can be obtained.

[0033]

According to the present invention, the wiring pattern can be protected from the insulating chips generated during the rubbing process and the insulating chips generated during the substrate cutting process, so that the product yield due to the wiring pattern damage can be reduced. Drop can be prevented. Also, since no insulating debris enters the input / output terminals,
There is no contact failure between the input / output terminal and the FPC and an increase in contact resistance does not occur, so that a liquid crystal device of stable quality can be obtained.

[Brief description of the drawings]

FIG. 1 is an enlarged plan view showing the periphery of an input / output terminal of a liquid crystal device according to the present invention.

FIG. 2 is a sectional view taken along line B-B 'of FIG.

FIG. 3 is a cross-sectional view illustrating an example of an input / output terminal of the liquid crystal device according to the present invention.

FIG. 4 is a sectional view showing another example of the input / output terminal of the liquid crystal device according to the present invention.

5 (a) to 5 (e) are process cross-sectional views illustrating a method for manufacturing the input / output terminal of the liquid crystal device shown in FIG.

6 (a) to 6 (e) are cross-sectional views showing the steps performed after the step shown in FIG. 5 in the method for manufacturing the input / output terminal of the liquid crystal device shown in FIG.

7 (a) to 7 (c) are cross-sectional views showing the steps performed after the step shown in FIG. 6 in the method for manufacturing the input / output terminal of the liquid crystal device shown in FIG.

FIG. 8 is a diagram illustrating a flexible printed circuit board.

FIG. 9 is a diagram illustrating a bonding state between an input / output terminal and a flexible printed circuit board.

FIG. 10 is a block diagram illustrating a configuration of an active matrix substrate for an electro-optical device to which the present invention has been applied.

FIG. 11 is a plan view of an electro-optical device showing an example of use of an active matrix substrate.

FIG. 12 is a sectional view taken along the line HH ′ of FIG. 11;

[Explanation of symbols]

1 ... electro-optical device, 2 ... active matrix substrate,
3 ... Counter substrate, 4 ... Indium tin oxide (ITO)
Film, 6 ... Liquid crystal, 8 ... Pixel electrode, 9 ... Flexible printed circuit (FPC), 10 ... TFT for pixel, 14 ...
Insulating film, 15, 25, 35 ... gate electrode, 16, 17,
26, 27, 36 ... source / drain electrodes, 41 ... synthetic resin layer, 42 ... metal conductor, 43 ... metal particles, 44 ...
・ Adhesive, 45 ・ ・ ・ Adhesive tape, 60 ・ ・ ・ Data line pulsation circuit, 70 ・ ・ ・ Scan line drive circuit, 75 ・ ・ ・ Route wiring, 80
... Seal layer, 81 ... Input / output terminals, 81a ... First conductive film, 81b ... Second conductive film, 82 ... Sealant, 83 ...
Liquid crystal filling port, 84 opening, 90 data line, 91
..Scanning lines, 92 ... Capacitance lines, 94 ... Liquid crystal cells, 98 ...
Light-shielding film, 150 ... conductive film for forming a gate electrode, 160 ...
-Source / drain electrode forming conductive film, 200: insulating substrate, 201: base protective film, 401: lower interlayer insulating film, 402: upper interlayer insulating film, 403: transparent Resin film, 404 flattening film, 406 recess, 551, 55
2,553,554... Mask for patterning

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroyuki Murai 997 Miyoshi, Nishi-Koshi-cho, Kikuchi-gun, Kumamoto Prefecture F-term (reference) 2H092 GA43 GA50 JA24 KB22 KB23 MA07 MA13 MA29 MA30 MA37 NA15 NA16 PA06 5C094 AA32 BA03 BA43 CA19 DA09 DA15 EA03 EA04 EA07 FA04 FB02 FB12 FB15 GB01 5G435 AA16 BB12 CC09 HH12 HH14 KK05

Claims (11)

[Claims] A plurality of scanning lines and a plurality of data lines formed in a matrix on a substrate; switching means connected to the scanning lines and the data lines; and a pixel electrode connected to the switching means. What is claimed is: 1. A liquid crystal device comprising: a transparent insulating film around an input / output terminal; 2. The liquid crystal device according to claim 1, wherein a peripheral portion of the input / output terminal is a lead wiring portion. 3. The liquid crystal device according to claim 1, wherein a peripheral portion of the input / output terminal is a portion adjacent to the input / output terminal. 4. The liquid crystal device according to claim 3, wherein the thickness of the transparent insulating film is larger than the height of the input / output terminal, and the opening has no transparent insulating film above the input / output terminal. A liquid crystal device comprising an indium tin oxide film formed on an inner wall of a transparent insulating film and an input / output terminal surface. 5. The liquid crystal device according to claim 4, wherein the inner wall of the transparent insulating film in the opening has a tapered shape. 6. The liquid crystal device according to claim 4, wherein the liquid crystal device has a recess around the input / output terminal of the opening. 7. A method for manufacturing a liquid crystal device in which a thin film transistor and an input / output terminal are formed over an insulating substrate, wherein a first conductive film serving as an input / output terminal is formed over the insulating substrate.
By forming and etching a patterning mask for forming an input / output terminal on the conductive film of FIG.
Is formed on the substrate, and the insulating film at the input / output terminal portion is removed.
Forming a second conductive film of the input / output terminal by forming and etching a patterning mask for forming the input / output terminal on the second conductive film, A method for manufacturing a liquid crystal device, comprising: forming a transparent insulating film in a portion. 8. A method for manufacturing a liquid crystal device in which a thin film transistor and an input / output terminal are formed on an insulating substrate, wherein a first conductive film serving as an input / output terminal is formed on the insulating substrate.
By forming and etching a patterning mask for forming an input / output terminal on the conductive film of FIG.
Is formed on the substrate, and the insulating film at the input / output terminal portion is removed.
Forming a second conductive film of an input / output terminal by forming a patterning mask for forming an input / output terminal on the second conductive film and etching the second conductive film; A transparent insulating film is formed around the input / output terminals including over the conductive film, and then a patterning mask for forming the input / output terminals is formed and the transparent insulating film is etched to form openings in the input / output terminals. The inner surface of the opening and the second
A method for manufacturing a liquid crystal device, comprising: forming a conductive thin film on a conductive film according to (1). 9. The method for manufacturing a liquid crystal device according to claim 8, wherein when etching the transparent insulating film, the vicinity of the second conductive film is over-etched deeper than the upper surface of the second conductive film. Of manufacturing a liquid crystal device. 10. The method according to claim 7, wherein the first conductive film and the second conductive film are made of chromium (Cr). 11. The method for manufacturing a liquid crystal device according to claim 7, wherein the formation of the input / output terminals is performed simultaneously with the formation of the thin film transistors.