JP2001189321A - Lateral heterobipolar transistor and manufacturing method thereof - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To provide a hetero bipolar transistor having a small parasitic capacitance and a small parasitic resistance and capable of lowering the resistance of an internal base layer, and a method of manufacturing the same. A so-called SOI structure in which a Si substrate, a BOX layer, and a semiconductor layer are stacked. The semiconductor layer 152 includes a collector 101 made of silicon and a SiGeC /
Si layer 102 and emitter 1 made of n-type polysilicon
03 and an external base layer 104. Internal base layer 102a is composed of Si _1-x Ge x C _y layer. Utilizing the heterojunction, it possible to reduce the resistance of the internal base layer, and it is possible to suppress the diffusion of the impurity in the intrinsic base layer formed of Si _1-x Ge _x C _y layer which is formed by epitaxial growth.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral hetero-bipolar transistor and a method of manufacturing the same, and more particularly, to an SOI.
About those using (Silicon on Insulator) heterostructure _{Si / Si 1-x Ge x} Si / Si 1-xy Ge x C y or the like formed on an insulating substrate such as.

[0002]

2. Description of the Related Art Conventionally, an SOI (Silicon on Insulator) substrate formed by stacking a silicon layer on an insulating layer has been developed.
By forming a CMOS device or a bipolar transistor, a technique has been proposed for achieving low transistor operating voltage, complete isolation between elements, reduction of parasitic capacitance, and the like, and obtaining excellent characteristics of the transistor. .
In particular, in the transmitting / receiving section of communication equipment that handles high-frequency signals,
Crosstalk between an analog circuit and a digital circuit poses a problem. However, by using an SOI substrate, it is expected that crosstalk can be significantly removed as compared with the related art.

On the other hand, recently, a hetero-bipolar transistor using a heterostructure such as Si / SiGe has been put into practical use as an element which can operate in a high-frequency range, which has been considered difficult with technology using a silicon process. These use a heterostructure in which the bandgap of the base is smaller than the bandgap of the emitter, so that the back injection of carriers from the base to the emitter is suppressed, so that the impurity concentration of the base is higher than that of the Si homojunction bipolar transistor. As a result, excellent characteristics can be obtained as compared with the Si homojunction type bipolar transistor, such as the base resistance can be reduced.

In addition, in the BiCMOS technology accompanying the recent demand for a system-on-chip, it is required to form a CMOS device and a bipolar transistor on the same chip. However, when a bipolar transistor is to be formed on an SOI substrate, it is necessary to increase the thickness of the silicon layer to some extent in the structure of the conventional vertical bipolar transistor. And it is necessary to suppress leakage current. However, providing a silicon layer having different thicknesses in the CMOS device region and the bipolar transistor region complicates the process.

Therefore, a proposal has been made to form a lateral hetero-bipolar transistor on an SOI substrate in order to use a silicon layer having the same thickness as that of the CMOS device region also in the bipolar transistor region. That is, by adopting the lateral hetero bipolar transistor structure, a silicon layer having a common thickness can be used in both regions, and the process can be greatly simplified. In addition, there is a report that the use of a lateral hetero bipolar transistor structure has a smaller parasitic resistance than a vertical bipolar transistor formed using an SOI substrate, and is advantageous for high-speed operation.

FIGS. 10 (a) and 10 (b) show a literature (A 31 GHz f _max Lateral BJT on SOI Using Self-Algin) which is an example of an attempt of such a lateral hetero bipolar transistor.
ed External Base Formation Technology: T. Shino et.
al. 1998 IEEE) is a plan view and a cross-sectional view of a lateral hetero-bipolar transistor provided on an SOI disclosed in Japanese Patent Application Laid-Open No. H10-163, 1988. As shown in the figure, the lateral hetero bipolar transistor has a BOX layer 100 made of a silicon oxide film.
1 and a silicon layer 1009 are formed on an SOI substrate. With the use of an SOI substrate, parasitic capacitance in an operation region of a transistor can be reduced. The thickness of the silicon layer 1009 is 0.1 μm. The silicon layer 1009 includes a strip-shaped p-type internal base layer 1004 doped with boron (B) and an internal base layer 100.
4, two external base layers 1006 doped with boron (B) at a higher concentration than the internal base layer 1004, and provided on both sides of the long side of the internal base layer 1004. n-type emitter 1005 and collector 1
002. Emitter 1005 is doped with a high concentration of arsenic (As), and collector 1002 is doped with a non-uniform concentration of arsenic. That is, in the collector 1002, the arsenic concentration is low in a portion near the internal base layer 1004 and the external base layer 1006 in order to increase the breakdown voltage, and the arsenic concentration increases as the distance from the internal base layer 1004 and the external base layer 1006 increases. It has a retro grade structure like this. Also, the electrode formation portions of the external base layer 1006, the emitter 1005, and the collector 1002 are located outside of each region so that the parasitic capacitance between the base electrode, the emitter electrode, and the collector electrode is reduced. Is provided at the end on the side. This document reports that a maximum oscillation frequency fmax of 31 GHz was obtained by such a lateral heterobipolar transistor.

FIGS. 11A to 11E are perspective views showing a method for manufacturing a bipolar transistor described in the above-mentioned document.

First, in the step shown in FIG.
On the n-type silicon layer 1009 into which (P) is introduced,
After forming an oxide film and a SiN film (not shown),
Array type resist mass covering NPN active region on N
A mark 1108 is formed. Next, a resist mask 1108
Active region 110 of silicon layer 1009 from above
Boron (B) dose 4 × 10 in the region excluding 7^Fifteenatom
s · cm^-2Ion implantation at P⁺ Form a diffusion area
You. Next, in the step shown in FIG.
The SiN film was patterned using 1108 as a mask.
Then, a resist mask 1 is formed by inserting a side etch.
Offset inward from the end of 108 by about 0.2 μm
After forming the SiN mask 1110, a resist mask
1108 is removed. Next, the process shown in FIG.
And T is crossed with respect to the SiN mask 1110.
An EOS mask 1111 is formed, and a silicon layer 1
009, SiN mask 1110 and TEOS mask
Boron is added to the area except the area covered by 1111.
(B) with a dose of 1 × 10¹⁴atoms · cm^-2, Accelerated energy
Ions are implanted under the condition of 25 KeV of energy. Next, FIG.
1D, the SiN mask 1110 and TE
The OS mask 1111 is removed. At this time, the internal base
The width of the layer 1004 is such that the implanted boron is the TEOS mask 11.
11 is determined by the distance diffused from the end. Finally,
In the step shown in FIG.
After mesa etching the part, arsenic (As)
Dose 1 × 10 ^Fifteenatoms · cm^-2, Acceleration voltage 120k
eV condition and dose amount 1 × 10¹⁶atomscm^-2, Add
Ions are implanted under the condition of a fast voltage of 65 keV. Silicon layer
1009 is made amorphous by this ion implantation.
RTA at 1050 ° C for 20 sec.
Recrystallized with an electric furnace annealing at 60 ° C for 60 min.
You.

Through the above steps, a bipolar transistor which is lateral, has small parasitic capacitance, high fmax and can operate at high speed can be formed.

[0010]

However, in the prior art described in the above document, the internal base layer 11
Since the width of 04 is determined by the diffusion distance of boron, there is a problem that it is difficult to stably obtain a desired impurity distribution. In addition, the emitter 1105 and the collector 110
Since the formation range of 2 is also determined by the diffusion distance of the n-type impurity, there is a problem that it is difficult to form a steep pn junction.

An object of the present invention is to provide a lateral heterobipolar transistor having a stable characteristic by forming a width or the like of an internal base layer to a desired dimension with high accuracy when forming the lateral heterobipolar transistor on an SOI substrate. An object of the present invention is to provide a hetero bipolar transistor and a method for manufacturing the same.

[0012]

According to the first aspect of the present invention, there is provided a lateral heterobipolar transistor comprising: a substrate having an insulating layer;
A mesa-shaped first semiconductor layer provided on the insulating layer; and a second semiconductor layer formed by epitaxial growth on a side surface of the first semiconductor layer and having a different band gap from the first semiconductor layer. And a third semiconductor layer formed by epitaxial growth on the side surface of the second semiconductor layer and having a band gap different from that of the second semiconductor layer. At least a part of the second semiconductor layer is It is a two-conductivity-type internal base layer.

Thus, the lateral thickness of the second semiconductor layer serving as the internal base layer is determined by epitaxial growth, not by implantation of impurity ions. Therefore,
The lateral thickness of the internal base layer is formed with high precision. Further, since the internal base layer is formed by epitaxial growth instead of implantation of impurity ions, a structure capable of in-situ doping of impurities while growing laterally is provided. An impurity concentration distribution is obtained.

At least the first semiconductor layer serves as a collector of the first conductivity type, and at least a part of the third semiconductor layer serves as an emitter operation region of the first conductivity type.

By further providing a second conductive type external base layer in contact with the second semiconductor layer, the formation of the electrodes is facilitated.

Since the band gap of the second semiconductor layer is smaller than the band gap of the third semiconductor layer, the second semiconductor layer functioning as the internal base layer is shifted from the third semiconductor layer functioning as the emitter operation region. As a result of suppressing the reverse injection of carriers into the layer, it is possible to reduce the base resistance by setting the impurity concentration of the second semiconductor layer higher than that of the homojunction bipolar transistor.

The first and third semiconductor layers are composed of a silicon layer, and the second semiconductor layer is composed of an alloy containing at least two of Si, Ge and C. It is possible to form a hetero bipolar transistor in which diffusion of impurities is suppressed by using a silicon process.

The first semiconductor layer has a {110} plane, and a side surface of the first semiconductor layer which is in contact with the second semiconductor layer has a {111} plane. A smooth side surface using the wet etching of above is obtained.

According to the first method for manufacturing a lateral heterobipolar transistor of the present invention, a step (a) of forming an etching mask on the semiconductor layer of a substrate having a semiconductor layer provided on an insulating layer; (B) patterning the semiconductor layer by etching including dry etching to form a mesa-shaped first semiconductor layer using a mask; and forming the first semiconductor layer on at least one side surface of the first semiconductor layer. (C) epitaxially growing a second semiconductor layer having a different band gap from the first semiconductor layer; and forming a third semiconductor layer having a different band gap from the second semiconductor layer on a side surface of the second semiconductor layer. (D) epitaxially growing a semiconductor layer, wherein at least the first semiconductor layer functions as a collector of a first conductivity type, and At least a portion of the conductive layer and the second
In this method, at least a part of the third semiconductor layer functions as a first conductivity type emitter operating region.

According to this method, the first base layer serving as the internal base layer is formed.
Is determined not by implantation of impurity ions but by epitaxial growth. Therefore, the thickness of the internal base layer in the lateral direction becomes highly accurate. In addition, since the internal base layer is formed by epitaxial growth instead of implantation of impurity ions, it is possible to perform in-situ doping of impurities while growing in the lateral direction. A distribution is obtained.

In the step (b), after the semiconductor layer is patterned into the shape of an etching mask by dry etching, a side portion of the patterned semiconductor layer is wet-etched while the etching mask is left. Forming the first semiconductor layer is preferable because etching damage can be removed while maintaining high patterning accuracy.

After the step (d), a step (e) of depositing a polycrystalline semiconductor film on the substrate, and flattening the polycrystalline semiconductor film by CMP to form at least an emitter in contact with the third semiconductor layer. By further including the forming step (f), a low-resistance emitter adjacent to the emitter operation region can be easily formed.

During or after the step (e), a first conductivity type impurity is introduced into the first region of the polycrystalline semiconductor film, and a second conductivity type impurity is introduced into the second region. At least a portion of the crystalline semiconductor film located between the first and second regions is removed to form an emitter in contact with the third semiconductor layer from the first region, A step (g) of forming an external base layer in contact with the semiconductor layer from the second region, whereby a low-resistance emitter and an external base layer can be easily formed using a polycrystalline film such as polysilicon. can do.

It is preferable that the impurity be introduced by ion implantation using a mask.

The step (g) is preferably performed by wet etching.

In the step (a), a semiconductor layer having a principal surface of {110} is used as a semiconductor layer on the insulating layer, and in the step (b), the second semiconductor layer of the first semiconductor layer is formed. By forming the etching mask so that the side surface in contact with the semiconductor layer becomes {111} plane, a particularly flat etching surface with a low etching rate can be obtained.
Using the 1 ° plane, an internal base layer having a uniform thickness in the lateral direction can be obtained.

In the step (b), it is preferable to perform crystal anisotropic etching using an etching solution containing at least one of ethylenediamine, pyrocatechol, KOH and hydrazine.

A second lateral heterobipolar transistor according to the present invention is a lateral heterobipolar transistor provided on an insulating layer, and includes a first semiconductor layer serving as a collector and at least one of the first semiconductor layers. A second semiconductor layer provided in contact with one side surface and serving as an internal base layer having a band gap smaller than that of the first semiconductor layer; and a second semiconductor layer provided in contact with the side surface of the second semiconductor layer. A third semiconductor layer serving as an emitter having a larger band gap than the semiconductor layer, a first electrode and a second electrode which are in contact with side surfaces of the first and third semiconductor layers, A third electrode provided in contact with the upper surface.

As a result, a lateral heterobipolar transistor having a relatively simple structure and exhibiting excellent characteristics such as low parasitic capacitance and low parasitic resistance and low base resistance can be obtained on the insulating layer. .

Since the first and second electrodes are made of metal, the resistance of the emitter and the collector can be reduced.

According to a second method of manufacturing a lateral heterobipolar transistor of the present invention, a first semiconductor layer containing a first conductivity type impurity is provided on an insulating layer. (A) introducing a conductive impurity;
(B) forming an etching mask having a slit having a width of 200 nm or less on the first semiconductor layer;
(C) forming a groove penetrating through the first semiconductor layer by removing a portion of the semiconductor layer located below the slit by etching using the etching mask; (D) epitaxially growing a second semiconductor layer having a band gap different from that of the first semiconductor layer from both side surfaces of the groove so as to fill the groove, and forming the second semiconductor layer on both sides of the slit in the insulating layer. (E) forming an opening in a region located above the first semiconductor layer, and forming a void by performing wet etching of the first semiconductor layer from the opening of the insulating layer; A step (f) of leaving each part of the first semiconductor layer on both sides of the second semiconductor layer, and a step (g) of forming first and second electrodes that fill the gaps
And (g) forming a third electrode in contact with the second semiconductor layer by filling the slit of the insulating layer,
A method in which the respective portions of the first semiconductor layer left on both sides of the second semiconductor layer function as collector and emitter operation regions, respectively, and the second semiconductor layer functions as an internal base layer. is there.

According to this method, a lateral hetero-bipolar transistor which can exhibit excellent characteristics such as a small parasitic capacitance and a small parasitic resistance and a low base resistance can be formed on the insulating layer by a simple process.

In the above step (f), ethylenediamine,
It is preferable to perform crystal anisotropic etching using at least one of pyrocatechol, KOH, and hydrazine. In the step (a), a first conductivity type impurity ion is implanted into the first semiconductor layer. Performing a first ion implantation for implanting ions and a second ion implantation for implanting impurity ions having a higher concentration than the first ion implantation into a part of the first semiconductor layer. Is formed from a portion of the first semiconductor layer in which the first ion implantation is performed without performing the second ion implantation, and the emitter operation region is formed in the first semiconductor layer. By forming the emitter operation region and the collector from the portions where the first and second ion implantations have been performed, respectively, the impurity concentration is adjusted to be optimum for the operation of the bipolar transistor. It becomes possible to.

By using a silicon layer as the first semiconductor layer and using an alloy containing at least any two of Si, Ge, and C as the second semiconductor layer, a lateral heterostructure utilizing a silicon process is used. The manufacture of a bipolar transistor becomes possible.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
FIG. 2B is a plan view and a perspective view of the lateral hetero bipolar transistor according to the first embodiment of the present invention.

As shown in FIGS. 1A and 1B, the lateral hetero-bipolar transistor of the present embodiment includes a Si substrate 150 and a BOX layer 151 made of a silicon oxide film provided on the Si substrate 150. , A semiconductor layer 152 provided on the BOX layer 151, and has a so-called SOI structure. The semiconductor layer 152 includes a collector 101 made of n-type single crystal silicon having a substantially square planar shape, and an annular p-type Si surrounding the collector 101.
SiGeC / Si layer 1 composed of GeC layer and n-type Si layer
02, an emitter 103 made of n-type polysilicon,
and a p-type polysilicon layer 105. SiGeC
And collector 103 and emitter 103 of / Si layer 102
A portion formed by a p-type SiGeC layer (a portion inside the broken line in the drawing) interposed between the internal base layer 102a and the collector 101 and the emitter 103 of the SiGeC / Si layer 102. The portion interposed between the n-type Si layers (the portion outside the broken line in the figure) is the emitter operation region 102b,
An external base layer 104 is constituted by the portion 102c of the GeC / Si layer 102 excluding the internal base layer 102a and the emitter operation region 102b and the p-type polysilicon layer 105.

The collector 101 has a thickness of about 200 nm and a side length of about 0.6 μm. The collector 101 has an antimony (Sb) (phosphorus) concentration of about 1 × 10 ¹⁹ atoms · cm ^−3. Or arsenic). The main surface of the collector 101 is a (110) surface, and the side surface is a smooth (111) surface. However, the collector 101
May not be the (110) plane, and the side faces may be (11).
1) It does not have to be a plane. In the present embodiment,
The internal base layer 102a has a concentration of about 2 × 10 ¹⁸ atoms
Si _1-x Ge containing cm ⁻³ boron and having a graded composition
_x C _y layer, but not containing C
Ge may be constituted by (e.g., Si _1-x Ge _x having a graded composition). However, the presence of even a small amount of C has a particularly large effect of preventing the diffusion of impurities. Further, the emitter operation region 102b has a concentration of about 1
It is made of single crystal Si containing phosphorus of 10 ¹⁸ atoms · cm ⁻³ or more. The emitter 103 has a concentration of about 1 × 1
It is made of n-type polysilicon containing phosphorus of 0 ²⁰ atoms · cm ⁻³ or more. Note that arsenic may be doped instead of phosphorus. That is, the emitter operation area
Si / SiGeC / Si between the internal base layer and the collector
Is formed. Also, the external base layer 1
04 is made of polysilicon containing boron at a concentration of about 1 × 10 ²⁰ atoms · cm ⁻³ , and the external base layer 104 functions as a contact region for the internal base layer 102a.

The collector 101 has a retrograde structure in which the concentration of the n-type impurity (antimony) increases as the distance from the internal base layer 102a increases.
In the internal base layer 102a, Ge (or Ge) is used.
And C) have a gradient composition in which the content decreases as the distance from the collector 101 increases.
Has a structure in which the mobility of electrons in the substrate is increased.
However, it is not always necessary to provide a retrograde in the collector 101 or a gradient composition in the internal base layer 102a.

Next, a method of manufacturing the lateral hetero-bipolar transistor according to the present embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

First, in a step shown in FIG. 2A, a Si substrate 150, a BOX layer 151 made of a silicon oxide film,
An SOI substrate composed of a Si film formed on the BOX layer 151 is formed. The method for forming the SOI substrate is as follows:
Although any of the well-known methods (for example, SIMOX method) may be adopted, in the present embodiment, a silicon wafer having a silicon oxide film formed on the surface and a silicon wafer are separated.
A method is adopted in which silicon oxide films are bonded so as to be sandwiched between silicon wafers, and one of the silicon wafers is polished and thinned. The Si film on the BOX layer 151 is doped with antimony (may be arsenic or phosphorus) having a concentration of about 1 × 10 ¹⁹ atoms · cm ⁻³ . And
The Si film is patterned to form a square collector 101 (mesa) with rounded corners. At this time,
<2 formed on Si film whose main surface is (110) plane
The side surface of the collector 101 is made to be a very smooth (111) surface by wet etching using a square resist mask having sides parallel to the 11> direction, utilizing the anisotropy of the etch rate depending on the crystal orientation. Can be. However, the collector 101 may be formed by forming an etching mask on the Si film to cover the collector layer 101 and then performing dry etching using the etching mask.

Next, in the step shown in FIG.
(Chemical Vapor Deposition) or UHV-CV
D (Ultra High Vacuum-CVD)
An undoped Si layer having a thickness of about 120 nm, which becomes a part of the collector 101, is epitaxially grown on the side surface of the mesa portion 01. At this time, in the Si layer, antimony (S
b) is diffused to form a retrograde impurity concentration profile. Then, the concentration is 2 × 10 ¹⁸ atoms · c
While doping in-situ boron of about m ⁻³ , the C content is kept constant (about 2%), and the Ge content is tilted as shown in FIG. 80n
After the SiGeC layer having a thickness of m is epitaxially grown, an undoped Si layer having a lateral thickness of about 10 nm is formed, thereby forming the SiGeC / Si layer. As described above, since the SiGeC layer in the SiGeC / Si layer 102 contains 2% of C, diffusion of boron in a subsequent heat treatment step can be more reliably prevented,
A heterojunction having a steeper impurity concentration profile can be realized.

Next, after the polysilicon film 160 is deposited on the substrate in the step shown in FIG. 2C, the polysilicon film 160 is removed by CMP (Chemical Mech) in the step shown in FIG.
hanical Polishing) or the like to etch back and flatten.

Next, in a step shown in FIG. 2E, after an oxide film 161 is formed on the substrate, a portion of the polysilicon film 160 which becomes the external base layer 104 has a boron concentration of about 1%.
Boron ions are implanted so as to be not less than × 10 ²⁰ atoms · cm ⁻³ , and phosphorus (which may be arsenic or antimony) has a concentration of about 1 × 10 ²⁰ atoms in a portion serving as the emitter 103.
-Doping is performed by ion implantation so as to be not less than cm ^-3 . After the step shown in FIG.
Illustration of the substrate 150 and the BOX layer 151 is omitted.

Next, since the external base layer 104 and the emitter 103 may leak through the undoped portion of the polysilicon film 160 in this state, a part of the polysilicon film 160 is removed by the following process. Both are electrically insulated. That is, FIG.
In the step shown in FIG. 3F, the oxide film 1 is separated from the portion of the polysilicon film 160 into which the impurity ions have been implanted at a predetermined distance.
After forming an opening in 61, in the step shown in FIG.
The etching is performed until the GeC / Si layer 102 is reached. At this time, by using an etching solution having a high etching selectivity between polysilicon and Si, SiGeC / S
Insulation can be achieved without damaging the i-layer 102. Thereafter, heat treatment (annealing) for activating the ion-implanted impurities is performed. By this heat treatment, n-type impurities such as phosphorus doped in the polysilicon of the emitter 103 diffuse to the undoped silicon of the emitter operation region 102b, and function as the emitter region of the npn bipolar transistor.

Next, in the step shown in FIG.
By removing 61, a lateral hetero bipolar transistor having the structure shown in FIG. 1B is obtained.

FIGS. 3A and 3B are views for explaining a lateral impurity profile in the region A shown in FIG. 2H of the lateral heterobipolar transistor of the present embodiment. FIGS. 4A and 4B are views for explaining a lateral impurity profile in a region B shown in FIG. 2H of the lateral heterobipolar transistor of the present embodiment.

FIGS. 3A and 3B and FIGS.
As shown in (b), in the collector 101, a retrograde distribution is formed in which the concentration of Sb, which is an impurity, increases from the near side to the far away from the internal base layer 102a in order to increase the breakdown voltage. . The Ge content in the internal base layer 102a is inclined to generate a drift electric field. Although the phosphorus concentration in the emitter 103 made of polysilicon is constant at a high concentration of about 5 × 10 ²⁰ atoms · cm ⁻³ , the internal base layer 1 is diffused.
02a. It is desirable that this diffusion concentration is as low as possible. Although the external base layer 104 is doped with boron at a high concentration, the internal base layer
Since an impurity having the same polarity as a is doped, it is electrically integrated with the internal base layer 102a and is maintained at substantially the same potential.

According to the present embodiment, the inner base layer 102
a in the lateral direction, not by implantation of impurity ions,
Since the thickness is determined by epitaxial growth using -situ doping, the thickness of the internal base layer 102a in the lateral direction does not depend on the accuracy of photolithography or the degree of impurity diffusion. Further, since the internal base layer 102a is formed not by implantation of impurity ions but by epitaxial growth by in-situ doping, diffusion of impurities is suppressed, and a relatively steep impurity concentration distribution is obtained.
Moreover, in the present embodiment, the inner base layer 102a
Is constituted by the SiGeC layer, the diffusion of impurities in the heat treatment step is suppressed by the presence of C, and the impurity concentration profile is maintained without being destroyed. Even if the internal base layer 102a is formed of a SiGe layer instead of a SiGeC layer, the effect of maintaining an impurity concentration profile properly is not sufficient because the diffusion speed of impurities in the SiGe layer is lower than the diffusion speed in the Si layer. Can be obtained to some extent.

In addition, since the lateral heterobipolar transistor of the present embodiment utilizes the SiGeC / Si heterojunction, the lateral heterobipolar transistor described in the above document using a Si homojunction has the following advantages. The effect of can be exhibited. That is, since the bandgap of the internal base layer is smaller than the bandgap of the emitter operation region, reverse injection of carriers from the internal base layer to the emitter operation region is suppressed. When the concentration is higher than that in the transistor, the base resistance can be reduced.

Since the SOI substrate is used, a lateral hetero-bipolar transistor suitable for high-speed operation with small parasitic capacitance and high fmax can be obtained as in the technique of the above-mentioned document.

In the structure shown in FIG.
The mesa-shaped single-crystal Si layer denoted by reference numeral 1 is used as an emitter instead of a collector, and the polysilicon layer denoted by reference numeral 103 is used as a collector extraction layer instead of an emitter, and reference numeral 102b is used.
May be used as a collector. In this case, a bipolar transistor having a particularly high withstand voltage can be obtained. In this case, the single crystal S
The i region preferably has a lateral thickness of about 0.2 μm or more. Like the collector according to the present embodiment, in order to increase the withstand voltage, the impurity Sb, which is closer to the inner base layer 102a and further away from the internal base layer 102a, is increased. It is more preferable to form a retrograde distribution in which the concentration of is increased.

(Second Embodiment) Next, a second embodiment which is a modification of the lateral hetero bipolar transistor in the first embodiment will be described.

FIG. 5 is a plan view of the lateral hetero bipolar transistor of the present embodiment. In the present embodiment, the structure of a portion functioning as an npn transistor is:
This is the same as the first embodiment.

As shown in the figure, the lateral hetero-bipolar transistor of the present embodiment has a Si substrate and a BOX layer made of a silicon oxide film provided on the Si substrate, as in the first embodiment. A semiconductor layer provided on the BOX layer to form a so-called SOI structure. FIG. 5 shows only the semiconductor layer. The semiconductor layer is provided with a linear SiGeC / Si layer 112 including a p-type SiGeC layer and an n-type Si layer.
On both sides of the iGeC / Si layer 112, a collector 111 made of single crystal silicon containing an n-type impurity and an emitter 113 made of polysilicon containing an n-type impurity are provided. An external base layer 114 made of a polysilicon layer containing a p-type impurity is provided at both ends of the central linear portion of the SiGeC / Si layer 112. And
The portion of the SiGeC / Si layer 112 constituted by the p-type SiGeC layer (the hatched portion in the figure) is the internal base layer 112a, and the n-type Si layer of the SiGeC / Si layer 112 (the portion shown in the figure) The portion constituted by the white portion) is the emitter operation region 112b.

The collector layer 111 has a thickness of about 200 nm, a side length of about 1.0 μm, and an antimony (phosphorous or arsenic) having a concentration of about 1 × 10 ¹⁹ atoms · cm ^−3. May be doped). The main surface of the collector 111 is a (110) surface, and the side surface is a smooth (111) surface. In the present embodiment,
The internal base layer 112a has a concentration of about 2 × 10 ¹⁸ atoms
Si _1-x Ge containing cm ⁻³ boron and having a graded composition
_x C _y layer, but not containing C
Ge may be constituted by (e.g., Si _1-x Ge _x having a graded composition). However, the presence of even a small amount of C has a particularly large effect of preventing the diffusion of impurities. Further, the emitter operation region 112b has a concentration of about 1
It is composed of single crystal Si containing phosphorus (or arsenic) of at least × 10 ¹⁸ atoms · cm ⁻³ . Emitter 113 is made of n-type polysilicon containing phosphorus (or arsenic) having a concentration of about 1 × 10 ²⁰ atoms · cm ⁻³ or more. That is, a hetero junction of Si / SiGeC / Si is formed between the emitter operation region, the internal base layer, and the collector. The external base layer 114 has a concentration of about 1 × 10
^The outer base layer 114 is made of polysilicon containing ²⁰ atoms · cm ⁻³ boron, and the inner base layer 11
It functions as a contact region for 2a. Further, the external base layer 114 and the collector 111 are connected to each other by the first insulating film 115.
3 are electrically insulated from each other by the second insulating film 116.

The collector 111 has a retrograde structure in which the concentration of the n-type impurity (antimony) increases as the distance from the internal base layer 112a increases.
In the internal base layer 112a, Ge (or Ge) is used.
And C) have a gradient composition in which the content decreases as the distance from the collector 111 increases.
Has a structure in which the mobility of electrons in the substrate is increased.
However, it is not always necessary to provide a retrograde in the collector 111 or a gradient composition in the internal base layer 112a.

Next, a brief description will be given of a method of manufacturing the lateral hetero bipolar transistor of the present embodiment.

Also in this embodiment, the planar shape of the lateral hetero bipolar transistor is different from that of the first embodiment, but the basic manufacturing process is the same as that of the first embodiment. That is, after forming an SOI substrate composed of a Si substrate, a BOX layer and a Si film, the mesa portion of the collector 111 is formed by patterning the Si film. At this time, by the same processing as in the first embodiment, the collector 111
Can be made a very smooth (111) plane. Next, the other side surface of the mesa portion of the collector 111 is covered with the first insulating film 115 and only one side surface is exposed, and then the collector 111 is placed on the one side surface by CVD or UHV-CVD. An undoped Si layer as a part is epitaxially grown. Next, this undoped Si
After epitaxially growing a SiGeC layer having a C content of 2% and an inclined Ge content on the layer, an undoped Si layer is further formed to form a SiGeC layer.
A C / Si layer 112 is formed. Then, after depositing a polysilicon film on the substrate, the polysilicon film is etched back and flattened. The external base layer 114 of the polysilicon film
Boron ions are implanted into
After phosphorus ions are implanted into the parts to be patterned, the polysilicon film is patterned and the insulator is buried,
The emitter 113 and the external base layer 114 are electrically insulated from each other by the second insulating film 116.

Thereafter, heat treatment (annealing) for activating the ion-implanted impurities is performed. By this heat treatment, n-type impurities such as phosphorus doped in the polysilicon of the emitter 113 diffuse to the undoped silicon of the emitter operation region 112b, and function as an emitter region of the npn bipolar transistor. Antimony (Sb) diffuses from the mesa portion of the collector 111 in the Si layer which is a part of the collector 111 in the epitaxial layer, thereby forming a retrograde impurity concentration profile.

Also in the present embodiment, the conditions for implanting impurities and the types of ions to be implanted in the above manufacturing process are the same as those in the first embodiment.

In this embodiment, basically, the same effects as those of the first embodiment can be obtained. However, considering the contact with the electrodes, the first embodiment has a larger area of the entire bipolar transistor. There is an advantage that it can be small.

(Third Embodiment) FIGS. 6A and 6B
FIGS. 4A and 4B are a plan view and a sectional view of a lateral heterobipolar transistor according to a third embodiment of the present invention. FIGS.

As shown in FIGS. 6A and 6B, the lateral hetero-bipolar transistor of this embodiment has a Si substrate 250 and a BOX layer 251 made of a silicon oxide film provided on the Si substrate 250. , A semiconductor layer 252 provided on the BOX layer 251, and has a so-called SOI structure. The semiconductor layer 252 is provided with an internal base layer 202a made of a p-type SiGe layer having a linear planar structure, and a collector made of n-type single crystal silicon is provided on both sides of the internal base layer 202a. 201a and an emitter 2 made of n-type single crystal silicon
03a. Further, the lateral heterobipolar transistor of this embodiment has an oxide film 206 covering the semiconductor layer 252 and an external base layer 202b made of p-type polysilicon contacting the internal base layer 202a through the opening of the oxide film 206. A collector contact 201b made of n-type polysilicon buried in a groove formed in oxide film 206 and collector 201a;
6 and an emitter contact 203b made of n-type polysilicon buried in a groove formed in the emitter 203a.
And

In this embodiment, the main surfaces of the collector 201 and the emitter 203 are (100) planes, but the main surfaces of the collector 201 and the emitter 203 are (110) planes as in the first and second embodiments. As the side is smooth (1
11) It may be a surface. Collector 201 and emitter 2
03 is doped with phosphorus at a concentration of about 1 × 10 ¹⁸ atoms · cm ⁻³ . In the present embodiment, the concentration of the internal base layer 202a is about 5 × 10 ¹⁸ atoms · cm ^−3.
Containing boron and having a composition represented by Si _0.7 Ge _0.3
Although composed of an iGe layer, a small amount of C (for example, about 2%) may be contained. By including a small amount of C, the effect of preventing diffusion of impurities is particularly increased. Collector contact 201b, emitter contact 203
b and the external base layer 202b have a concentration of about 1 × 10 ²⁰ at
oms · cm ^-3 or more of phosphorus is doped.

Next, the manufacturing process of the lateral hetero bipolar transistor of the present embodiment will be described with reference to FIGS.
This will be described with reference to FIG. 7A to 7E are cross-sectional views illustrating the steps of manufacturing the lateral hetero bipolar transistor of the present embodiment.

First, in the step shown in FIG. 7A, a Si substrate 250, a BOX layer 251 made of a silicon oxide film,
An SOI substrate composed of a Si film (semiconductor layer) formed on the BOX layer 251 is formed. Semiconductor layer 25
2 has a thickness of about 200 nm, and the semiconductor layer 252 is doped with phosphorus having a concentration of about 1 × 10 ¹⁸ atoms · cm ⁻³ .

Next, in the step shown in FIG. 7B, an oxide film 206 is formed on the semiconductor layer 252, and a slit 207 is formed at the center of the oxide film 206, and then, as shown in FIG. In the step, the slit 207 is penetrated to the semiconductor layer 252.

Next, in the step shown in FIG. 7D, S or S is applied from both sides of the slit 207 by CVD or UHV-CVD.
i _0.7 Ge _0.3 is epitaxially grown, and united at the center of the slit 207 to form an internal emitter layer 202 a buried in the slit 207. At this time,
Boron having a concentration of about 5 × 10 ¹⁸ atoms · cm ⁻³ is contained in the internal emitter layer 202a by in-situ doping. After that, grooves are formed by dry etching in regions on both sides of the oxide film 206 that are about 200 nm away from the slits, and the grooves 208 and 209 that are enlarged to the semiconductor layer 252 are formed by wet etching. At this time, the grooves 2 are formed by the isotropic etching action of the wet etching.
08, 209 expands in the horizontal direction, and the end is slit 2
From the position of 07 to the position of about 100 nm.

Next, in the step shown in FIG.
Embedding a metal such as aluminum in 8,209,
Collector contact 201b and emitter contact 2
03b is formed. Further, after depositing a polysilicon film doped with boron at a high concentration on the substrate, the polysilicon film is patterned to form an external base layer 202b that is in contact with the internal base layer 202a at the slit 207.

According to the lateral hetero bipolar transistor of the present embodiment, since the internal base layer 202a is constituted by the SiGe layer formed by epitaxial growth, a heterojunction having a relatively steep concentration profile is formed as described above. be able to.

In addition, according to the method of the present embodiment, since the internal base layer 202a and the external base layer 202B are connected in a self-aligned manner, the parasitic resistance is reduced, and especially the parasitic capacitance can be significantly reduced. . Further, since the collector contact 201b and the emitter contact 203b can be made of a buried metal, the parasitic resistance of each contact is reduced, and a lateral hetero-bipolar transistor having good characteristics can be formed.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
FIG. 4 is a plan view of a lateral heterobipolar transistor according to the embodiment. Although a plan view is omitted in the present embodiment, the lateral heterobipolar transistor of the present embodiment has basically the same planar structure as the third embodiment.

As shown in FIG. 8, the lateral heterobipolar transistor of the present embodiment has basically the same structure as that of the third embodiment, but the impurity concentrations of the emitter 203a and the collector 201a are different from each other. Is different. The other structure is the same as that of the third embodiment.

That is, in the present embodiment, the emitter 203a is doped with antimony (Sb) at a high concentration of about 1 × 10 ²⁰ atoms · cm ⁻³ or more, and the collector 201a is doped with about 1 × 10 ¹⁷ atoms. ^-A relatively low concentration of antimony (Sb) of cm ^-3 is doped. As described above, the emitter 203a and the collector 201a are each doped with an impurity to an optimum concentration, so that the emitter 2
03a through the internal base layer 202a to the collector 201
Electrons can be efficiently injected into a, and in this embodiment, in addition to the effects of the third embodiment, a high-speed and high-gain transistor operation can be realized.

Next, the manufacturing process of the lateral hetero bipolar transistor of the present embodiment will be described with reference to FIGS.
This will be described with reference to FIG. FIGS. 9A to 9E are cross-sectional views illustrating the manufacturing steps of the lateral heterobipolar transistor of the present embodiment.

First, in the step shown in FIG. 9A, a Si substrate 250, a BOX layer 251 made of a silicon oxide film,
An SOI substrate composed of a Si film (semiconductor layer) formed on the BOX layer 251 is formed. Semiconductor layer 25
2 has a thickness of about 200 nm. Then, the semiconductor layer 25
2, a resist mask 220 having an opening wider than a region including the emitter formation region and the collector formation region
Is formed, and antimony (Sb) ions are implanted into the semiconductor layer 252 from above the resist mask 220.
The implantation is performed under the condition that the concentration in the region 52 becomes about 1 × 10 ¹⁷ atoms · cm ⁻³ . By this step, the low-concentration impurity-implanted region 210 to be a collector later is formed in the semiconductor layer 252.
Then, a high-concentration impurity implantation region 211 to be an emitter later is formed.

Next, in a step shown in FIG. 9B, an oxide film 206 is formed on the semiconductor layer 252, and the oxide film 206 includes an emitter forming region of a region into which antimony ions have been implanted. Further, a resist mask 221 having an opening overlapping with a region for forming a slit for forming a base is formed, and antimony (Sb) ions are doped into the semiconductor layer 252 from above the resist mask 221 in the semiconductor layer 252. Is about 1 × 10 ²⁰ atoms · c
The injection is performed under the condition of m- ³ .

Thereafter, in the step shown in FIG. 9C, a slit 207 is formed at the center of the oxide
In the step shown in FIG. 4D, the slit 207 is formed in the semiconductor layer 252.
Through.

Next, in the step shown in FIG. 9E, S or S is applied from both sides of the slit 207 by CVD or UHV-CVD.
i _0.7 Ge _0.3 is epitaxially grown, and united at the center of the slit 207 to form an internal emitter layer 202 a buried in the slit 207. At this time,
Boron having a concentration of about 5 × 10 ¹⁸ atoms · cm ⁻³ is contained in the internal emitter layer 202a by in-situ doping. Thereafter, a groove is formed by dry etching in a region on both sides of the oxide film 206 which is about 200 nm away from the slit, and further a groove 208 expanded to the semiconductor layer 252 and the lightly doped region 210 by wet etching.
And a groove 209 that extends to the semiconductor layer 252 and the high-concentration impurity implantation region 211. At this time, the grooves 20 are formed by the isotropic etching action of the wet etching.
8 and 209 are expanded in the horizontal direction, and the ends thereof are slits 20.
7 to a position of about 100 nm.

Next, in the step shown in FIG.
Embedding a metal such as aluminum in 8,209,
Collector contact 201b and emitter contact 2
03b is formed. Further, after depositing a polysilicon film doped with boron at a high concentration on the substrate, the polysilicon film is patterned to form an external base layer 202b that is in contact with the internal base layer 202a at the slit 207.

According to the lateral hetero bipolar transistor of this embodiment, the emitter 203a and the collector 201a
Can be adjusted to a concentration more suitable for the operation of the bipolar transistor. In addition to the same effects as in the third embodiment, the impurity concentration of the emitter 203a and the collector 201a are different from each other by a simple process. A density profile can be realized.

[0082]

As described above, the present invention is to form a lateral heterobipolar transistor having a SiGeC base and having a small parasitic capacitance and parasitic resistance and capable of high-speed operation on an SOI substrate by a simple process. Can be.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a perspective view of a lateral heterobipolar transistor according to a first embodiment of the present invention.

FIGS. 2A to 2H are cross-sectional views illustrating a method for manufacturing a lateral heterobipolar transistor according to the first embodiment of the present invention.

FIGS. 3A and 3B are diagrams for explaining a lateral impurity profile in a region A shown in FIG. 2H of the lateral heterobipolar transistor according to the first embodiment;

FIGS. 4A and 4B are diagrams for explaining a lateral impurity profile in a region B shown in FIG. 2H of the lateral heterobipolar transistor according to the first embodiment;

FIG. 5 is a plan view of a lateral heterobipolar transistor according to a second embodiment.

FIGS. 6A and 6B are a plan view and a cross-sectional view of a lateral heterobipolar transistor according to a third embodiment.

FIGS. 7A to 7E are cross-sectional views illustrating manufacturing steps of the lateral hetero-bipolar transistor according to the third embodiment.

FIG. 8 is a plan view of a lateral heterobipolar transistor according to a fourth embodiment.

FIGS. 9A to 9E are cross-sectional views illustrating a manufacturing process of the lateral hetero bipolar transistor according to the fourth embodiment.

FIGS. 10A and 10B are a plan view and a cross-sectional view of a horizontal bipolar transistor in a conventional document.

FIGS. 11A to 11E are cross-sectional views illustrating a manufacturing process of a horizontal bipolar transistor in a conventional document.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Collector 102a Internal base layer 102b Emitter operation area 103 Emitter 104 External base layer 105 P-type polysilicon layer 111 Collector 112a Internal base layer 112b Emitter operation area 113 External base layer 114 Emitter 115 p-type polysilicon layer 150 Si substrate 151 BOX layer 152 semiconductor layer 160 polysilicon film 161 oxide film 201a collector 201b collector contact 202a internal base layer 202b external base layer 203a emitter 203b emitter contact 206 oxide film 207 slit 250 Si substrate 251 BOX layer 252 semiconductor layer

Claims (20)

[Claims] A substrate having an insulating layer; a first mesa-shaped semiconductor layer provided on the insulating layer; and a first semiconductor formed by epitaxial growth on a side surface of the first semiconductor layer. A second semiconductor layer having a band gap different from that of the layer; and a third semiconductor layer formed by epitaxial growth on a side surface of the second semiconductor layer and having a different band gap from the second semiconductor layer. A lateral hetero-bipolar transistor, wherein at least a part of the second semiconductor layer is an internal base layer of a second conductivity type. 2. The lateral hetero-bipolar transistor according to claim 1, wherein at least said first semiconductor layer serves as a collector of a first conductivity type, and at least a part of said third semiconductor layer operates as an emitter of a first conductivity type. A lateral hetero-bipolar transistor characterized by being a region. 3. The lateral hetero-bipolar transistor according to claim 1, further comprising a second conductivity type external base layer in contact with said second semiconductor layer. 4. The lateral hetero-bipolar transistor according to claim 1, wherein a band gap of the second semiconductor layer is smaller than a band gap of the third semiconductor layer. 5. The lateral hetero-bipolar transistor according to claim 1, wherein said first and third semiconductor layers are made of a silicon layer, and said second semiconductor layer is made of Si. , Ge and C are made of an alloy containing at least two of them. 6. The lateral hetero-bipolar transistor according to claim 1, wherein a main surface of said first semiconductor layer is a {110} plane, and said first semiconductor layer has a main surface of {110}. A lateral heterobipolar transistor, wherein a side surface in contact with the second semiconductor layer is a {111} plane. 7. A step (a) of forming an etching mask on the semiconductor layer of a substrate having a semiconductor layer provided on an insulating layer, and etching the semiconductor layer by dry etching using the etching mask. (B) forming a first semiconductor layer in the shape of a mesa by patterning the first semiconductor layer; and forming a second semiconductor layer having a band gap different from that of the first semiconductor layer on at least one side surface of the first semiconductor layer. (C) epitaxially growing a semiconductor layer; and (d) epitaxially growing a third semiconductor layer having a band gap different from that of the second semiconductor layer on a side surface of the second semiconductor layer. At least the first semiconductor layer functions as a collector of a first conductivity type, and at least a part of the second semiconductor layer functions as an internal base layer of a second conductivity type. Is capacity, the third
Characterized in that at least a part of the semiconductor layer of (1) functions as a first-conductivity-type emitter operation region. 8. The method of manufacturing a lateral heterobipolar transistor according to claim 7, wherein in the step (b), the semiconductor layer is patterned into an etching mask shape by dry etching.
A method for manufacturing a lateral hetero-bipolar transistor, wherein the first semiconductor layer is formed by wet-etching a side portion of the patterned semiconductor layer while leaving the etching mask. 9. The method for manufacturing a lateral heterobipolar transistor according to claim 7, wherein, after the step (d), a step (e) of depositing a polycrystalline semiconductor film on a substrate; (F) planarizing by CMP to form at least an emitter in contact with the third semiconductor layer. 10. The method for manufacturing a lateral heterobipolar transistor according to claim 7, wherein a first conductivity type impurity is added to the first region of the polycrystalline semiconductor film during or after the step (e). In the area of the second
Impurities of the conductivity type are respectively introduced, at least a portion of the polycrystalline semiconductor film located between the first and second regions is removed, and an emitter in contact with the third semiconductor layer is removed from the first semiconductor layer. A method of manufacturing a lateral heterobipolar transistor, further comprising a step (g) of forming an external base layer in contact with the second semiconductor layer from the second region, while forming the external base layer from the second region. 11. The method for manufacturing a lateral hetero bipolar transistor according to claim 10, wherein the introduction of the impurity is performed by ion implantation using a mask. 12. The method according to claim 11, wherein the step (g) is performed by wet etching. 13. The method for manufacturing a lateral heterobipolar transistor according to claim 7, wherein in the step (a), a main surface of the semiconductor layer on the insulating layer is a {110} plane. And in the step (b), the etching mask is formed such that a side surface of the first semiconductor layer in contact with the second semiconductor layer becomes a {111} plane. Of manufacturing a lateral hetero bipolar transistor. 14. The method for manufacturing a lateral heterobipolar transistor according to claim 7, wherein in the step (b), at least one of ethylenediamine, pyrocatechol, KOH, and hydrazine is used. A method for manufacturing a lateral hetero-bipolar transistor, comprising performing crystal anisotropic etching using an etching solution containing: 15. A lateral heterobipolar transistor provided on an insulating layer, wherein the first semiconductor layer serving as a collector is provided in contact with at least one side surface of the first semiconductor layer, and A second semiconductor layer serving as an internal base layer having a band gap smaller than that of the first semiconductor layer, and a second semiconductor layer provided in contact with a side surface of the second semiconductor layer;
A third semiconductor layer serving as an emitter having a band gap larger than that of the first and second semiconductor layers; a first electrode and a second electrode contacting side surfaces of the first and third semiconductor layers; And a third electrode provided in contact with the upper surface of the transistor. 16. The lateral hetero bipolar transistor according to claim 15, wherein said first and second electrodes are made of metal. 17. A step (a) of introducing a first conductivity type impurity into the first semiconductor layer of a substrate provided with a first semiconductor layer containing the first conductivity type impurity on an insulating layer; Step (b) of forming an etching mask having a slit with a width of 200 nm or less on the first semiconductor layer, and removing a portion of the semiconductor layer located below the slit by etching using the etching mask. (C) forming a groove penetrating the first semiconductor layer, and a second semiconductor having a band gap different from the first semiconductor layer from both side surfaces of the groove in the first semiconductor layer. (D) epitaxially growing a layer so as to fill the groove, and (e) forming an opening in a region of the insulating layer located above the first semiconductor layer on both sides of the slit. Up To form a void portion through the opening portion of the insulating layer by performing wet etching of the first semiconductor layer,
A step (f) of leaving each part of the first semiconductor layer on both sides of the second semiconductor layer, a step (g) of forming first and second electrodes for filling the voids, (H) forming a third electrode in contact with the second semiconductor layer by filling the slit of the layer, wherein the third electrode is left on both sides of the second semiconductor layer in the first semiconductor layer. A method for manufacturing a lateral hetero-bipolar transistor, wherein the respective portions function as collector and emitter operation regions, respectively, and the second semiconductor layer functions as an internal base layer. 18. The method for manufacturing a lateral heterobipolar transistor according to claim 17, wherein in the step (f), a crystal anisotropic etching using at least one of ethylenediamine, pyrocatechol, KOH and hydrazine is performed. A method of manufacturing a lateral hetero-bipolar transistor. 19. The method for manufacturing a lateral heterobipolar transistor according to claim 17, wherein in the step (a), a first ion implantation for implanting a first conductivity type impurity ion into the first semiconductor layer is performed. And a second ion implantation for implanting a higher concentration of impurity ions than a part of the first ion implantation into a part of the first semiconductor layer. Forming a portion of the layer where the first ion implantation has been performed without performing the second ion implantation, and forming the emitter operation region in the first semiconductor layer of the first and second layers; A method for manufacturing a lateral heterobipolar transistor, wherein the method is formed from a portion where a second ion implantation has been performed. 20. The method for manufacturing a lateral heterobipolar transistor according to claim 17, wherein a silicon layer is used as the first semiconductor layer, and Si, A method for manufacturing a lateral hetero-bipolar transistor, comprising using an alloy containing at least two of Ge and C.