JP2001186014A - Phase synchronization device, phase synchronization method, and communication device - Google Patents

Abstract

(57) [PROBLEMS] To provide a phase synchronizer capable of performing high-speed switching of a frequency in an asynchronous state by using a dead zone existing in an output signal of a phase comparator and reducing a spurious amount in a synchronous state. The purpose is to provide. A phase comparator that generates a phase difference signal, a phase advancer that generates a phase advance signal by advancing the phase of the phase difference signal, and a phase delay signal that generates a phase difference signal by delaying the phase of the phase difference signal It comprises a phase delay unit, a combiner that combines the phase advanced signal and the phase delay signal to generate a corrected phase difference signal, and an oscillator that is frequency-controlled based on the corrected phase difference signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronizer, and more particularly, to an improvement of a phase synchronizer which is used as a frequency synthesizer of a communication device and generates a predetermined frequency signal.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing an example of a conventional phase synchronizer.
The configuration of the LL frequency synthesizer is shown. 1 is P
LL (Phase locked loop), 2 is LPF (low pass fi
lter), 3 is VCO (voltage control oscillator),
Reference numeral 10 denotes a crystal oscillator, 11 denotes a reference frequency divider, 12 denotes a comparison division cycle, 13 denotes a phase comparator, and 14 denotes a charge pump.

[0003] This phase synchronizer has PLL1, LPF2
And VCO3. The PLL 1 detects a frequency difference and a phase difference between the feedback VCO output signal fv and the reference signal fr generated inside the PLL, and outputs a control signal fc for reducing these differences to the LPF 2. The LPF 2 outputs a control voltage signal Vc obtained by smoothing the control signal fc and removing high-frequency components. VCO
3 changes the internal oscillation frequency based on the control voltage signal Vc so as to lock the oscillation frequency to the reference signal fr.
Generate the output signal fv.

The PLL 1 further includes a crystal oscillator 10, a reference frequency divider 11, a comparison frequency divider 12, a phase comparator 13, and a charge pump 14. Crystal oscillator 10
Generates an oscillation signal fx of a predetermined frequency, and generates a reference frequency divider 1
1 divides the oscillation signal fx and outputs a reference signal fr having a reference frequency. On the other hand, the comparison frequency divider 12 divides the frequency of the VCO output signal fv and outputs a comparison signal fp. Then, the phase comparator 13 compares the phase of the reference signal fr with the phase of the comparison signal fp, and outputs a phase difference signal f based on the comparison result.
u and fd are output.

The phase difference signal fu (up pulse) is a signal output as a phase difference when the phase of the comparison signal fp is ahead of the reference signal fr, and the phase difference signal fd (down pulse) Is a signal that is output as the phase difference when the phase of the comparison signal fp is behind the reference signal fr. The charge pump 14 obtains a difference between DC components obtained by integrating the phase difference signals fu and fd, and outputs the difference as a control signal fc.

The control signal fc is converted into a control voltage signal Vc in the LPF 2 and input to the VCO 3 as a correction value of the oscillation frequency. Then, the VCO 3 generates a VCO output signal fv having a frequency corresponding to the voltage value of the control voltage signal Vc, and the VCO output signal fv is fed back to the comparison frequency divider 12.

By repeating such an operation, the comparison signal fp obtained by dividing the VCO output signal fv based on the set frequency is finally locked to the reference signal fr, and as a result, the VCO output signal fv becomes Locked to the reference signal fr.

In such a conventional phase synchronizer, there is a problem that frequency stability and pull-in characteristics (frequency switching time) cannot be compatible. The frequency switching time in the phase synchronizer of FIG. 9, that is, the time from when the set frequency is switched to when the output frequency is synchronized with the reference frequency, cannot be shorter than the time constant of the LPF 2 in the loop.

If the time constant of the LPF is shortened, the frequency switching time can be shortened.
The frequency stability of the output signal is degraded. Conversely, LP to remove harmonic components etc. and obtain a stable output signal
If the band of F2 is narrowed, the time constant becomes large and the frequency switching time becomes long. That is, there is a strong correlation between the pull-in characteristic (frequency switching time) and the frequency stability, and there is a problem that the frequency switching time cannot be shortened without deteriorating the frequency stability.

FIG. 10 is a diagram showing the relationship between the phase difference Δf and the phase difference signals fu and fd in the conventional phase synchronizer. The horizontal axis indicates the phase difference Δf of the input signal to the phase comparator 13, and the vertical axis indicates the control voltage signal Vc based on the output signals fu and fd from the phase comparator 13. Therefore, the slope of the graph indicates the sensitivity of the phase difference signals fu and fd to the phase difference Δf. Decreasing the time constant of LPF2 is equivalent to tilting the characteristic in the direction of arrow A in the figure (increase the sensitivity), and increasing the time constant is tilting the characteristic in the direction of arrow B (sensitivity). It is understood that the pull-in characteristic of the PLL and the frequency stability contradict each other.

As a method of improving the pull-in characteristic of the PLL, a method of reducing a time constant only at the time of pull-in or increasing a loop gain has been conventionally proposed. However, in these methods, since the phase comparison characteristic has a periodicity,
There has been a problem that an error output of the opposite polarity is temporarily output at the time of pull-in and the pull-in operation is deteriorated.

Another problem is deterioration of phase noise characteristics due to a dead zone. The dead zone is the phase comparator 13
, The phase difference between the reference signal fr and the comparison signal fp becomes a value near zero, and the phase comparator 13 outputs the phase difference signal fu,
This is a range in which fd cannot be generated normally. In FIG. 10, a section C in which the control voltage signal Vc does not change according to the phase difference Δf
Corresponds to a dead zone.

The cause of this dead zone is that the phase comparator 1
3 is the characteristic of an output buffer gate (not shown) as an output stage. Since the output buffer gate has an operation delay time, a rounded waveform, and the like, there is a minimum time width of a pulse that can be output. That is, the reference signal fr and the comparison signal f
When the phase difference of p is near zero, pulses of a predetermined time width (phase difference signals fu and fd not reflecting the phase difference Δf) are output from the output buffer gate. For this reason, the phase comparator 13 cannot output the phase difference information when the phase difference Δf is equal to or smaller than the predetermined value, and a dead zone occurs.

Although the characteristic shown in FIG. 10 has a predetermined sensitivity, the sensitivity sharply changes at the boundary of the dead zone and becomes zero in the dead zone including the zero phase difference. In the synchronizer, the operation near zero phase difference becomes unstable. That is, when the phase difference Δf enters the dead zone C, the phase comparator 13 cannot output the phase difference signals fu and fd based on the phase comparison result between the reference signal fr and the comparison signal fp to the charge pump 14.

In this manner, the phase comparator 13 does not substantially perform its function in the dead zone C, and the output signal frequency of the VCO 3 drifts. As a result, VC
The output signal fv of O3 causes jitter. The jitter refers to the output signal fv of the VCO 3 to which the control voltage signal Vc is not input.
Is a state that is slightly changed in the non-control state. VCO
When 3 causes jitter, it causes deterioration of the phase noise characteristic of the phase synchronizer. The output buffer gate is a phase comparator 1
3 is indispensable to enhance the load driving capability, and it is desired to improve it while maintaining it.

As prior arts of a phase synchronizer for controlling an output pulse from a phase comparator, Japanese Patent Application Laid-Open Nos. 4-63021 (Prior Art 1) and 10-65531 (Prior Art 2) are disclosed. JP-A-8-213901 (Prior Art 3), JP-A-9-261443 (Prior Art 4), JP-A-10-233681 (Prior Art 5), and JP-A-10-336026 (Prior Art) There is technology 6).

In the prior art 1, since the control circuit is controlled by detecting the output inversion of the phase comparator, a delay occurs in the loop itself, the convergence rate is not improved, and the stability at the time of frequency lock is improved. Does not reach. Further, when the phase difference between the VCO and the reference signal is lower than the detection level of the phase comparator at the time of frequency lock, no output signal is output, and a dead zone exists.

In the prior art 2, since the amount of charge / discharge current of the charge pump is increased / decreased by the switching circuit, the phase noise characteristic is deteriorated due to chattering generated at the time of switching. Further, since the method of controlling the pulse width is used, the pulse width cannot be reduced to the minimum unit or less, and the stability at the time of frequency lock cannot be improved.

In the prior art 3, since the amount of charge / discharge current of the charge pump is increased / decreased by the switching circuit, chattering generated at the time of switching is a factor and phase noise is degraded. Further, since noise is removed from the output signal of the phase comparator by inserting a smoothing circuit at the subsequent stage of the phase comparator, it is not possible to improve the dead band jitter when the frequency is locked.

The prior arts 4 and 6 aim at speeding up lock-up at the time of frequency pull-in, and do not cope with phase noise improvement at the time of frequency lock.

In the prior art 5, since the pulse width difference generator and the pulse width detector are used, the circuit scale is large and the configuration is complicated. In addition, since the input value and the optimum value are compared in the pulse width detector, it is necessary to calculate and set a pattern for tracing the optimum value in advance. The burden on the above is large.

[0022]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and uses a dead zone existing in an output signal of a phase comparator to perform high-speed frequency switching in an asynchronous state. It is another object of the present invention to provide a phase synchronization device capable of reducing a spurious amount in a synchronized state. It is another object of the present invention to provide a phase locked loop device in which a dead zone does not substantially occur when the phase difference between the reference signal and the comparison signal is near zero and phase noise characteristics are improved.

[0023]

A phase synchronizer according to the present invention includes a phase comparator for generating a phase difference signal based on a feedback signal and a reference signal, and a phase comparator for generating a phase advanced signal by advancing the phase of the phase difference signal. A phase adder, a phase adder that delays the phase of the phase difference signal to generate a phase delay signal, a combiner that combines the phase advanced signal and the phase delay signal to generate a correction phase difference signal, and a correction An oscillator that is frequency-controlled based on the phase difference signal and generates a feedback signal.

Further, the phase synchronizer according to the present invention further includes a correction amount adjuster for generating a correction amount adjustment signal based on the phase difference information signal from the phase comparator. And the phase delay unit is configured to delay the phase of the phase difference signal by the phase amount based on the correction amount adjustment signal. With such a configuration, the amount of spurs can be further reduced by automatically adjusting the amount of advance phase in the phase advancer and the amount of delay / advancement of the phase advancer, thereby speeding up synchronization at the time of frequency switching. Can be.

In the phase synchronizer according to the present invention, the synthesizer is constituted by an adder or an integrator. Therefore, it can be realized with a simple configuration.

In the phase synchronization apparatus according to the present invention, the phase comparator generates a phase advance of the feedback signal with respect to the reference signal as a first phase difference signal, and generates a phase delay thereof as a second phase difference signal. , The phase advancer is the first,
The phase of the second phase difference signal is advanced to generate first and second phase advanced signals, respectively, and the phase delay unit delays the phases of the first and second phase difference signals to respectively generate the first and second phase advanced signals. A second phase delayed signal is generated, and a combiner combines the first phase advanced signal and the first phase delayed signal to generate a first corrected phase difference signal, and generates a second phase advanced signal and a second phase advanced signal. The two phase delay signals are combined to generate a second corrected phase difference signal, and the oscillator is configured to be frequency-controlled based on the first and second corrected phase difference signals.

In the phase synchronization method according to the present invention, a phase comparing step of generating a phase difference signal based on the feedback signal and the reference signal, and a phase accelerating step of generating a phase advanced signal by advancing the phase of the phase difference signal A phase delaying step of delaying the phase of the phase difference signal to generate a phase delay signal; a combining step of combining the phase advanced signal and the phase delay signal to generate a correction phase difference signal; And an oscillation step of generating a feedback signal based on frequency control.

A phase synchronizing method according to the present invention includes the above-mentioned phase synchronizing device as a frequency synthesizer.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing an example of the configuration of the phase synchronizer according to the present invention. This phase synchronizer comprises PLL1, LPF2 and V
It is configured with CO3. The PLL 1 detects a frequency difference and a phase difference between the VCO output signal fv and a reference signal fr generated inside the PLL, and outputs a control signal fc for reducing these differences to the LPF 2. The LPF 2 outputs a control voltage signal Vc obtained by smoothing the control signal fc and removing high-frequency components. The VCO 3 changes the internal oscillation frequency so as to lock to the reference signal fr based on the control voltage signal Vc, and generates a VCO output signal fv.

The PLL 1 further includes a crystal oscillator 10, a reference frequency divider 11, a comparison frequency divider 12, a phase comparator 13, a charge pump 14, and a pulse width adjuster 4. The crystal oscillator 10 generates an oscillation signal fx of a predetermined frequency, and the reference frequency divider 11 divides the frequency of the oscillation signal fx and outputs a reference signal fr. On the other hand, the comparison frequency divider 12
The output signal fv of CO3 is frequency-divided to generate a comparison signal fp. Then, the phase comparator 13 compares the phases of the reference signal fr and the comparison signal fp, and the comparison result (phase difference Δf)
To generate phase difference signals fu and fd. The pulse width adjuster 4 generates corrected phase difference signals fuu, fdd, and the charge pump 14 generates the corrected phase difference signals fuu, fd.
The control signal fc is output based on d.

FIG. 2 is a block diagram showing one configuration example of the pulse width adjuster 4 shown in FIG. The pulse width adjuster 4 includes a phase advancer (phase advancer) 41 for advancing the phase of an input signal by a predetermined amount φ and outputting the same, and a phase adder for delaying the input signal by a predetermined amount φ and outputting the same. Delay unit (phase delay unit) 42
And adders 43 and 44 for adding these output signals. Note that the phase advancer 41 includes a phase advancer 41U used for the phase difference signal fu and a phase difference signal f
and a phase advancer 41D used for the phase difference signal fu.
And a phase delay unit 42D used for the phase difference signal fd.

The phase difference signal fu (up pulse) input from the phase comparator 13 is converted into a phase advanced signal fu1 and a phase delay signal fu2 in the phase advancer 41U and the phase delayer 42U. These signals are added to an adder 43.
Are combined to generate a corrected phase difference signal fuu, which is output to the charge pump 14. Similarly, the phase difference signal fd (down pulse) input to the pulse width increasing / decreasing device 4 includes a phase advanced signal fd1 and a phase delay signal fd2.
Then, the adder 44 combines these signals to generate a corrected phase difference signal fdd.

The corrected phase difference signals fuu and fdd amplify the phase difference signals fu and fd when the phase difference Δf is large (increase the pulse width), and amplify the phase difference signals when the phase difference Δf is small. The signals are signals in which the signals fu and fd are attenuated (pulse width is reduced), that is, signals in which the phase difference signals fu and fd are emphasized. This operation will be further described with reference to FIGS.

FIG. 3 is a diagram showing the relationship between the phase difference Δf and the phase difference signals fu, fd in this phase synchronizer. The horizontal axis shows the phase difference Δ of the input signal to the phase comparator 13.
The vertical axis represents the control voltage signal Vc when the phase difference signals fu and fd output from the phase comparator 13 are output to the charge pump 14 on the vertical axis. Therefore, the characteristics are the same as those of the conventional phase synchronizer shown in FIG.

FIG. 4 is a diagram showing the relationship between the phase difference Δf and the phase advanced signals fu1 and fd1 output from the phase advancer 41. The horizontal axis indicates the phase difference Δf, and the vertical axis indicates the control voltage signal Vc when the phase advanced signals fu1 and fd1 are output to the charge pump 14. Similarly, FIG. 5 is a diagram showing a relationship between the phase difference Δf and the phase delay signals fu2 and fd2, and FIG. 6 is a diagram showing a relationship between the phase difference Δf and the corrected phase difference signals fuu and fdd. FIG.

Here, the advance phase amount of the phase advancer 41 is the dead zone width C1 in the phase delay region (the negative region of the phase difference Δf) in FIG. 3, and the dead zone in FIG. (Positive region of the phase difference Δf). Further, the amount of delay phase of the phase delay unit 42 is the dead zone width C2 in the phase advanced region in FIG. 3, and the dead zone in FIG. 5 is shifted to the phase delay region.

The corrected phase difference signal fu for the phase difference Δf
The characteristics of u and fdd are obtained by synthesizing FIGS. 4 and 5, and as shown in FIG. 6, a low sensitivity region including a zero phase difference having a moderate sensitivity, and a high sensitivity having a higher sensitivity. A region is formed. That is, when the phase difference Δf is large, the sensitivity is large, and when the phase difference Δf is small, the sensitivity is small. Moreover,
Even when the phase difference Δf is zero or near zero, the inclination is maintained, the sensitivity does not become zero, and there is no dead zone.

When the frequency is switched in this phase synchronizer, the VCO output signal fv is not synchronized with the output signal fx of the crystal oscillator 10, and the reference signal fr and the comparison signal fp are not synchronized.
A state occurs in which the difference between the frequency and the phase is large. This state corresponds to a high-sensitivity region, and the phase difference signals fu and fd are amplified by the pulse width adjuster 4, so that a pulse having a wider width than the conventional one can be output to the charge pump 14. For this reason, the VCO 3 supplies the control voltage signal V
c can be applied, and high-speed synchronization can be performed.

On the other hand, when the frequency of the phase synchronizer is stable, the VCO output signal fv is synchronized with the output signal fx of the crystal oscillator 10, and the reference signal fr and the comparison signal fp are output.
Are small in the frequency and phase differences. This state corresponds to a low-sensitivity region, and the phase difference signals fu and fd are attenuated by the pulse width adjuster 4, and a pulse having a smaller width than the conventional one (a pulse less than the minimum time width of the output buffer gate) is supplied to the charge pump 14. Output. Therefore, VC
Since a control voltage signal Vc smaller than that of the related art can be applied to O3, frequency stability is ensured and the amount of spurious can be reduced.

As a result, the frequency can be rapidly switched in the asynchronous state, and the spurious amount in the synchronous state can be reduced. In addition, even in the conventional dead zone when the frequency is stable, the pulse width adjuster 4 has sensitivity due to the combining action. Therefore, the dead zone can be substantially eliminated, and one factor of the phase noise deterioration in the conventional phase synchronization device can be reduced.

If such a phase synchronizer is used as a frequency synthesizer in a wireless communication device such as a mobile phone,
A communication device capable of high-speed synchronization and having good frequency stability can be provided. Further, a communication device having good phase noise characteristics can be provided.

In this embodiment, the adders 43, 4
4, the phase advanced signals fu1, fd1 and the phase delay signal f
Although the addition with u2 and fd2 is performed, the phase synchronizer according to the present invention is not limited to such an addition operation. For example, instead of the adder, an arithmetic unit or an integrator that performs a non-linear operation or the like may be used.

Embodiment 2 In the present embodiment, a description will be given of a phase synchronizer capable of adjusting a leading phase amount and a lagging phase amount of a pulse width changer. FIG. 7 is a block diagram showing one configuration example of the phase synchronizer according to the present invention. In the figure, 5 is a correction amount adjuster, and fcn is a correction amount adjustment signal.

The correction amount adjuster 5 outputs a correction amount adjustment signal fcn to the pulse width adjuster 4. Pulse width adjuster 4
The phase advancer 41 and the phase advancer 42 change the leading phase amount and the lagging phase amount based on the correction amount adjustment signal. That is, the amount of leading phase and the amount of lagging phase can be adjusted to a more ideal state by using the correction amount adjuster 5. Therefore, excellent high-speed synchronization and low spurious can be realized.

For example, the reference frequency divider 11 and the comparison frequency divider 1
2. The phase comparator 13, the pulse width adjuster 4, and the charge pump 14 can be sealed in one semiconductor package and provided as a so-called PLL-IC. This PLL-IC can realize the PLL 1 of the first embodiment by connecting the crystal oscillator 10.
According to the present embodiment, in such a case, if the correction amount adjuster 5 which is an external device such as a personal computer is connected to the PLL-IC, the advance amount of the phase inside the PLL-IC is calculated by the correction amount adjustment signal fcn. The amount of delay phase can be easily set and changed.

Embodiment 3 In the present embodiment, a phase synchronization device that automatically adjusts the amount of leading phase and the amount of lagging phase and always performs ideal synchronization control will be described. FIG. 8 is a block diagram showing a configuration example of the phase synchronization device according to the present embodiment. In the figure, frp is a phase difference information signal output from the phase comparator 13 to the correction amount adjuster 5.

The phase comparator 13 compares the phase of the reference signal fr with the phase of the comparison signal fp, and outputs a phase difference information signal based on the comparison result. As the phase difference information, for example, phase difference signals fu and fd can be used. The correction amount adjuster 5 generates a correction amount adjustment signal fcn based on the phase difference information signal frp. For example, an adjustment table indicating the correspondence between the phase difference information signal and the correction amount adjustment signal obtained in advance is provided, and the phase difference information signal frp is converted into the correction amount adjustment signal fcn based on the adjustment table.

According to the present embodiment, even during the operation of the phase synchronizer, the correction amount adjustment signal fcn is automatically changed every time on the basis of the phase difference information signal frp. The leading and lagging phase amounts can be set to ideal values. For this reason, always excellent high-speed synchronization and low spurious can be realized.

Embodiment 4 The phase advancers 41U, 4
1D can be configured by an APF (All Band Pass Frequency Filter). The APF is an all band pass type filter, and can change the phase without changing the gain. Therefore, A as phase advancers 41U and 41D
By using the PF, the advance phase amount can be easily adjusted.

Embodiment 5 The phase delay units 42U, 4
2D can be constituted by a buffer circuit. The buffer circuit is a circuit that can keep the level constant without changing the gain, and a constant phase delay occurs when the level is adjusted. Therefore, the phase of the input signal can be delayed.

The buffer circuit can be composed of, for example, one operational amplifier, the delay amount is specific to the operational amplifier, and theoretical calculation and adjustment are easy. Therefore, if a buffer circuit such as an operational amplifier is used as each of the phase delayers 42U and 42D, the circuit configuration is simplified, and the amount of delay is easily adjusted.

In place of the buffer circuit, an even number (particularly, two) of inverter circuits connected in series can be used. In this case, the circuit can be configured with a simpler circuit than the buffer circuit, and the offset adjustment of the operational amplifier becomes unnecessary.

Embodiment 6 FIG. The phase delay units 42U, 4
2D can be configured by a pulse counter.
The pulse counter outputs a phase difference signal f as a pulse signal.
When u and fd are counted and a predetermined count value is reached, a pulse signal of a predetermined width is output, and a large amount of delay can be obtained by functioning as a so-called frequency divider. Therefore, if pulse counters are used as the phase delayers 42U and 42D, a large amount of delayed phase can be obtained with a simple circuit configuration.

Embodiment 7 FIG. The phase delay units 42U, 4
2D can be configured by an LPF (low-pass frequency filter). The LPF is a low-pass filter, and generates a constant phase delay at the same time as a high-frequency gain cut. The LPF can be constituted by RC (resistance and capacitor). Therefore, if the LPF is used, and the phase delay amount is fixed, the phase delay units 42U and 42D can be realized with the simplest circuit configuration.

Embodiment 8 FIG. The phase delay units 42U, 4
The 2D can be configured by an on-state switching circuit including a transistor and the like. If the switching circuit is set to always output, the output level can be kept constant without changing the gain of the input signal. In such a switching circuit, like the buffer circuit, a constant phase delay occurs when the level is adjusted, so that the phase of the input signal can be delayed. Moreover, the phase delay amount in the switching circuit can be adjusted from a small delay amount equivalent to the buffer circuit to a large delay amount equivalent to the pulse counter. Therefore, if a switching circuit is used, it is possible to realize the phase delay units 42U and 42D capable of adjusting the delay phase amount in a wide range.

[0056]

According to the present invention, a corrected phase difference signal can be obtained by synthesizing a phase advanced signal obtained by advancing the phase of a phase difference signal and a delayed phase delay signal. Since the corrected phase difference signal is a signal obtained by amplifying the phase difference signal in the asynchronous state, if the frequency of the oscillator is controlled based on the corrected phase difference signal, high-speed synchronization at the time of frequency switching is possible. Further, since the phase difference signal is attenuated in the synchronized state, the spurious amount can be reduced by controlling the frequency of the oscillator based on the corrected phase difference signal. Furthermore, even in the conventional dead band region when the frequency is stable, the dead band can be substantially eliminated, and phase noise deterioration can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a phase synchronization device according to the present invention (Embodiment 1).

FIG. 2 is a block diagram showing a configuration example of a pulse width changer 4 of FIG.

FIG. 3 is a diagram showing a relationship between a phase difference Δf and phase difference signals fu and fd in the phase synchronizer of FIG. 1, where the vertical axis represents a case where the phase difference signals fu and fd are output to a charge pump; Of the control voltage signal Vc.

FIG. 4 shows a phase difference Δf and phase advanced signals fu1 and fd1.
FIG.

FIG. 5 shows a phase difference Δf and phase advanced signals fu2 and fd2.
FIG.

FIG. 6 shows a phase difference Δf and corrected phase difference signals fuu and fdd.
FIG.

FIG. 7 is a block diagram illustrating a configuration example of a phase synchronization device according to the present invention (Embodiment 2).

FIG. 8 is a block diagram illustrating a configuration example of a phase synchronization device according to the present invention (Embodiment 3).

FIG. 9 is a block diagram showing an example of a conventional phase synchronization device.

FIG. 10 is a diagram showing a relationship between a phase difference Δf and phase difference signals fu and fd in a conventional phase synchronizer, in which a vertical axis indicates a control voltage signal Vc.

[Explanation of symbols]

Reference Signs List 1 PLL, 10 crystal oscillator 11 reference divider, 12 comparison divider 13 phase comparator, 14 charge pump 2 LPF, 3 VCO 4 pulse width increase / decreaser 41, 41U, 41D phase advancer 42, 42U, 42D Phase delayers 43, 44 synthesizer, 5 correction amount adjuster fv VCO output signal, fp comparison signal fr reference signal fu phase difference signal (up pulse) fd phase difference signal (down pulse) fu1, fd1 phase advanced signal, fu
2, fd2 phase delay signal fuu correction phase difference signal (up pulse) fdd correction phase difference signal (down pulse) frp phase difference information signal, fcn correction amount adjustment signal fc control signal, Vc control voltage signal

Claims (6)

[Claims] 1. A phase comparator for generating a phase difference signal based on a feedback signal and a reference signal, a phase adder for advancing the phase of the phase difference signal to generate a phase advanced signal, and A phase delay unit that generates a phase delay signal by delaying it, a synthesizer that generates a corrected phase difference signal by combining the phase advanced signal and the phase delay signal, and generates a feedback signal that is frequency-controlled based on the corrected phase difference signal A phase synchronizer consisting of a oscillating oscillator. 2. The apparatus according to claim 1, further comprising a correction amount adjuster for generating a correction amount adjustment signal based on the phase difference information signal from the phase comparator, wherein the phase advancer adjusts the phase difference by a phase amount based on the correction amount adjustment signal. 2. The phase synchronizer according to claim 1, wherein the phase of the signal is advanced, and the phase delay unit delays the phase of the phase difference signal by a phase amount based on the correction amount adjustment signal. 3. The phase synchronizer according to claim 1, wherein said combiner comprises an adder or an integrator. 4. The phase comparator generates a phase advance of a feedback signal with respect to a reference signal as a first phase difference signal, and generates a phase delay as a second phase difference signal. , Advancing the phases of the first and second phase difference signals to generate first and second phase advanced signals, respectively, wherein the phase delay unit changes the phases of the first and second phase difference signals. The first phase advanced signal and the first phase delayed signal to generate a first corrected phase difference signal. Combining the second phase advanced signal and the second phase delay signal to generate a second corrected phase difference signal, wherein the oscillator is frequency controlled based on the first and second corrected phase difference signals. Item 4. The phase synchronizer according to item 1, 2 or 3. 5. A phase comparing step of generating a phase difference signal based on a feedback signal and a reference signal; a phase advancing step of advancing the phase of the phase difference signal to generate a phase advanced signal; A phase accelerating step for generating a phase delay signal by delaying, a synthesizing step for synthesizing the phase advanced signal and the phase delay signal to generate a corrected phase difference signal, and generating a feedback signal by frequency control based on the corrected phase difference signal A phase synchronization method comprising an oscillating step. 6. A communication device comprising the phase synchronizer according to claim 1 as a frequency synthesizer.