JP2001184231A - Program development supporting device and method of controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a program development supporting device capable of stopping a CPU without using any CPU inside signal. SOLUTION: This program development supporting device uses a CPU 5 constituted of an instruction decoder control part 16 for decoding the instruction of the CPU and a program counter 1 to be controlled by the instruction decoder control part 16. The program development supporting device is provided with an address predictor 27 for preliminarily predicting an address to be outputted by the program counter 1, and for predicting the jump address of the destination of branch before the jump address of the destination of branch is outputted by the program counter 1 and an address comparator 4 for comparing a jump address 21 of the destination of branch predicted and outputted by the address predictor 27 with a preliminarily set stop address 9. The instruction decoder control part 16 outputs an address count signal 23 indicating the change of the address to be outputted by the program counter 1 and jump address signals 24 and 25 of the destination of branch obtained as the result of the decoding of the instruction to the address predictor 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program development support apparatus and a control method therefor, and more particularly to a program development support apparatus for debugging in program development and a control method therefor.

[0002]

2. Description of the Related Art In recent years, the operation of a program development support device has been diversified due to the complexity, increase in scale, increase in real-time performance, diversification of compilers, etc., of a program incorporated in a computer device, and thus the function of a program development support device has been increased. It is becoming functional.

A multifunctional program development support device is a CP
This is realized by adding a circuit necessary for program analysis inside the U. Connecting an additional circuit inside the CPU means that the internal circuit has a wiring capacity and a gate capacity. CPU delay due to signal delay from the controller and the control circuit itself of the program development support device
It has become difficult to further add an additional circuit using the signal of the internal circuit.

A conventional address break function, which is one of the functions of the program development support apparatus, is to transfer an address signal 13 output from a program counter 1 of a CPU 5 through an address bus 3 as shown in FIG. The address is input to the comparator 4 to detect that the address matches the address set in the break address setting unit 11.
Sends the break signal 2 to the CPU 5 to stop the CPU 5.

The program counter 1 outputs the PC address 2 shown in FIG. 9 in the cycle T 3 of the CPU clock shown in FIG. 9, and an address signal 13 is inputted to the address comparator 4 via the address bus 3.

The address comparator 4 supplies the address signal 1 in the T4 cycle after the time “delay of address” in FIG.
3, the comparator address 2 in FIG. 9 is compared with the break address signal 9 set in the break address setting unit 11, and when the addresses match, the break signal 2 is supplied to the instruction decoder in cycle T4. Send to control unit 6.

The instruction decoder control unit 6 supplies a break signal 2
Is input, the instruction decoder control section 6 outputs the CPU stop signal 15 to the program counter 1 in the T5 cycle to stop the program counter 1.

However, since the operation speed required for the program development support device has been improved due to the improvement of the CPU operation speed, necessary signals are extracted from the CPU internal circuit according to the conventional method, and the extracted signals are controlled by an address matching circuit or the like. However, there are cases where the above method cannot be used. Thus, as an example, a case where it is impossible to stop at the address set by the break address setting device will be described with reference to the timing chart of FIG.

The program counter 1 is a CPU of FIG.
In the T3 cycle of the clock, the PC address 2 in FIG. 10 is output. Here, the wiring capacity from the address bus 3 to the address comparator 4, which is the output of the program counter 1, is increased by connecting the program development support device 10, and the wiring capacity between the program counter 1 and the address comparator 4 is increased. 10 "address delay" delays occur,
In the cycle T5 in FIG. 10, the comparator address 2 is determined.

The address comparator 4 compares the comparator address 2 with the break address set in the break address setting unit 11 at the time T5 when the comparator address 2 in FIG. 10 is determined, and at the time T5 cycle, the address comparator 4 When the address signal 13 inputted to the break address setting unit 11 matches the break address signal 9, the break signal 2 is sent to the instruction decoder control unit 6.

The instruction decoder control unit 6 controls the break signal 2
Is input, a CPU stop signal 15 is output to the program counter 1, and the program counter 1 stops.

However, the instruction decoder control unit 6
If the break signal 2 is not received in the T4 cycle when the instruction of the PC address 2 is executed, an address break at the PC address 2 cannot be realized.

As described above, when the time interval of Tn in FIG.
The address delay and the address comparison delay are relatively long, and the break signal 2 can be output only in the T5 cycle. In the T5 cycle, the next instruction cycle (PC address 3) has already been started. It starts and the CPU stops in the T6 cycle. In the target T4 cycle (after execution of the instruction at the address 2), the CPU stops.
Cannot stop PU.

[0014]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the above-mentioned drawbacks of the prior art and, in particular, to provide a new program development supporting apparatus which can stop a CPU without using a signal inside the CPU. And a control method thereof.

[0015]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, the first aspect of the program development support apparatus according to the present invention uses a CPU provided with an instruction decoder control unit for decoding instructions of the CPU and a program counter controlled by the instruction decoder control unit. An address predictor for predicting an address output by the program counter in advance, and predicting a jump address of a branch destination before the program counter outputs a jump address of a branch destination. An address comparator for comparing a jump address of a branch destination predicted and output by the address predictor with a preset stop address is provided, and the instruction decoder control unit indicates that an address output from the program counter has changed. The address count signal and the branch destination result obtained by decoding the instruction And a jump address signal at the branch destination is obtained by converting the jump address signal at the branch destination into an address signal at the interrupt destination. According to a third aspect, the address predictor includes: a first unit for predicting a jump address of a branch destination; and a jump destination of a branch destination predicted by the first unit. When the address is different from the jump address of the branch destination output by the instruction decoder control unit, a second means for correcting the jump address of the branch destination to the jump address of the branch destination output by the instruction decoder control unit is provided. In a fourth aspect, the address predictor stores a predicted address signal indicating a predicted jump address of a branch destination. An address latch that latches a predicted address signal in the predicted address setter at the output timing of the address count signal, and receives a signal latched by the address latch, and a plurality of jump addresses of branch destinations. A branch address table that outputs a frequency, a frequency selector that predicts a jump address of a branch destination from each frequency of the predicted address output by the branch address table, a jump address signal output by the instruction decoder control unit, A branch destination / interrupt destination comparator for comparing a selection signal output from a frequency selector and correcting a prediction difference, and a signal output from the branch destination / interrupt destination comparator, which is output from the branch address table. And a selector for selecting one predicted address from a plurality of branch destination jump addresses to be executed. And the predicted address output from the selector is stored in the predicted address setting device. In a fifth aspect, the branch address table stores the predicted address under a condition close to an environment in which the CPU operates. A simulation is performed, and an address input to the branch address table, a plurality of branch destination jump addresses corresponding to the address, and a frequency of branching to the address are tabulated. In a sixth aspect, when there is no address in the branch address table that matches the address output by the address latch, the address predictor adds “1” to the address output by the address latch. Outputting an address to the predicted address setting device through the selector, In a seventh aspect, the branch destination / interrupt destination comparator is configured to output the frequency when the selection signal output from the frequency selector matches a jump destination signal output from the instruction decoder control unit. A selection signal from a selector is output to the selector, and when they do not match, a jump address of a branch destination output by the instruction decoder control unit is output to the selector.

According to another aspect of the present invention, there is provided a program development support apparatus that includes a CPU having an instruction decoder control unit for decoding an instruction of the CPU, and a program counter controlled by the instruction decoder control unit. An address predictor that predicts an address output by a program counter in advance, and predicts and outputs a jump address of a branch destination before the program counter outputs a jump address of a branch destination. An instruction comparator for comparing the jump address of the branch destination with a preset stop address is provided, and the instruction decoder control unit sends a jump address signal of the branch destination obtained as a result of decoding the instruction to the address predictor. A method for controlling a program development support device configured to output A first step of predicting a jump address of a branch destination by the addressless predictor, and when the jump address of the branch destination predicted by the first means is different from the jump address of the branch destination output by the instruction decoder control unit. And a second step of correcting the jump address of the branch destination to the jump address of the branch destination output by the instruction decoder control unit.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A program development support device according to the present invention is a program development using a CPU having an instruction decoder control unit for decoding instructions of a CPU and a program counter controlled by the instruction decoder control unit. An address predictor for predicting an address output from the program counter in advance, and predicting a jump address of a branch destination before the program counter outputs a jump address of the branch destination; An address comparator for comparing a jump address of a branch destination predicted and output by the unit with a preset stop address, wherein the instruction decoder control unit performs an address count indicating that an address output from the program counter has changed. Signal and the jump destination of the branch destination obtained as a result of decoding the instruction. It is characterized in that it has configured to output to the less signal the address predictor.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a program development support apparatus and a control method according to the present invention will be described below in detail with reference to FIGS.

FIG. 1 is an overall block diagram of a program development support device according to the present invention, FIG. 2 is a block diagram of an address predictor of the present invention, FIG. 3 is a diagram showing an example of a branch address table, and FIG. 6 to 6 are timing charts for explaining the operation. These figures show an instruction decoder control unit 16 for decoding an instruction of the CPU and a program counter 1 controlled by the instruction decoder control unit 16.
A program development support apparatus using a CPU 5 comprising: a CPU that predicts an address output by the program counter 1 in advance, and outputs a jump destination of the branch destination before the program counter 1 outputs a jump address of the branch destination. An address predictor for predicting an address; and an address comparator for comparing a jump address of a branch destination predicted and output by the address predictor with a preset stop address. 16 is
An address count signal 23 indicating that the address output from the program counter 1 has changed, and a jump address signal 2 of a branch destination obtained as a result of decoding the instruction.
4 and 25 are output to the address predictor 27. The program development support device is characterized in that the jump address signal of the branch destination is the address signal 25 of the interrupt destination. Is shown.

The address predicting unit 27 stores a predicted address signal 59 indicating a jump address of a branch destination and a predicted address setting unit 5 which outputs the predicted address signal 59 at the output timing of the address count signal 23.
3; a branch address table 4 for receiving a signal latched by the address latch 40 and outputting a plurality of jump destinations 43 to 45 and their frequencies 46 to 48 in response to the signal latched by the address latch 40;
2, a frequency selector 52 for predicting the jump address of the branch destination from each frequency of the predicted addresses output from the branch address table 42, and the instruction decoder controller 16
Compares the jump address signals 24 and 25 output from the frequency selector 52 with the selection signal 57 output from the frequency selector 52, and corrects a prediction difference. A selector 51 selects one predicted address from a plurality of branch destination jump addresses 43 to 45 output from the branch address table 42 in accordance with a signal 58 output from the comparator 54, and a predicted address output from the selector 51. 59 is the predicted address setting unit 53
And a program development support device characterized by being stored in the branch address table 4.
Numeral 2 performs a simulation under conditions close to the environment in which the CPU operates, an address 42A input to the branch address table 42, a plurality of branch destination jump addresses 42C corresponding to the address 42A, and branch to the address. A program development support device characterized in that a frequency 42D and a frequency are tabulated,
When there is no address in the branch address table 42 that matches the address 41 output from the address latch 40, the address predictor 27 adds “1” to the address 41 output from the address latch 40. A program development support device for outputting an address 49 to the predicted address setting device 53 via the selector 51 is shown. The branch destination / interrupt destination comparator 54
When the selection signal 57 output from the frequency selector 52 and the jump address signals 24 and 25 of the branch destination output by the instruction decoder control unit 16 match, the selection signal 57 from the frequency selector 52 is Output to the selector 51, and when they do not match, the instruction decoder controller 16
And outputs to the selector 51 the jump addresses 24 and 25 of the branch destinations output by the program development support apparatus.

Hereinafter, the present invention will be described in more detail.

FIG. 1 is an overall block diagram of the program development support apparatus. In the figure, 5 is a CPU,
The CPU 5 includes a program counter 1 and an address bus 3
An address count signal 23 indicating that the address has changed while decoding the instruction; a branch signal 24 indicating the address of the branch destination obtained as a result of decoding the instruction; and an interrupt signal indicating the address of the interrupt destination. 25, the data bus 12, and the internal memory 7.
And a built-in referral circuit 8.

As a program development support device, an address predictor that receives the address count signal 23, the branch signal 24, and the interrupt signal 25, predicts the next address, and outputs a predicted address value 21 27 is compared with the predicted address value 21 output from the address predictor 27 and the break address in the break address setting device 11, and when the predicted address value 21 matches the break address, the break signal 2 is controlled by the instruction decoder control. It comprises an address comparator 4 which outputs to the section 16.

When the instruction decoder controller 16 receives the break signal 2, the instruction decoder controller 16 outputs a CPU stop signal 15 to the program counter 1,
The configuration is such that the increment operation of the program counter 1 is stopped.

Next, the configuration of the address predictor of the present invention will be described.

The address predictor 27 of the present invention stores the predicted address value 21 and
Address setting unit 53 which outputs the address to the address comparator 4
An address latch 40 for latching an address in synchronization with a predicted address value 21 output from a predicted address setting unit 53 in synchronization with an address count signal 23;
Outputs address signals 43, 44, 45 indicating a plurality of jump destination addresses corresponding to the addresses, and frequency signals 46, 47, indicating the frequency of occurrence of the jump destination addresses, based on the latched address value 41. 4
8 and a frequency signal 4
6, 47 and 48, a frequency selector for outputting a selection signal 57 for selecting an address signal predicted at the present time, a selection signal 57 and a branch signal 24 or a branch signal 24 output from the instruction decoder control unit 16. A branch destination / interrupt destination comparator 54 that compares the interrupt signal 25 and outputs a selection signal 58, and selects one of the address signals 43 to 45 in response to the selection signal 58, and outputs the selected address signal 59. The address signal 59, which is composed of the selector 51 for outputting and stored in the predicted address setting unit 53, is again configured to be the next predicted address value.

If there is no corresponding address in the branch address table 42, a signal 49 obtained by adding 1 to the address value 41 (predicted address + 1) is output. become.

The branch address table 42 includes an address 42A corresponding to the address value 41, each instruction 42B corresponding to this address, a plurality of jump destination addresses 42C provided corresponding to each instruction 42B, and a jump frequency 42D. And a frequency selector 52,
From the value of a counter (not shown) in the frequency selector 52, an address that will appear next will be selected.

The branch address table 42 is created by simulation using the simulator 70 and the source list 71 having the configuration shown in FIG. The simulation technology is a known technology, and it is a known technology that a jump frequency is obtained by a simulator. However, by performing a simulation under conditions close to the CPU execution environment, the branch frequency and the interrupt frequency can be accurately obtained. As a result, it is possible to prevent a prediction error from occurring.

As described above, in the present invention, the address to be executed next is predicted by the address predictor 27 with reference to the branch address table 42 of FIG.

Next, the operation of the thus configured address predictor will be described.

The instruction decoder controller 16 completes instruction decoding, updates the program counter 1 for the next instruction execution, and outputs an address to the address bus 3. At this time, the address count signal 23
Is output from the instruction decoder control unit 16, and the predicted address value 21 predicted at the time of execution of the previous instruction is latched as the address value 41 in the address latch 40.

At this time, the branch address table 42 shown in FIG.
If there is an identical address in the address column in the middle, jump address 1 to address signal 43, jump address 2 to address signal 44, jump address 3 to address signal 45, and the frequency of address signal 1 The frequency of the address signal 2 is added to the frequency signal 47 to the frequency signal 46.
To output the frequency of the address signal 3 to the frequency signal 48,
In this case, the address value 41 is stored in the branch address table.
If there is no address that matches the address, a signal 49 obtained by adding 1 to the address value 41 (predicted address + 1) is output. The address predictor 27 outputs a (predicted address + 1) signal 49 to the predicted address setter 53 via the selector 51 when the instruction is not a branch instruction. At the time of a branch instruction,
At the present time, the frequency selector 52 selects the most frequent one of the frequency signals 46, 47 and 48, and outputs a selection signal 57 to the branch destination / interrupt destination comparator 54. Frequency selector 5
2 counts the number of jumps of the address shown in the address column of FIG. 3, and determines the selection signal 57 according to the jump frequency of FIG. As an example, jump frequency 1 is 5
0%, jump frequency 2 is 10%, jump frequency 3 is 40
When the frequency selector is%, the operation of the frequency selector outputs the selection signal 57 of the jump address 1 for 5 times, the jump address 2 for 1 time, and the jump address 3 for 4 times.

The branch destination / interrupt destination comparator 54 outputs the branch destination signal 24, the interrupt signal 25, and the selection signal 5 from the frequency selector 52.
7, a selection signal 58 is output to the selector 51.
The selection signal 58 normally selects the address signal 49. When the selection signal 57 is output from the frequency selector 52, one of the address signals 43, 44, and 45 is selected. The selector 51 selects one of the address signals 43, 44, and 45 according to the selection signal 58, and sets the predicted address value 21 in the predicted address setting unit 53. The address predictor 27 outputs the predicted address value 21 that is the value of the predicted address setter 53 to the address comparator 4, and the address comparator 4 compares the predicted address value 21 with the break address signal 9 and finds a match. At times, the break signal 2 is output to the instruction decoder control unit 16. When receiving the break signal 2, the instruction decoder control unit 16
A PU stop signal 15 is output to the program counter 1 to stop the program counter 1.

FIG. 4 is a timing chart showing an operation in a state where a branch signal or an interrupt signal is not included.

In the T1 cycle, the address 1 has already been set in the predicted address setting unit 53. In this state,
The program counter 1 is incremented, the address 1 is output to the address bus 3, and at the same time, the address count signal 23 is output. Address count signal 23
Is the address 1 output from the predicted address setting unit 53.
Is latched by the address latch 40 and output to the branch address table 42 as an address value 41 at the same time.
Then, the branch address table 42 outputs a (prediction address + 1) signal, stores the address in the prediction address setting unit 53 via the selector 51, and outputs the address to the address comparator 4.

FIG. 5 is a timing chart showing an operation when a branch signal or an interrupt signal is output and a break signal 2 is output as a result of the coincidence.

In the T1 cycle, the address 1 has already been set in the predicted address setting unit 53. In this state,
The program counter 1 is incremented, the address 1 is output to the address bus 3, and at the same time, the address count signal 23 is output. Address count signal 23
Is the address 1 output from the predicted address setting unit 53.
Is latched by the address latch 40 and output to the branch address table 42 as an address value 41 at the same time.
Then, the branch address table 42 outputs address signals 43 to 45, which are branch addresses, to the selector 51. At the same time, the branch address table 42 outputs respective frequency signals 46 to 48 to the frequency selector 52.

The frequency selector 52 selects an address that will appear next from the frequency of appearance of each jump address of the instruction at the current time point, and outputs a selection signal 57. Branch destination
The interrupt destination comparator 54 compares the selection signal 57 with the branch signal 24 or the interrupt signal 25.
The interrupt destination comparator 54 outputs a selection signal 58 to the selector. The selector 51 selects one of the address signals 43 to 45 based on the selection signal 58, and selects the selected address 59.
Is stored in the predicted address setting unit 53 and output to the address comparator 4. In this case, since the break address matches the predicted address value 21 output from the address predictor 27, the address comparator 4 outputs the break signal 2 to the instruction decoder control unit 16 in the T3 cycle, and In the cycle, the CPU stop signal 15 is output from the instruction decoder control unit 16 to the program counter 1,
It stops at the address set in the break address setting device 11.

FIG. 6 shows that the break signal 2 does not match at first, but is corrected by using a branch signal or an interrupt signal.
Is a timing chart showing the operation in the case of output.

In the T1 cycle, the address 1 has already been set in the predicted address setting unit 53. In this state,
The program counter 1 is incremented, the address 1 is output to the address bus 3, and at the same time, the address count signal 23 is output. Address count signal 23
Is the address 1 output from the predicted address setting unit 53.
Is latched by the address latch 40 and output to the branch address table 42 as an address value 41 at the same time.
Then, the branch address table 42 outputs a (predicted address + 1) signal 49 to the selector 51, and this signal is
The predicted address value 21 is stored in the predicted address setting unit 53, and is further transmitted from the address predictor 27 to the address comparator 4.
Output as However, at this time, address 2 is different from break address 5 in break address setter 10.

In the present invention, since the branch signal 24 or the interrupt signal 25 is input to the branch destination / interrupt destination comparator 54 during the T3 cycle period, in this case, The interrupt destination comparator 54 corrects the jump address of the branch destination into the branch signal 24 or the interrupt signal 25 and outputs the corrected signal. As a result, the predicted address setting value 53 becomes the address 5, and at the same time, the address 5 is input to the address comparator 4. Then, the break signal 2 which is a coincidence signal is set to T
Output in 4 cycles. Therefore, the program counter 1 stops in the T5 cycle.

In the present invention, the predicted address setting unit 5
3 is configured so that an initial value 53A can be set, so that at the start of debugging, a start address is set as an initial value, and the values of other necessary registers are set to start debugging.

[0045]

The program development support apparatus and the control method thereof according to the present invention are constructed as described above.
There is an excellent effect that the wiring delay caused by drawing out the internal address bus to the outside can be eliminated, and the CPU can be stopped at the target break address even at the time of the high-speed CPU clock.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a program development support device according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of an address predictor.

FIG. 3 is a table showing an example of a branch address table.

FIG. 4 is a timing chart showing an operation when a break address is not set.

FIG. 5 is a timing chart showing an operation when a break address is set and a program counter stops.

FIG. 6 is a timing chart showing another operation when a break address is set and the program counter stops.

FIG. 7 is a diagram showing a procedure for creating a branch address table.

FIG. 8 is a block diagram of a conventional program development support device.

FIG. 9 is a timing chart showing the operation of a conventional program development support device.

FIG. 10 is a timing chart showing a problem of a conventional program development support device.

[Explanation of symbols]

 Reference Signs List 1 PC (program counter) 2 Break signal 3 Address bus 4 Address comparator 5 CPU 6 Instruction decoder control unit 7 Built-in memory 8 Built-in peripheral 9 Break address signal 10 Program development support device 11 Break address setting device 12 Data bus 13 PC output Address signal 14 to be input to the address comparator 4 15 address signal to be input to the address comparator 4 15 CPU stop signal 16 instruction decoder control unit 21 predicted address value 23 address count signal 24 branch signal 25 interrupt signal 27 address predictor 40 address latch 41 address value 42 branch address Table 43 Address signal (jump address 1) 44 Address signal (jump address 2) 45 Address signal (jump address 3) 46 Frequency signal (jump frequency 1) 47 Frequency signal ( Jump Frequency 2) 48 frequency signal (jump frequency 3) 49 (predicted address +1) signal 51 selector 52 frequency selector 53 predicted address setter 54 branch target-interrupt destination comparator 57 selects signal 58 select signal

Claims (8)

[Claims] 1. A program development support device using a CPU comprising an instruction decoder control unit for decoding instructions of a CPU and a program counter controlled by the instruction decoder control unit, wherein the program counter outputs An address predictor that predicts an address in advance and predicts a branch destination jump address before the program counter outputs a branch destination jump address; and a branch destination jump address predicted and output by the address predictor. And an address comparator for comparing with a preset stop address. The instruction decoder control section includes an address count signal indicating that an address output from the program counter has changed, and a branch obtained as a result of decoding the instruction. Output the previous jump address signal to the address predictor. Program development support apparatus characterized by being configured so. 2. The jump address signal of the branch destination is:
2. The method according to claim 1, further comprising an interrupt destination address signal.
The described program development support device. 3. An address predictor comprising: a first means for predicting a jump address of a branch destination; and a jump address of the branch destination predicted by the first means, wherein the jump address is a branch address output by the instruction decoder control unit. 2. The apparatus according to claim 1, further comprising a second means for correcting the jump address of the branch destination to a jump address of the branch destination output from the instruction decoder control unit when the jump address differs from the jump address. 2. The program development support device according to 2. 4. An address predictor, comprising: a predictive address setter for storing a predictive address signal indicating a jump address of a branch destination; and a predictive address signal in the predictive address setter at an output timing of the address count signal. An address latch to be latched, a branch address table receiving a signal latched by the address latch, and outputting a jump address of a plurality of branch destinations and the frequency thereof, and branching from each frequency of the predicted address output by the branch address table. A frequency selector for predicting a previous jump address, a branch destination / interrupt for comparing a jump address signal output from the instruction decoder control unit with a selection signal output from the frequency selector, and correcting a prediction difference. A comparator and a signal output from the branch destination / interrupt destination comparator. And a selector for selecting one predicted address from a plurality of branch destination jump addresses output from the selector, and storing the predicted address output from the selector in the predicted address setting device. Or the program development support device according to 2. 5. The branch address table according to claim 1, wherein
A simulation is performed under conditions close to the environment in which U operates, and a table is formed of addresses input to the branch address table, a plurality of branch destination jump addresses corresponding to the addresses, and the frequency of branching to the addresses. The program development support device according to any one of claims 1 to 4, wherein: 6. When there is no address in the branch address table that matches the address output by the address latch, the address predictor adds the address obtained by adding “1” to the address output by the address latch. The program development support device according to claim 1, wherein an output is provided to the predicted address setting device via a selector. 7. The branch destination / interrupt destination comparator, when a selection signal output from the frequency selector matches a branch destination jump address signal output by the instruction decoder control unit, the frequency selection. 7. A selector according to claim 1, further comprising: outputting a selection signal from a selector to the selector; and outputting a jump address of a branch destination output by the instruction decoder control unit to the selector when they do not match. A program development support device according to any of the above. 8. A CPU comprising an instruction decoder control unit for decoding an instruction of the CPU, and a program counter controlled by the instruction decoder control unit; Before outputting the jump address of the branch destination, an address predictor for predicting the jump address of the branch destination, and an address for comparing the jump address of the branch destination predicted and output by the address predictor with a preset stop address A comparator, wherein the instruction decoder control unit is configured to output a jump address signal of a branch destination obtained as a result of decoding the instruction to the address predictor, the control method of the program development support device. A first step of predicting a jump address of a branch destination by the address predictor; When the jump address of the branch destination predicted by the first means is different from the jump address of the branch destination output by the instruction decoder control unit, the branch address of the branch destination output by the instruction decoder control unit is output. And a second step of correcting the jump address to a previous jump address.