JP2001177390A - Driver circuit device - Google Patents

Abstract

(57) [Problem] In the conventional example, the output voltage at the "H" and "L" levels is usually about 2 volts and 0.8 volts, and the output current is several milliamps. Since the conductance of the output nMOS is set to a large value, a large output current flows due to the load capacitance when the transistor is turned on, the peripheral voltage fluctuates and noise occurs, and the signal is disturbed. . SOLUTION: From the "H" level of an input signal 10.IN
An input transition detection circuit 6 for detecting a change in state from L level or from L level to H level and generating a one-shot pulse, and a first driver circuit having a large conductance connected to a capacitor load 15 5, a second additional driver circuit 5a of small conductance, a first logic gate (73, 74, 75) for guiding 10 to 5 at 6 and a second logic gate for guiding the input signal to 5a at 6 A driver circuit device comprising an additional driver gate drive circuit at the time of input transition comprising (71, 72, 76).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit device capable of suppressing fluctuations in power supply voltage to peripheral circuits due to a large output current when driving a large load at high speed.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional driver circuit device [this is referred to as a "conventional example"]. Fig. 3 (a)
3 is a block diagram showing a circuit configuration of a conventional example, and FIGS.
(d) is a tie chart of the voltage waveform accompanying the operation.
In all the drawings, the same reference numerals indicate the same or corresponding members. First, in FIG. 3A, the input signal 10 · IN
Is at the "H" level, the signal "L" level is held at the node [node] 13.IN1 (the output stage of the NAND 11) via the drive gate selection circuit 1, and conversely, the node 14 / IN2 (the NAND 12) The output stage), the signal “H” level is held, and the nMOS [n-channel Metal Oxide Semiconductor is composed of FET and Field-Effected Transistor] 2.
N1 is off, nMOS3 and N2 are on, and an “L” level is output as the output signal OUT [FIG.
(b) See]. In this state, the input signal 10 • IN becomes “L”.
When the level transitions to the level, the level of each signal transitions to the opposite level.
3 is turned off, and "H" level is output to the output OUT. Then, the input signal 10 · IN
Transitions to the "H" level, the transition to each level is again made to the initial state. As a result, nMOS2 is off and nMOS
3 is turned on, an “L” level is output to the output OUT, and the load [not shown] is driven by repeating such a state.

[0003]

However, in the driver circuit device having such a configuration of the prior art, the "H" level output voltage VOH is usually about 2 volts, and the "L" level output voltage VOL is usually about 0.1 volt. The output current IOH at the "H" level and the IOL of the output current at the "L" level are usually set to several milliamps.
The conductance of OS · 2 and nMOS · 3 is set to a very large value. Therefore, nMOS · 2
Alternatively, when the nMOS 3 is turned on, a large output current IOH or IOL flows due to the load capacitance connected to the output OUT. As a result, the power supply voltage which is the peripheral voltage of the nMOS 2 or nMOS 3. VDD and the ground voltage GND [the voltage drop caused by the internal resistance 21 of the nMOS and the ground voltage rise caused by the internal resistance 31] fluctuate.

FIGS. 3 (c) and 3 (d) show fluctuation voltage waveforms of the power supply voltage VDD and the ground voltage GND in such a state. This phenomenon is due to the fact that the output cycle is shortened as the access speed is increased, and the amplitude voltage is increased,
It may even cause a malfunction in the peripheral circuit. Further, there is a problem that this noise affects the level of the output voltage VOH at the "H" level and the level of the output voltage VOL at the "L" level, which hinders an increase in speed. Here, an object of the present invention is to divide the output into two systems, a driver having a large conductance and a driver having a small conductance, and alternately drive these drivers only in a predetermined section [time], thereby achieving high-speed operation. Suppress the fluctuation of the power supply potential connected to the driver without impairing the operation. An object of the present invention is to provide a driver circuit device capable of expecting stable operation.

[0005]

According to a first aspect of the present invention, there is provided a driver circuit device according to the first aspect of the present invention, wherein the logic of an input signal is changed from "H" level to "L" level or "L" level. An input transition detection circuit that detects a change in state from L level to “H” level and generates a one-shot pulse, a first driver circuit having a large conductance, and a second additional driver circuit having a small conductance A first logic gate that guides an input signal to a first driver circuit in the input transition detection circuit, and a second logic gate that guides the input signal to a second additional driver circuit in the input transition detection circuit. And an additional driver gate drive circuit at the time of an input transition. Thus, according to the invention of claim 1 of the present invention,
It is possible to obtain a special effect that stable operation can be expected without deteriorating high-speed operation, suppressing fluctuations in the power supply potential and the ground potential connected to the driver.

According to a second aspect of the present invention, in the driver circuit device according to the first aspect, the input transition detection circuit separates one input signal into two systems and inputs them through a time difference route. A first NOR circuit, a second NOR circuit separated into the two systems inverted by a first inverter before the separation, and input via a time difference route; a first NOR circuit; and a second NOR circuit. And a NOR circuit that receives an output from the NOR circuit and inputs the logical sum of the outputs. Thus, according to the invention of claim 2 of the present invention, the transition of the logic of the input can be detected in a short time,
A remarkable effect that noise propagation to peripheral devices can be prevented, malfunction of the signal circuit is prevented beforehand, and operation reliability is improved is recognized.

According to a third aspect of the present invention, in the driver circuit device according to the first or second aspect,
The input transition additional driver gate drive circuit includes a drive gate selection circuit for selecting a driver gate to be driven according to the logic of an input signal in an output stage of a second inverter provided in an output stage of the input transition detection circuit. Two third NOR circuits that respectively OR the two outputs of the circuit, and the respective OR of the two outputs of the drive gate selection circuit and the output of the third inverter provided in the output stage of the second inverter And a fourth NOR circuit, wherein an output stage of the third NOR circuit is connected to a gate of the first driver circuit, and an output stage of the fourth NOR circuit is connected to the second additional driver circuit. , And is connected to the gate.
Therefore, during the input transition, a driver having a large conductance is applied within a predetermined time, and after securing a sufficient VOH · VOL potential, an additional driver having a small conductance is applied. Therefore, the present invention can be said to be extremely suitable for reducing harmonic noise and the like based on disturbance of a current waveform due to a change in load current.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a circuit according to an embodiment of the present invention. FIG.
(a) to (f) are time charts showing waveform changes of each signal voltage, power supply voltage, ground voltage and the like representing the operation in FIG. In FIG. 1, nMOS · 8 · N3 and nMOS · 9 · N4 are nMOS having a small conductance band as compared with nMOS · 2 · N1 and nMOS · 3 · N2. First, the input signal 10 · I
When the "H" level is input to N, the node 77 of the inverter 75 for introducing the output of the input transition detection circuit 6 described later.
T1 is at “H” level, and the next inverter node 78
2 is in the state of “L” level, the node 79a of the output stage of the NOR 73 and the signal of IN3 and the node 79b of the output stage of the NOR 74.
The signal of IN4 is both at "L" level, and both nMOS.2 and nMOS.3, which have a large conductance band, are off.

The nMOS · 8 and nMOS · 9 having a small conductance band are provided with an input signal 10 · IN.
, The nMOS · 8 is at the “H” level, and the nMOS · 9 is at the “L” level. Therefore, the nMOS.8 is on and the nMOS.9 is off, and a "H" level voltage signal is output to the output 100.OUT. Next, consider the case where the logic of the input signal 10 has transitioned to the "L" level in this state.
Here, the present invention relates to the transition of the logic level of the input signal 10.IN.
Input transition detection circuit 6 as means for detecting [Transition]
Is provided. Therefore, only when the input signal 10.IN transitions from the “H” level to the “L” level and conversely, when the transition from the “L” level to the “H” level, the node 77 outputs “ A circuit for outputting an “H” level from the L level to the node 78 is shown.

That is, since the transition of the logic data of the input signal 10.IN is detected and the node 77 outputs the "L" level and the node 78 outputs the "H" level, the node 79c.IN
The logic signal at node 5 and the logic signal at node IN6 are "L".
N, which is a level and has a small conductance band
MOS 8 and nMOS 9 are turned off. At this time, the input logic data is passed through to the output logic of the nodes 13 and 14, the “H” level is applied to the node 13, and the “H” level is applied to the node 14.
The L "level is passed through, the nMOS 2 having a large conductance band is turned off, and the nMOS 3 having a large conductance band is turned on. As a result, the" L "level is output to the output 100 OUT.

In this case, as shown in FIG.
At a predetermined time when the “L” level reaches the “L” level output “L” level voltage / VOL, the “H” level is applied to the logic signal of the node 77 · T1 and the “H” level is applied to the logic signal of the node 78 / T2. If the circuit constant of the input transition detection circuit 6 is set so that the L level appears, the nMOS 2 and nMOS 2 having a large conductance band are obtained at the time when the output 100 OUT reaches the “L” level voltage VOL. 3 is turned off, and nMOS · 8 having a small conductance band
And the nMOS 9 pass through the logic data of the input signal 10.IN, and as a result, the nMOS 9 is turned on and the output 10
0-Holds "L" level of OUT.

Further, in this state, the input signal 10.IN
Changes to the “H” level. The transition of the logical data is detected by the input transition detection circuit 6, and the node 77
Output the "L" level and the node 78 output the "H" level, so that the nodes 79c and 79d are at the "L" level and have a small conductance band.
And the nMOS 9 turns off. At this time, the logical data of the input signal 10 · IN is passed through the outputs of the nodes 13 and 14, the “L” level is applied to the node 13, and the “
The "H" level is output, the nMOS.2 having a large conductance band is turned on, and the nMOS.3 is turned off. As a result, the "H" level is output to the output 100.OUT.

At this time, the logical data “H” level is “H”.
At a predetermined time to reach the level voltage VOH, the node 77
Since the circuit constant of the input transition detection circuit 6 is set so that the "H" level appears at the node 78 and the "L" level appears at the node 78, the output 100.OUT reaches the "H" level voltage VOH when the output 100. With a large conductance band
The MOS 2 and nMOS 3 are off, the nMOS 8 and nMOS 9 having a small conductance band allow the input signal 10 IN to pass through, and as a result, the nMOS 8 is turned on and the output 100 OUT becomes “H”. "Level will be maintained. In this way, according to the present invention, the nMOS.8 and nMOS.9 having a small conductance can be applied for a while at the transition of the logic data of the input signal 10.IN by the circuit constant of the input transition detection circuit 6, The effect of suppressing a change in the output voltage waveform can be exhibited.

[0014]

As described above in detail, according to the present invention, the time until the output reaches the "H" level voltage VOH and the "L" level voltage VOL is not delayed, that is, the access is impaired. This provides a special effect that a driver circuit device that can suppress a fluctuation in the power supply potential caused by a large output current [sink current] without any problem can be realized. That is, according to the first aspect of the present invention, it is possible to obtain an excellent effect that stable operation can be expected without deteriorating high-speed operation, suppressing fluctuations in the power supply potential and the ground potential connected to the driver, and Claim 2
According to the invention, a remarkable effect that the transition of the logic of the input can be detected in a short time, the influence of noise on the peripheral device can be prevented, the malfunction of the signal circuit is prevented beforehand, and the reliability of the operation is improved. In addition, a driver having a large conductance is applied within a predetermined time at the time of input transition, and after securing a sufficient VOH · VOL potential, an additional driver having a small conductance is applied. Since the load current to be generated is also relatively small, the present invention can be said to be extremely suitable for reducing harmonic noise and the like based on disturbance of the current waveform due to a change in load current.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration in a driver circuit device according to an embodiment of the present invention.

FIG. 2 is a time chart showing an operation waveform of each part in the driver circuit device of FIG. 1 showing an embodiment of the present invention;

3A and 3B are explanatory diagrams of a conventional technique, in which FIG. 3A is a block diagram showing a circuit configuration thereof, and FIG. 3B is a time chart showing operation waveforms at various parts in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Drive gate selection circuit 2, 3 nMOS (The reciprocal of conductance and resistance is large) 4 DC power supply (VDD) 5 Driver circuit 5a Additional driver circuit 6 Input transition detection circuit 7 Additional driver gate drive circuit at the time of input transition 8, 9 nMOS (Small conductance) 10 Input signal (IN) 11,12 Nand 13,14 Node (IN1, IN2) 15 Capacitor load (CL) 21,31 nMOS internal resistance 21a, 31a Inner terminal of nMOS internal resistance 61,62, 63,65,66,67,68,75,76,80 Inverter 60,64,69,71,72,73,74 Noah 77,78 Node (T1, T2) 79a, 79b, 79c, 79d Node (IN3, IN4, IN5
IN6) 100 output (OUT) 101 output "H" level current (IOH) 102 output "L" level current (IOL)

Continued on the front page F-term (Reference) 5J055 AX25 AX55 AX56 AX64 BX16 CX24 DX22 DX57 DX72 DX83 EX07 EX21 EY01 EY10 EY21 EZ00 EZ07 EZ25 FX12 FX17 FX35 GX00 GX01 GX04 5J056 AA05 BB02 BB25 CC00 DD13DD

Claims (3)

[Claims] In a driver circuit for driving a large load on an electronic circuit, a change in state of the logic of an input signal from "H" level to "L" level or from "L" level to "H" level is detected. An input transition detection circuit for generating a one-shot pulse, a first driver circuit having a large conductance, a second additional driver circuit having a small conductance, and a first driver for inputting an input signal by the input transition detection circuit. An input transition additional driver gate drive circuit comprising: a first logic gate leading to a circuit; and a second logic gate leading an input signal to a second additional driver circuit in the input transition detection circuit. Characteristic driver circuit device. 2. The driver circuit device according to claim 1, wherein the input transition detection circuit includes: a first NOR circuit that separates one input signal into two systems and inputs the signals through a time difference route; A second NOR circuit which has been separated into the two systems previously inverted by the first inverter and input through a time difference route, and outputs of the first NOR circuit and the second NOR circuit which are input and both 2. The driver circuit device according to claim 1, further comprising a NOR circuit that outputs the logical sum of 3. The driver circuit device according to claim 1, wherein the additional driver gate drive circuit at the time of input transition is connected to an output stage of a second inverter provided at an output stage of the input transition detection circuit. , Two third NOR circuits for performing a logical OR operation with two outputs of a drive gate selection circuit for selecting a gate of a driver to be driven according to the logic of an input signal, and two outputs of the drive gate selection circuit and the second output. And two fourth NOR circuits each performing an OR operation with an output of a third inverter provided at an output stage of the second inverter. The output stage of the third NOR circuit has a gate of the first driver circuit. And the output stage of the fourth NOR circuit is connected to the second stage.
3. The driver circuit device according to claim 1, wherein said driver circuit device is connected to a gate of said additional driver circuit.