JP2001177388A - Drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a P-channel MOSFET on the high potential side of an output stage
An object of the present invention is to enable a high-speed operation and reduce the current consumption in a driver circuit using the same. SOLUTION: A P-channel FET (M1) having a source connected to a high potential side (VDD) of a first power supply system and a drain connected to an output terminal, and a second P-channel FET (M1) lower than the first power supply system.
And an output control circuit (IN1) that operates with the power supply voltage (Va) of the power supply system, and controls the gate of the P-channel FET (M1) based on the output voltage of the output control circuit (IN1). In (1), the output terminal of the output control circuit (IN1) and the P-channel FET (M
A capacitor (C1) is connected between the capacitor (C1) and the gate terminal of the P-channel FET (M).
An initial setting switch (S) for connecting or disconnecting the connection point with the gate terminal of 1) and the power supply voltage terminal of the first power supply system.
W).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit formed as a MOS integrated circuit and a P-channel FE as a push-side transistor disposed on the high potential side of a power supply voltage.
Regarding a technique useful when applied to a drive circuit having T,
For example, this technique is particularly useful when used in an output circuit of a synchronous rectification control IC that controls the current of a motor.

[0002]

2. Description of the Related Art Conventionally, as a push-pull type output circuit used in an output stage of a drive circuit such as a synchronous rectification control IC or the like, an N-channel MOS is used for a push-side transistor.
There are those using SFETs and those using P-channel MOSFETs. When an N-channel MOSFET is used for the transistor on the push side, when the output voltage increases, the gate-source voltage of the transistor decreases and the transistor does not turn on sufficiently.
Only an output voltage lower than the threshold voltage of the OS can be obtained. Therefore, in order to turn on the transistor sufficiently and obtain an output up to the high potential point, it is necessary to apply a voltage higher than the high potential point of the power supply voltage to the gate of the N-channel MOSFET on the high potential side.

On the other hand, when a P-channel MOSFET is used as a high-potential transistor in a push-pull type output circuit, a voltage lower than the power supply voltage by at least the threshold voltage of the MOSFET is applied to the gate of the P-channel MOSFET.
ET can be easily and sufficiently turned on.

FIG. 10 is a circuit diagram showing an example of a driver circuit using a P-channel MOSFET on the high potential side of the output stage.

When the P-channel MOSFET M1 is arranged on the high potential side of the push-pull output stage, the power supply potential VDD is applied to the gate when the P-channel MOSFET is off, and the power supply potential VDD is lower than the power supply potential VDD by at least the threshold voltage of the MOSFET M1 when off. A voltage needs to be applied to the gate.

The gate of the MOSFET M1 is connected to the power supply potential V
In order to make the voltage lower than DD, a MOSFET M15 is provided between the gate of the MOSFET M1 and the ground.
The gate may be connected to the ground by the switching operation of the OSFET M15. However, when the power supply voltage VDD is MO
In the case of a high-voltage system (for example, 12 V) higher than the (gate) breakdown voltage of the SFET M1, considering the gate-source breakdown voltage of the P-channel MOSFET, the gate voltage at the time of ON cannot be reduced to the ground potential. The gate voltage must be clamped, for example, by providing a diode DZ10 to prevent the gate potential of the MOSFET M1 from excessively lowering.

Further, the P-channel MOSFET M1
In order to turn off the MOSFET at high speed and operate the driver circuit at high speed, the parasitic capacitance of the MOSFET M1 must be charged at high speed. Therefore, the power supply potential VDD and the MOS
It is conceivable to provide a depletion-type MOSFET M14 acting as a resistor between the gate of the FET M1.

[0008]

However, in the driver circuit having the above configuration, the MOSFET
When M1 is turned on, a DC current IM15 (= IDZ10 + IM14) flows from the power supply potential VDD to the ground side, which causes a problem that current consumption becomes excessive.

An object of the present invention is to provide P
An object of the present invention is to enable high-speed operation and reduce current consumption in a driver circuit using a channel MOSFET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, an output stage composed of a push-pull circuit connected to the power supply voltage of the first power supply system is provided, and a P-channel FET is used as a transistor on the high potential side of the output stage. In a drive circuit which is operated by a power supply voltage of a two-power supply system and has an output control circuit for driving a gate of the P-channel FET, a capacitor is connected between an output terminal of the output control circuit and a gate terminal of the FET. In addition, the output amplitude of the output control circuit is set lower than the gate-source breakdown voltage of the FET, and a connection point between the capacitor and the gate terminal of the FET and a power supply voltage terminal of the first power supply system. Is provided with an initial setting switch means for connecting or disconnecting the switch.

According to such a means, the gate potential of the FET can be set to the high potential point of the first power supply system and the potential point lower than the low potential output control circuit of the low power supply system through the capacitor even through the capacitor. You can shake between. Further, since a DC path is not included in a portion for generating a gate potential, current consumption is small. Further, by setting the output amplitude of the output control circuit, the gate-source voltage of the FET can be suppressed to a withstand voltage or less.

Further, by appropriately adjusting the capacitor capacity and the output amplitude of the output control circuit so that the peak value of the current flowing into or out of the gate of the FET becomes large, the FET having the characteristic of the capacitive load can be obtained. Can be operated at high speed.

The problem here is the initial charge amount of the capacitor. If the charge amount varies, the capacitor may not operate normally. However, according to the above means, the amount of charge of the capacitor can be initially set by the switch means, so that the operation can always be started in a normal state.

As the switch means, for example, a switch element such as a MOSFET which is opened and closed by a power-on reset pulse generated when the power of the system is turned on can be used. In addition, as the switch means, a Zener diode connected in reverse direction from the high potential side of the first power supply system to the gate of the FET is used. The output amplitude of the output control circuit is Va, and the Zener voltage of the Zener diode is Vf. In such a case, the configuration may be such that Va> Vf. In the case of such a configuration, the Zener diode can be Zener broken down by the high-level output of the output control circuit, and the charge amount of the capacitor can be initialized.

More preferably, there is provided a booster circuit for raising the source potential of the FET to a voltage higher than the potential on the high potential side of the first power supply system, and a high level of the gate voltage of the FET performed by the output control circuit is provided. And the control of the low level and the control of the step-up and step-down of the source voltage of the FET performed by the step-up circuit are performed in synchronism in opposite phases.

According to such means, when the FET is turned on, the gate potential is lowered and the source potential is raised at the same time, so that the FET can be turned on faster.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

[First Embodiment] FIG. 1 is a circuit diagram showing the simplest embodiment of a driver circuit to which the present invention is applied.

The driver circuit 1 of this embodiment is an integrated circuit for driving a motor formed on one semiconductor chip such as single crystal silicon, for example, and generates a timing pulse Φ having a small amplitude of 0 V to 6 V, for example. Upon receiving the output voltage, a large amplitude output voltage Vout of 0 V to VDD (for example, 12 V) is output.
The output voltage Vout is applied to the gate of the load MOSFET M10, and the drive current of the motor is supplied by the load MOSFET M10.

In FIG. 1, M1 and M2 are output MOSFETs forming a push-pull type output stage. The output MOSFET M2 disposed on the ground side is an N-channel, and the output MOSFET M1 disposed on the high potential side is a P-channel.
Channel. This output stage is supplied with a large power supply voltage VDD (for example, 12 V) of the drive system.

IN1 is an inverter circuit for controlling the output, which outputs a high level (power supply potential Va) and a low level (ground potential) in response to the timing pulse Φ. The inverter IN1 has a drive system power supply voltage V
A power supply voltage Va (for example, 6 V) of a control system lower than DD is supplied. This power supply voltage Va is a high potential side output MOS.
It is set so as not to exceed the gate-source breakdown voltage of the FET M1.

C1 is a high-potential side output MOSFET M1
This is a capacitor for controlling the gate voltage of the inverter circuit IN1 and is provided between the output terminal of the inverter circuit IN1 and the gate terminal of the output MOSFET M1.

SW is a switch for initializing the charge amount of the capacitor C1, and when ON, connects the electrode of the capacitor C1 on the output MOSFET M1 side to the power supply voltage VDD. The switch SW is connected to a power-on reset pulse RS generated based on power-on, for example, when the power of the system in which the driver circuit 1 is incorporated is turned on.
And then turned off during normal operation.

FIG. 2 is a timing chart for explaining the operation of the driver circuit 1.

This timing chart shows the state of the system in which the driver circuit 1 is incorporated since power-on. In the figure, M1, M2, M1
0 and SW are MOSFETs M1, M2 and M10, respectively.
And the state of the switch SW, VG is the gate potential of the output MOSFET M1 to which the capacitor C1 is connected, and Φ and / Φ are the internal signal input to the inverter IN1 and the inverter I
This is the output of N1.

As shown in FIG. 2, when the power is turned on (shown as "initial" in FIG. 2), a high-level reset pulse is input to the driver circuit 1, whereby the switch SW is turned on for a short time. During this time, the capacitor C1 is charged, and the potential VG of the connection node n1 is pushed up to the power supply voltage VDD. The switch SW is turned on only when a reset pulse is applied, and then turned off during normal operation.

The timing pulse Φ starts with a low-level input when the power is turned on. The input of “H” (high) and “L” (low) is repeated at a predetermined cycle. Accordingly, the potential at the lower end of the capacitor C1 and the output MO on the ground side
Since the gate potential of the SFET M2 is the same as the output potential of the inverter IN1, it starts at a high level (power supply voltage Va of the control system) when the power is turned on, and thereafter repeats a low level and a high level at a predetermined cycle.

The gate potential VG of the output MOSFET M1 on the high potential side is determined by the inverter I when the gate capacitance of the MOSFET is sufficiently smaller than the capacitance of the capacitor C1.
In accordance with the output voltage / Φ of N1, the potential changes to a high level (VDD) and a low level (VDD-Va) in synchronization with the output. Thereby, the output MOSFET M1 on the high potential side
Repeatedly turns off and on in synchronization with the timing pulse Φ.

The capacitance (C1) of the capacitor C1 is equal to the output MO.
If the gate capacitance is not sufficiently large with respect to the gate capacitance of the SFET M1, the gate potential VG at the high level is not different from the power supply potential VDD as described above, but when it is at the low level, it is different from the above case. . That is, when the output / Φ of the inverter IN1 changes from the high level to the low level, electric charge flows from the gate of the output MOSFET M1 to the capacitor C1, so that the potential difference Va is equal to the gate capacitance (Cin) of the output MOSFET M1.
And the low-level potential becomes VDD− ｛1-Cin / (Cin + C
1) It becomes と Va. The gate capacitance (Cin) at this low-level gate potential is determined by the output MOSFET
This is the gate capacitance increased by turning on M1.

Therefore, the capacity of the capacitor C1 is determined by the output M
Considering the gate capacitance of the OSFET M1 and the potential difference between the inverter output / Φ, the output MOSFET M1 is determined to be sufficiently turned on when the gate potential VG is at a low level. For example, when the gate capacitance of the MOSFET M1 is 0.06 pF, if the capacitor C1 having a capacitance of about 1 pF is used, the output MOSFET M1 can be turned on sufficiently and at high speed.

The ground-side output MOSFET M2 repeatedly turns on and off in synchronization with the output / Φ of the inverter IN1, that is, in synchronization with the timing pulse Φ in the opposite phase.
Therefore, two output MOSFs performing a push-pull operation
The voltage Vo at the output node that is the node between ET M1 and M2
ut repeats a high level (power supply potential VDD) and a low level (ground potential) in synchronization with the timing pulse Φ, whereby the load MOSFET M10 is turned on and off.

As described above, according to the driver circuit 1 of this embodiment, the push-pull output stage to which the power supply voltage VDD of the drive system is supplied by the inverter output / Φ swinging within the range of the power supply voltage Va of the control system. The P-channel MOSFET M1 arranged on the high potential side can be driven without consuming current. That is, in the conventional circuit of FIG. 10, there is a through current flowing from the MOSFET M14 to the MOSFET M15, but in the circuit of FIG. 1, since there is no such a through current, the MOSFET M1 can be driven with low current consumption. The output amplitude Va of the inverter IN1 is provided between the gate and the source of the output MOSFET M1.
Since the above voltage is not applied, the output MOSFET M
Operation control at a breakdown voltage of 1 or less is possible, and a zener diode is not required.

Further, the output MOS during operation is adjusted by adjusting the output amplitude Va of the inverter IN1 and the capacitance of the capacitor C1.
Since the amplitude of the voltage applied to the gate of the FET M1 can be appropriately adjusted, the value of the peak current flowing from the gate to the capacitor C1 at the time of turning on the output MOSFET M1 is set to be large, and the output MOSFET is set.
The ON operation of TM1 can be performed at high speed.

The capacitor C1 is switched by the switch SW.
Is normally initialized at the start of the operation, so that the driver circuit 1 can operate normally from the time of the high-level timing pulse Φ first input to the driver circuit 1 at the start of the operation.

[Second Embodiment] FIG. 3 is a circuit diagram of a second embodiment of a driver circuit suitable for applying the present invention.

In the driver circuit 2 of this embodiment, the switch SW of the first embodiment is constituted by a MOSFET or the like.

That is, SW2 in FIG. 3 indicates a switch circuit, which includes an N-channel MOSFET M5 which is turned on / off by receiving a reset pulse RS at its gate,
P-channel MOSFET M6 which is turned on in conjunction with FET M5 and connects power supply potential VDD and capacitor C1
A Zener diode DZ1 connected between the gate and source of the MOSFET M6 and having a step-down voltage set to be equal to or lower than the breakdown voltage of the MOSFET M6, and a diode which acts as a resistor when the MOSFET M5 is turned on to generate a gate bias voltage of the MOSFET M6. Pricing type MOSFE
TM4 and the like.

According to such a configuration, the charge amount of the capacitor C1 is initialized at the start of the operation of the driver circuit 2 in the same operation as the timing chart of FIG. 2, and the first timing pulse .PHI. Can be operated normally from the time of input.

In the circuit shown in FIG.
ET and the power supply voltage VDD when the node n1 is reset.
It is necessary to use a P-channel MOS in order to charge the MOS transistor. In such a case, a voltage higher than the breakdown voltage may be applied between the gate and the source. However, according to the circuit of FIG. Can be prevented from being applied.

[Third Embodiment] FIG. 4 is a circuit diagram of a third embodiment of a driver circuit suitable for applying the present invention.

The driver circuit 3 of this embodiment comprises an electrode on the MOSFET M1 side of the capacitor C1 and the power supply potential VDD.
This is an example in which a Zener diode DZ is used as a switching means connected between the Zener diode DZ.

The Zener voltage V of this Zener diode DZ
DZ is set to be smaller than the output amplitude Va of the inverter IN1. Thus, even when the potential of the capacitor M1 on the MOSFET M1 side is indefinite at the start of the operation of the driver circuit 3, the output of the inverter IN1 becomes high level and the potential of the capacitor M1 on the MOSFET M1 side is raised. Can be initially set near the power supply voltage VDD.

That is, when the power supply voltage VDD is supplied to the power supply terminal at the start of the operation, the Zener diode DZ causes a Zener breakdown and a reverse current flows, and the potential of the node n1 becomes the power supply potential VDD and the Zener voltage from the power supply potential VDD. The voltage falls within a voltage range between the potential lower by the voltage (VDD-VDDZ). When the output / Φ of the inverter IN changes from the low level to the high level in this state, the potential of the node n1 is boosted by the potential difference Va, so that the potential of the node n1 is boosted to the power supply potential VDD or higher, and as a result, the Zener diode DZ , And the potential of the node n1 is almost set to the power supply potential VDD.

At the start of operation, the output of inverter IN / Φ
Is at a high level, the charge amount of the capacitor C1 is initialized at least at the timing of the first half cycle when the timing pulse Φ changes from “L” to “H” to “L”, and the subsequent operation is performed normally. Can be done. Moreover,
In this embodiment, the Zener diode DZ is a MOSFET M
1 also functions as a withstand voltage protection element.

[Fourth Embodiment] FIG. 5 is a circuit diagram showing a fourth embodiment of a driver circuit suitable for applying the present invention.

The driver circuit 4 of this embodiment has a capacitor C1 in addition to the configuration of the driver circuit 2 of the second embodiment.
Diode DZ reversely connected between the power supply potential VDD and a connection node n1 of the power MOSFET M1 and the output MOSFET M1
2 is provided.

The Zener diode DZ2 is set such that its Zener voltage VDZ2 is lower than the gate-source breakdown voltage of the output MOSFET M1. With this setting,
For example, even when the charge charged in the capacitor C1 leaks and the potential of the connection node n1 decreases, the gate-source voltage of the output MOSFET M can be prevented from rising above the breakdown voltage due to Zener breakdown.

Further, the Zener voltage VDZ2 is applied to the inverter I
If a value smaller than the output amplitude Va of N1 is selected, one Zener breakdown always occurs while the inverter IN1 outputs the high level and the low level, and the output MOSFET is output at the timing when the timing pulse Φ becomes the low level.
The gate potential of M1 is clamped at a constant bias. As a result, the drive circuit 1 can be operated in the same state every time the period of the timing pulse Φ is obtained, and stable operation can be obtained over a long period of time.

[Fifth Embodiment] FIG. 6 is a circuit diagram showing a fifth embodiment of a driver circuit suitable for applying the present invention.

The driver circuit 5 of this embodiment has a push-pull output in which two N-channel MOSFETs are connected in series between the power supply voltage VDD and the ground at the next stage of the output stage of the circuit of the embodiment of FIG. This is a cascade connection of two stages. Furthermore, in the first stage push-pull output stage,
The Zener diode DZ2 for gate withstand voltage protection shown in FIG. 5 is connected between the power supply voltage VDD and the gate terminal of the MOSFET M1.

Output node n of the first stage push-pull circuit
2 is a second stage push-pull circuit (MOSFET M
3, M4) N-channel MOSFET M3 on the high potential side
Connected to the gate.

The push-pull circuit of the second stage has two Zener diodes DZ3, DZ3 having different directions between the gate and the source of the N-channel MOSFET M3 on the high potential side.
Z4 is connected in series. These Zener diodes DZ3 and DZ4 may generate a potential difference between the output node n2 of the first-stage circuit and the output node n3 of the second-stage circuit due to the parasitic capacitance of the MOSFET M3 and the like. This is to prevent the gate of the MOSFET M3 from being destroyed.

The output node n3 of the second stage circuit is connected to the gate of the N-channel MOSFET M5 on the high potential side of the third stage push-pull output circuit (MOSFET M5, M6). Also in the circuit of the third stage, two Zener diodes DZ5 for withstand voltage protection having different directions between the gate and the source of the N-channel MOSFET M3 on the high potential side.
DZ6 is provided.

In the drive circuit of this embodiment, 1
Stage push-pull circuit (MOSFET M1, M2)
Can be driven by a small drive because the load is only the gate capacitance of the MOSFET M3 in the second stage. Therefore, a small-sized M is used as the first-stage P-channel MOSFET M1.
OSFETs can be used. Small size MOSFET
Since the gate capacitance also becomes smaller, the capacitor C
High-speed driving is possible even if the capacity of the first capacitor is reduced. Further, since the capacity of the capacitor C1 may be small, it is possible to reduce the area of the capacitor C1 and suppress an increase in the chip area required for forming a circuit.

The circuit of the embodiment of FIG. 6 has a larger number of elements in the output stage than the circuits of the embodiment of FIGS.
The second push-pull output stage is constituted by an N-channel MOS. Since the N-channel MOSFET can be considerably smaller than the P-channel MOSFET having the same gm (transfer conductance), the area occupied by the entire drive circuit can be reduced.

Since the high-potential MOSFETs M3 and M5 of the second and third push-pull output circuits are N-channel MOSFETs, respectively,
The gate voltage of the FET M5 is higher than the power supply voltage VDD by MO.
It appears that the voltage rises only to a voltage lower than the threshold voltage of the SFET M3 and that an output up to the power supply voltage VDD cannot be obtained, but the gate of the MOSFET M3 on the high potential side of the second stage push-pull circuit Due to the parasitic capacitance between the sources, the gate potential of the MOSFET M5 of the next stage push-pull circuit is bootstrapped to the power supply voltage VDD or higher, and the MOSFET M5 is sufficiently turned on.

[Sixth Embodiment] FIG. 7 is a circuit diagram showing a sixth embodiment of a driver circuit suitable for applying the present invention.

The driver circuit 6 of this embodiment has a configuration similar to that of the driver circuit 1 of the first embodiment, with the addition of a charge pump circuit 11 (IN2, C2, DB). That is, the inverter IN2 is connected before the inverter IN1, and the power supply voltage VDD and the inverter IN2 are connected.
The diode DB and the capacitor C2 are connected in series between the output terminal of the first embodiment. The source of the MOSFET M1 is connected not to the power supply voltage VDD but to the connection node n5 between the diode DB and the capacitor C2. The control of the push-pull output stage by the inverter IN1 and the operation of the charge pump circuit 11 by the inverter IN2 are simultaneously performed and synchronized by the timing pulse Φ.

The charge pump circuit 11 includes an inverter I
N2, a diode DB, and a capacitor C2. By operating the inverters IN1 and IN2 with signals having opposite phases, when the MOSFET M1 is off, electric charges are charged from the power supply voltage VDD to the capacitor C2 through the diode DB, When the MOSFET M1 is ON, the P-channel MOSFET M1 is hit by hitting the capacitor C2.
The potential of the node n5 to which the source terminal is connected is pushed higher than the power supply voltage VDD.

The diode DB is selected to have a withstand voltage (reverse voltage) about the source-drain withstand voltage of the MOSFET M1, and the capacitor C2 is sufficiently larger than the gate capacitance of the load MOSFET M10 receiving the output voltage of the driver circuit 6. A capacitor having a large capacity (for example, 20 pF) is selected. Thereby, the potential of the node n5 can be boosted to VDD or more when the output / Φ of the inverter IN2 is at the high level.

Although the N-channel MOSFET M10 is shown as the load of the driver circuit 6, the output voltage from the driver circuit 6 is higher than the power supply voltage VDD, so that the gate voltage is clamped between the gate and the source of the MOSFET M10. And a Zener diode DZ7 for preventing gate breakdown.

FIG. 8 is a timing chart for explaining the operation of the driver circuit 6.

This timing chart shows a state after the switch SW is turned on by a reset pulse at the time of turning on the power supply, the initialization is completed, and the normal operation is started. In the figure, VG3 is a load MOSFET
The output voltage of the driver circuit 6 applied to the gate of M10, VGS is the gate-source voltage of the output MOSFET M1, and VS and VG are the output MOSFET M1 respectively.
Are the source potential and gate potential, and Φ and / Φ are input / output timing pulses of the inverters IN1 and IN2, respectively.

As shown in FIG.
When the output / Φ of the inverter IN2 is at a low level due to the operation of the charge pump circuit 11, the diode DB is forward-biased and the charge is charged from the power supply voltage VDD to the capacitor C2 to charge the source potential VS to the potential (VDD).
−VF), and when the output / Φ changes to a high level, the potential is raised to a potential (VDD−VF + Va) higher by the amplitude Va. Here, VF is a forward voltage of the diode DB.

On the other hand, the gate potential VG of the output MOSFET M1 becomes the potential (VDD) when the switch SW is turned on.
−VF), the output Φ of the inverter IN1
And the Zener breakdown of the Zener diode DZ2, when the output Φ of the inverter IN1 is at the low level, the Zener diode DZ breaks down and the gate potential VG is lower than the source potential VS by the Zener voltage VDDZ2 (VDD−VF +
Va−VDDZ2), and when the output φ changes to a high level, the amplitude is raised by the amplitude Va. At this time, the source potential VS falls to (VDD−VF), so that the Zener diode DZ2 is forward-biased, and the gate potential VG becomes VG.
≒ VS (= VDD-VF). Here, VDZ2 is a Zener voltage of the Zener diode DZ2 and is 5 V (> | Vth
p1 |: threshold voltage of MOSFET M1).

Accordingly, the gate-source voltage VGS of the output MOSFET M1 is controlled so as to reciprocate between (0V) and (-VDZ2) in synchronization with the timing pulse Φ, so that the on / off operation is reliably performed. . Also, output MO
At the time of turn-on / turn-off of the SFET M1, the control for stepping down / boosting the gate potential and the control for stepping up / down the source potential are simultaneously performed, and the power supply voltage Va of the control system is set as Va> VDZ2. Since the amplitude of the gate-source voltage VGS is suppressed, the speed of the turn-on / turn-off operation can be increased.

The load MOSFET M10 driven by the output voltage of the driver circuit 6 is composed of an N-channel MOS and has a Zener diode DZ7 between its gate and source.
Is connected to the gate voltage VG3, the voltage (VDD + VF + V) is synchronized with the timing pulse / Φ.
a) is applied, the voltage is clamped by the Zener diode DZ7 and is higher than the power supply potential VDD.
D + VDZ7) and a low-level potential (0 V) are alternately applied, so that the N-channel load MOSFET M10 can be sufficiently turned on / off and the turn-off operation can be sped up. Here, VDZ7 is a Zener voltage of the Zener diode DZ7.

FIG. 9 is a schematic block diagram of a polyphase motor on which the driver circuits 1 to 6 of the first to sixth embodiments are mounted.

In the figure, 101 is a three-phase brushless motor, 111 is a Hall sensor for detecting the rotational position of the motor 101, 112 is a frequency generator (tacho generator) for detecting the rotational speed of the motor 101 in frequency, and 102 is the motor 101 A motor control IC in which a circuit for performing multi-phase drive control and rotation speed control of the motor is integrated and 3 is a motor 10
1 is a motor drive IC in which an output circuit 131 for supplying a multi-phase drive current is integrally formed. The 14th position generates and supplies a control system power supply (for example, 6 V) and a drive system power supply (for example, 12 V) and supplies power. It is a power supply circuit that sometimes outputs a reset pulse RS.

The motor control IC 102 has a Hall amplifier 1 for amplifying the position detection signal Ps from the Hall sensor 11.
21, phase switching circuit (commitment circuit) 122, pre-driver circuit 123, amplifier 124 for amplifying speed detection signal Vs from frequency generator 112, speed detection signal Vs
A zero-cross comparator 125 for shaping the signal into a binary pulse signal V1, a speed control logic 127 for performing a logic operation related to speed control and outputting a timing pulse Φ for speed control, and a clock circuit 1 for generating a reference clock f0
28 etc. are provided.

The output circuit 131 is provided with any one of the driver circuits 1 to 6 of the above embodiment and six sets of current output transistors (the load MOSFET M10 of the embodiment). The driving current for three phases is supplied to the motor 101 in synchronization with the timing pulse Φ from.

As described above, the driver circuits 1 to 1 according to the present invention
6 is a motor capable of high-speed control with low current consumption by improving the driver circuit.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, the P-channel FET to be turned on / off is not limited to the MOSFET constituting the push-pull output stage, and the P-channel FET of the high power supply circuit can be replaced by the output of the low power supply circuit by a dual power supply IC. A similar effect can be obtained by applying the present invention when operating. Examples of such a circuit include a bootstrap circuit and a level shift circuit.

Further, the switch for initial setting is not limited to a configuration that is turned on by a reset pulse at the time of turning on the power supply, and is configured to be turned on at an arbitrary timing when it is desired to initialize the charge amount of the capacitor or the gate potential of the P-channel FET. You may.

Further, in the embodiment, a charge pump including a diode and a capacitor has been exemplified as a circuit for obtaining a boosted voltage, but other various known boosting circuits may be used.

In the above description, the invention made mainly by the present inventor has been described with respect to a driver circuit for synchronous rectification control such as used in a three-phase motor which is the application field in which the invention was made. The present invention is not limited to this and can be widely used for various driver circuits that output current and output voltage.

[0080]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, it is possible to provide a driver circuit capable of high-speed control and consuming less current. Further, there is an effect that a stable operation can be obtained from the initial operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a simplest embodiment of a driver circuit to which the present invention is applied.

FIG. 2 is a timing chart illustrating an operation of the driver circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a second preferred embodiment of a driver circuit to which the present invention is applied.

FIG. 4 is a circuit diagram showing a third preferred embodiment of a driver circuit to which the present invention is applied.

FIG. 5 is a circuit diagram showing a fourth preferred embodiment of a driver circuit to which the present invention is applied.

FIG. 6 is a circuit diagram showing a fifth embodiment of a driver circuit suitable for applying the present invention.

FIG. 7 is a circuit diagram showing a sixth preferred embodiment of a driver circuit to which the present invention is applied.

FIG. 8 is a timing chart illustrating the operation of the driver circuit of FIG. 7;

FIG. 9 is a block diagram illustrating an example of a polyphase motor in which the driver circuit of the embodiment is incorporated.

FIG. 10 is a circuit diagram showing an example of a driver circuit in which a P-channel MOSFET is provided on the high potential side.

[Description of References] 1 to 6 Driver circuit M1 P-channel output MOSFET M10 Load MOSFET C1 Capacitor IN1, IN2 Inverter circuit (output control circuit) SW switch SW1 switch DZ Zener diode (switch means) VDD Drive system power supply voltage (first system) Va) Control system power supply voltage (second system power supply) 11 Charge pump circuit (boost circuit)

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5J055 AX02 AX12 AX27 AX57 BX16 CX10 CX20 DX13 DX14 DX22 DX56 EY10 EY12 EY13 EY21 EY24 EZ07 EZ54 EZ55 EZ61 GX01 GX04 5J056 AA05 BB02 DD30 DD29 DD29 FF07 FF08 GG06 KK01

Claims (1)

[Claims] 1. A P-channel FET having a source connected to a high potential side of a first power supply system and a drain connected to an output terminal.
And an output control circuit that operates at a power supply voltage of a second power supply system lower than the first power supply system, wherein the drive circuit controls the gate of the FET based on the output voltage of the output control circuit. A capacitor is connected between the output terminal of the output control circuit and the gate terminal of the FET, and the output amplitude of the output control circuit is set lower than the gate-source breakdown voltage of the FET; A drive circuit comprising: a switch for initial setting for connecting or disconnecting a connection point between a capacitor and a gate terminal of the FET and a power supply voltage terminal of the first power supply system.