JP2001168303A - Electronic virtual ground memory device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new method of manufacturing an electronic memory device which is integrated on a semiconductor containing a virtual ground cell matrix. SOLUTION: A matrix is formed on a semiconductor substrate 10 as it is provided with continuous bit lines 7 which extend as discrete parallel stripes traversing a substrate 10. The matrix contains a circuit part C' for selective transistors 20, and a decoder equipped with a P-channel and an N-channel MOS transistor and an address circuits A and B are built in a memory device. A process in which an N well 11 where the P-channel transistor is housed is formed on a part A of the substrate, and another process in which the active regions of all transistors are specified by a screen mask 33 and an isolation layer 13 is grown through the intermediary of an opening provided to the mask 33, are at least provided. The active region specifying mask 33 is not opened on the matrix region C" of the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electronic virtual ground memory device integrated on a semiconductor and formed with a matrix of virtual ground cells, and a method of manufacturing the same.

More specifically, the present invention is a method of fabricating an electronic virtual ground memory device integrated on a semiconductor and including a matrix of floating gate memory cells, wherein the matrix is discrete. A decode and decoder formed on a semiconductor substrate having a plurality of continuous bit lines extending across the substrate as parallel stripes, wherein the matrix includes circuit portions for select transistors, and the device includes P-channel and N-channel MOS transistors. Forming an N-well in at least one of said substrate portions incorporating an address circuit portion and containing said P-channel transistor;
The present invention relates to a method including at least a step of defining active regions of all transistors by a screen mask and a step of subsequently growing an isolation layer through an opening of the mask.

[0003]

2. Description of the Related Art As is well known, EPROM or FLAS
An H-EPROM type semiconductor integrated electronic memory device is basically configured in the form of a cell matrix divided into sections, which are sub-matrices formed from memory cell blocks having predetermined dimensions.
Each block has the necessary bias and address lines to locate individual memory cells and decode the information contained therein. Such a memory device is described, for example, in European Patent No. 0 0
573728.

[0004] This earlier document describes a method of forming an integrated device of the EPROM or FLASH-EPROM type in which individual memory blocks include a cell matrix formed from a plurality of mutually orthogonal word lines and bit lines. It has been disclosed. The intersection of a plurality of word lines and bit lines defines a memory cell.

This type of structure, known in the art as a "tablecloth" or intersection matrix, is unique in that bit lines are formed in a semiconductor substrate by parallel, continuous, diffuse stripes.

[0006] An innovative aspect of this particular arrangement is the presence of some metal contacts in the substrate area housing the integrated memory cells, a feature that greatly enhances the ability to integrate on a semiconductor substrate. Enhance.

[0007] Metal contacts are formed only at the ends of the bit lines and provide termination pads for each memory block. An electrical diagram of this arrangement is partially shown in the accompanying FIG. 1 where it can be seen that there are opposing contact areas 4 bounding the plurality of floating gate memory cells 3.

[0008] Each memory cell 3 is bounded by a corresponding continuous main bit line 7, and a discontinuous bit line 17 or bit line "segment". Each segment is connected to an adjacent continuous main bit line 7 by an address active element 20. Each bit line segment has a right or left address active element 20.

In addition, flash memory cells require a field oxide isolation region to maintain a high capacitance ratio between the control gate and the floating gate. However, the presence of the field oxide film means that most of the circuit area on the semiconductor substrate is occupied by the field oxide film.

[0010] Considering the specific examples of EPROMs erased by ultraviolet light or OTP memories that are not erased at all, the high capacitance ratio between the control gate and the floating gate, besides increasing the size of the entire integrated circuit, Obviously too much. Therefore, it is desirable to have a memory cell organization structure that can significantly reduce the circuit area occupied by the matrix while maintaining the matrix configuration.

[0011]

SUMMARY OF THE INVENTION The technical problem underlying the present invention is that a virtual ground cell
To provide a new method of manufacturing an electronic memory device that includes a matrix, which method has features suitable for enabling the production of very dense memory circuits that are smaller in size than conventional devices. Have.

[0012]

The solution behind the present invention is to remove the isolation region of the field oxide from the matrix region of the memory cell and to have a doped region opposite the bit line. This is to realize the separation of the bit lines in the matrix. Based on this idea, the technical problem is solved by the method defined previously and defined in claim 1 above. The features and advantages of the method of the present invention will become more clearly apparent from the following description of embodiments, given by way of non-limiting example in connection with the accompanying drawings.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to the drawings, the flow of processing of the present invention for forming an EPROM and / or an OTP memory will be described below.

For a better understanding of the embodiments of the present invention, see, for example, European Patent Application 968 by the applicant.
No. 3,0657.1, a virtual grounding contactless EEPR
Reference will frequently be made to FIG. 1, which is a fragmentary diagram of the electrical schematic for section or block 1 of the OM memory device.

The memory device can include a plurality of blocks 1 which are integrated to form a memory matrix. Each block 1 includes a plurality of memory cells 3
And a plurality of right or left addresses and a decoding device 20. In particular, it comprises a floating gate MOS device for forming individual memory cells 3 and a control and selection MOS device 20 for performing the function of addressing and decoding individual memory cells 3.

Each n-th memory block 1 is basically a sub-matrix comprising memory cells 3 organized in rows (word lines) and columns (bit lines) and address devices 20. is there. The sub-matrix is integrated in a region of the semiconductor substrate bounded by opposing contact regions 4 arranged to contact both ends of the bit lines formed on the substrate.

For each n-th memory block 1,
The contact area 4 belonging to the predetermined area has a mirror-like symmetrical correspondence to the opposite contact area at the other end of the bit line. Thus, continuous parallel bit lines 7 extending into the nth memory block are bounded by pairs of opposing contact areas 4. Alternatively, these contact regions 4 can be provided only at one end of the bit line.

The plurality of memory cells 3 are defined by intersections of bit lines 7 and word lines. In particular, the cells are arranged beside such intersections and have a right or left decode and address device (transistor) 20.
Are connected by a discontinuous segmented bit line 17 connected to the continuous main bit line 7 via.

In each substrate area of the block 1, a contact area 4
Advantageously, at least one interruption is provided in each nearby bit line 7. This interruption can be implemented by inserting a control switch that acts as a section or block selector.

In a preferred embodiment, each block is
It includes a control switch 8 connected to both ends of each bit line 7 near the contact area 4. In this way, the n-th memory
Bit line 7 of block 1 can be electrically isolated from other blocks cascaded thereto. In order to facilitate the integration of the block selector, it is preferable to connect all the control terminals of the control switch 8 inserted near the same contact area 4 to each other.

Each step of the manufacturing method for producing individually selectable memory blocks in integrated form will now be described in detail. The method proposed here will be described with reference to FIGS. These figures are enlarged vertical cross-sectional views of non-adjacent portions of the semiconductor substrate 10 on which the memory device of the present invention is formed.

More specifically, the first part, denoted by A, represents the semiconductor zone in which the P-channel transistors of the circuit associated with the memory matrix are formed. The second part, denoted by B, is the N of the circuit associated with the memory matrix.
1 represents a semiconductor zone in which a channel transistor is formed.

The third part, denoted C, represents the semiconductor zone in which the cells of the memory matrix are formed. The area of the third part C can be divided into two zones C ′ and C ″, each containing a selection transistor and a suitable cell matrix, as shown in FIG.

Throughout the following description, certain steps of the process are discussed in detail to avoid having to pack into this specification secondary or important elements that are common or well known to those skilled in the art. Absent.

In FIG. 2, the first step of the process is a cell
A step of forming an N well 11 in a portion of the semiconductor substrate 10 where a PMOS transistor linked to a matrix is to be formed. The N-well 11 can be formed by using the N-well mask 12 to completely cover the semiconductor substrate 10 except for the zone where the N-well 11 will be formed.

Next, the mask 12 is removed as before.
Next, active regions of all transistors are formed. The definition of the active regions separated from each other by the isolation region made of the field oxide film 13 is conventionally achieved.

For example, the thin oxide film layer 31 is
The silicon nitride layer 32 is deposited to a thickness in the range of 800-1500 °, and then the field oxide 13 is grown at 900 ° C. in the region where the oxide / silicon nitride bilayer has been removed. It can be grown at a temperature of up to 1080C.

The double layer of the oxide film layer 31 and the silicon nitride layer 32 is removed using an active area defining mask 33 which is open only at a predetermined position 34 where a field oxide film is to be formed.

According to the present invention, the field oxide film 13
Advantageously, only the circuit parts A and B of the circuit associated with the matrix and the matrix part C ′ where the matrix selection transistor is located are provided.
In addition, to improve the planarization of memory devices,
Advantageously, the gate region of the matrix cell is formed in a truly flat part of the semiconductor.

For this purpose, the active area defining mask 34 is patterned with narrow windows in the zone where the separation has to be carried out. In effect, for a given heat treatment, a thinner layer of field oxide will grow in a zone with limited surface area, so this mask will allow the selection transistor's field oxide thickness and circuitry associated with the matrix. Of about 2000 or 3000 degrees between the thickness of the field oxide of this transistor.

Alternatively, two masks can be used, one dedicated to the isolation of the circuit transistors and the other dedicated to the isolation of the select transistors. This allows a thinner field oxide to be grown on the matrix area, but this method is more costly. After defining the active region, a gate oxide layer 35 is grown, an N-channel transistor is formed in part B, and a select transistor is formed in part C '.

Subsequent masking operations allow the gate oxide layer 35 to be part of the matrix C "in order to channel dope the subsequently formed memory cells and modify the threshold voltages of the P-channel and N-channel transistors. And the implantation step can be performed without masking.

The circuit can be shielded by a mask during matrix implantation. Instead, various oxide layers useful for forming the memory cell 3 are grown in the active region.

A further isolation implantation mask is provided to shield the N-well 11. Next, isolation implantation is performed with an energy suitable for distributing the dopant under the field oxide film 13. For N-channel transistors and transistors in zone C ', lighter implants can be used instead.

Capacitively coupled floating gate MOS
To produce a memory cell having a device, the process flow includes a first conductive layer 14 (referred to as poly 1), an interpoly dielectric layer 15, and a second conductive layer 16.
It should provide multiple depositions over the entire area of the semiconductor needed to produce a layer structure including (poly cap).

The material utilized for conductive layers 14 and 16 is typically polysilicon, and the intermediate dielectric layer is, for example, ON
O (oxide film / nitride / oxide film) can be used. The poly cap layer 16 can be doped at this stage of the process. A protective oxide layer 18 or top oxide is deposited over the poly cap layer 16.

FIG. 4 is a cross-sectional view of the layer structure resulting from the last series of steps. At this stage of the manufacturing process, the bit lines of the cell matrix are defined. The bit line 7 is defined by using a mask 21 that withstands the definition of the first conductive layer 14 which is a polysilicon layer. This mask 21 is well known to those skilled in the art as a poly 1 mask.

A poly-1 mask is shown in FIG. By a conventional photolithographic process, the layer structure not protected by the poly 1 mask is converted into a second conductive layer 16, an intermediate dielectric layer 15,
The first conductive layer 14 and the gate oxide film are sequentially removed by etching in order, exposing the substrate. The poly 1 mask is removed and the gate region is sealed with an oxidation process.

The region 19 of the bit line 7 can be defined through the opening 23 of the layer structure by an ion implantation step using arsenic, which is necessary to give the conductivity of N ⁺ . The cell matrix now has openings or trenches 2 through which implants are performed to form bit line regions 19.
3 are considered to be formed from a plurality of continuous stripes separated by three.

This process then provides for the deposition of a first dielectric layer 27, such as silicon oxide, deposited from the liquid or gas phase, into the grooves 23 of the matrix. For example, this layer 2
7 can be a TEOS type when deposited from the liquid phase, or silane grown from the gas phase under certain conditions effective to prevent the formation of cracks or microvoids. The thickness of the layer 27 is illustratively 500 ° suitable for separating the bit lines 7 from each other and covering the gap between them.
Up to 3000 °. Thereafter, a second dielectric layer 28 is deposited, and the gap between the bit lines 7 is filled to flatten the surface of the semiconductor substrate.

This deposition step includes a pre-diffusion operation or spinning of a highly viscous material that is a gel or liquid phase, followed by a coagulation process. A preferred material is a Spin-O comprising a mixture of siloxane and alkyl or aromatic organics adapted to reduce stress on the deposited thin film.
n Glass (SOG). In a preferred embodiment, a mixture of a siloxane and a methyl compound is used.

This coagulation, or more suitably the densification and branching treatment, is hereinafter referred to as "polymerization". Advantageously, the mixture is converted into a highly planarized dielectric layer 28 by a suitable heat treatment applied, for example, at a temperature of 400 ° C. The thickness obtained by this polymerization is, for example, in the range of 3000-6000 °.

At this point, the method of the present invention provides for a partial etch of the second dielectric layer 28 using plasma technology. This unmasked back etch is
This continues until the cap layer 16 is exposed and the top oxide film is also removed. Thus, the second dielectric layer 28 is
As shown in (1), it is confined in the gap region between the bit lines.

A salient feature of this etch is its polysilicon selectivity. Experiments have also shown that the selective etching produced by the plasma technique more closely fulfills the aforementioned requirements. At this point, a maskless phosphorus implant can be performed to dope the poly cap layer 16, if not previously performed.
In any case, the bit line is protected by the planarized dielectric layer 28. After the planarization process, a new photolithographic step using a mask 29, commonly referred to as a matrix mask, is required.

The mask shown in FIG. 8 serves to remove the second conductive layer 16 and the intermediate dielectric layer 15 from the parts A and B intended to integrate P-channel and N-channel transistors. Will be. An optical injection step can also be performed to adjust the threshold voltages of the transistors in parts A and B.

At this point, multiple depositions can be achieved to produce a conductive layer 25 indicated by poly 2 and an optional final conductive layer 26. These layers are more clearly shown in FIG. 11, which is a schematic perspective view of the structure provided by the processing steps performed so far. Materials such as polysilicon and tungsten silicide (WSi ₂ ) are generally used to form conductive layer 25 and final conductive layer 26, respectively. Etching is performed by a photolithographic process using a mask 30 shown in FIG. 9 called a poly 2 mask to define the plurality of gate areas of the memory cell 3, the N- and P-channel transistors of the circuit, and the select transistors. Must achieve.

The mask must have parallel stripes of various widths oriented in a direction perpendicular to the bit lines, similar to the word lines of FIG. By removing the final conductive layer 26, which is a silicide layer, the conductive layer 25 of poly2, and the first conductive layer 14 of poly1, through the poly2 mask, the gates of all the transistors are defined. The etch stops at the gate oxide of the CMOS circuit, and during this matrix etching step, the silicide, poly2, and polycap are etched.

This etch stops at the interpoly dielectric,
This resist is not removed as shown in FIG. Next, a mask is used for a self-aligned etching operation. With this mask, the circuit is double resist
Protected by the level, the word line can be defined once the matrix etch is complete. The intermediate dielectric 15, the poly-1 conductive layer 14, and the gate oxide are removed by etching. Before removing the resist, an implant can be performed to improve bit line isolation.

As shown in FIG. 11, according to the present invention,
Boron P ^- to improve the separation of the bit lines 7 running infusion. The boron implant affects the region of the substrate adjacent to the bit line 7 which is doped opposite to the bit line. Basically, bit line isolation is ensured by diode junctions that are reverse biased during normal operation of the memory matrix.

To avoid the use of dual levels of resist, the poly 2 and self-aligned etch masks can be arranged to separately define circuits and matrices. This step is completed by re-oxidation sealing the second cell.

Thereafter, the processing is performed in the same manner as the conventional CMOS processing, and a series of steps for completing the memory device will be briefly described below without regard to any specific drawing. I will.

Mask N-LDD: This mask is used to implant the sources and drains of P-channel and N-channel transistors as described in US Pat. No. 4,719,184 issued to the assignee of the present invention. .
For example, the mask is arranged to shield the matrix, otherwise the bit lines are re-injected,
You will be short-circuited.

Mask P-LDD: This mask is used to re-implant the source and drain of a P-channel transistor. A dielectric layer is deposited and etched to form spacers. N ⁺ masking for N-channel transistor source and drain implants.

P ⁺ masking for P-channel transistor source and drain implants. A separate dielectric layer is deposited. Contact mask: Define and etch contacts. Contact and ion implantation masks: After removing the resist, an RTP heat treatment follows to activate the implanted species. This masking level and heat treatment requires only self-aligned contacts to the active area,
Optional.

Deposit barrier and tungsten, back etch them and deposit metal. Metal mask: used to define metal stripes. Deposit the finishing dielectric. Pad Exposure Mask: Used to define and etch pads.

In summary, the manufacturing method proposed here solves a technical problem and offers a number of advantages. That is, the main advantages of the resulting circuit architecture are small size and simple design. In fact, the design is simplified because there is no need to provide dedicated isolation to the memory matrix, and the floating gate and control
Since no sophisticated coupling is required between the gates, circuit space for this coupling can be eliminated.

[Brief description of the drawings]

FIG. 1 shows EPROM or FLASH according to the prior art.
FIG. 3 is a circuit diagram showing a memory block constituting an EPROM device.

FIG. 2 is a vertical sectional view schematically showing an enlarged part of a semiconductor substrate during the course of the manufacturing method according to the present invention.

FIG. 3 is a vertical sectional view schematically showing, in an enlarged manner, a part of a semiconductor substrate with the progress of a manufacturing method according to the present invention.

FIG. 4 is a vertical sectional view schematically showing, in an enlarged manner, a part of a semiconductor substrate with the progress of a manufacturing method according to the present invention.

FIG. 5 is a vertical cross-sectional view schematically showing a part of a semiconductor substrate in an enlarged manner with the progress of the manufacturing method according to the present invention.

FIG. 6 is a vertical sectional view schematically showing a part of a semiconductor substrate in an enlarged scale with the progress of the manufacturing method according to the present invention.

FIG. 7 is a vertical sectional view schematically showing, in an enlarged manner, a part of a semiconductor substrate with the progress of a manufacturing method according to the present invention.

FIG. 8 is a vertical sectional view schematically showing, in an enlarged manner, a part of a semiconductor substrate with the progress of the manufacturing method according to the present invention.

FIG. 9 is a vertical sectional view schematically showing an enlarged part of a semiconductor substrate during the course of the manufacturing method according to the present invention.

FIG. 10 is a vertical cross-sectional view schematically showing a part of a semiconductor substrate in an enlarged manner with the progress of the manufacturing method according to the present invention.

FIG. 11 is a perspective view schematically showing a part of a semiconductor substrate which is subjected to a processing step according to the present invention.

[Description of Signs] 3 floating gate memory cell, 7 continuous main bit lines, 10 semiconductor substrate, 11 N well,
12 N-well mask, 13 field oxide, 14 first conductive layer, 15 intermediate dielectric layer, 16
Second conductive layer, 19 regions, 23 openings, 25, 2
6 conductive layer, 31 oxide film layer, 32 silicon nitride layer, 33 active area defining mask.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 (72) Inventor Paolo Caprara Italy, 20100 Milan, Via Gririvola 18 (72) Invention Person Manrio Sergio Ceredda Italy 22050 Romagna Via Via Novel 7F Term (reference) 5B025 AA01 AC01 5F001 AA01 AB02 AD03 AD41 AD51 AD61 AD62 AD63 AG10 AG30 AG40 5F083 EP02 EP22 EP55 ER25 GA09 JA39 LA04 LA05 LA06 LA18 NA04 PR03 PR12 PR23 PR33 PR36 PR38 PR39 ZA01 5F101 BA01 BB02 BD22 BD24 BD32 BD36 BD37 BD38 BH14 BH16 BH21

Claims (7)

[Claims] 1. A method of manufacturing an electronic virtual ground memory device integrated on a semiconductor and comprising a matrix of floating gate memory cells (3), comprising:
The matrix has a plurality of continuous bit lines (7) extending across the substrate (10) as discrete parallel stripes formed on a semiconductor substrate (10), said matrix comprising a circuit portion for a select transistor (20). (C ')
And the device comprises a P-channel and an N-channel M
Forming at least one (A) N-well (11) in said at least one (A) substrate portion, incorporating a decode and address circuit portion (A, B) having an OS transistor; Defining an active area of all transistors with a screen mask (33), and thereafter growing an isolation layer (13) through openings in said mask (33). A method of manufacturing an electronic virtual ground memory device, wherein said mask (33) is not open on a matrix area (C ") of a memory cell. 2. The active area defining mask (33) is patterned so as to provide a narrow opening (24) or a narrow window for said circuit part (C ′) in which isolation is to be performed. 2. The method of manufacturing an electronic virtual ground memory device according to claim 1, wherein: 3. The electron according to claim 1, further comprising the step of injecting into the region adjacent to the bit line region using a dopant of the opposite type to the bit line region. A method of manufacturing a virtual ground memory device. 4. A step of growing an oxide film layer on the matrix region (C ″), and a layer structure including a first conductive layer (14), an intermediate dielectric layer (15), and a second conductive layer (16). Depositing over the entire semiconductor; photolithographically using a poly 1 mask to define a plurality of parallel openings (23) in the layer structure and to demarcate the floating gate region; Self-aligning etching over the active region of the structure (14, 15, 16) and the thin tunnel oxide layer (3) to define said continuous bit line; and on the bit line (7) region (19) Implanting to provide a predetermined conductivity; filling and planarizing the opening (23) with the dielectric (27) over the bit line (7) region (19); a conductive layer of poly 2 (25) and final conductivity Combining and depositing layers (26); photolithographically using a poly 2 mask to form a plurality of parallel openings in the layer structure defining word lines and circuits; and implanting through the openings. And improving the isolation of the bit lines. 2. The method of claim 1, further comprising: 5. The electronic virtual ground of claim 4, wherein said implanting step is performed in a substrate region adjacent to the bit line using a dopant of the opposite type as the bit line. A method for manufacturing a memory device. 6. An electronic virtual ground memory device integrated on a semiconductor and including a matrix of floating gate memory cells (3), wherein the matrix is formed on a semiconductor substrate (10); Substrate (10) as discrete parallel stripes separated from active area
A plurality of continuous bit lines (7) extending across the matrix, the matrix includes a circuit portion (C ') for a select transistor (20), and the device comprises a P-channel and an N-channel.
An electronic virtual ground memory device incorporating decode and address circuit portions (A, B) having channel MOS transistors, wherein the matrix circuit portion (C ") of said memory cells comprises:
An electronic virtual ground memory device characterized by being remote from an isolated field oxide region. 7. An electronic virtual ground memory as claimed in claim 6, including a region adjacent to the bit line (7) region (19), implanted with a dopant of the opposite type to the bit line. device.