JP2001166015A - Edge failure detection device for semiconductor test equipment - Google Patents

Abstract

(57) [Summary] [Purpose] A rate signal is output with a predetermined time delay or a predetermined time earlier than a strobe edge signal.
An edge defect can be detected when these signals are not output for a predetermined number of times. A flip-flop includes a rate signal RSE.
Since the signal RCYC having a period from the input of LE1 to the input of the rate signal RSELEN is output,
If the strobe edge STRB is normally output within this period, the signal R output from each of the ANDs 31 to 3N is output.
W1 to RWN coincide with the output of the flip-flop 30. However, if the strobe edge STRB or the rate signal RATE is delayed, advanced, or not output, the signals RW1 to RWN do not match the output RCYC of the flip-flop 30, and the exclusive OR circuit 42,
The output of 43 becomes high level "1", and an error is detected. The number of timing edges and strobe edges is counted by the cyclic counters 81 and 82,
An error in the number of occurrences is detected by comparing the two values.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test for detecting whether or not a rate signal as a reference clock and a strobe edge signal as a determination timing are normally output when testing the electrical characteristics of a semiconductor device. The present invention relates to a device for detecting an edge defect of a device.

[0002]

2. Description of the Related Art In order to ship a semiconductor device of which performance and quality are guaranteed as a final product, all or a part of the semiconductor device is extracted in each process of a manufacturing section and an inspection section, and its electrical characteristics are inspected. There is a need. The semiconductor test device is a device for inspecting such electrical characteristics. The semiconductor test apparatus gives predetermined test pattern data to the semiconductor device under test, reads output data of the semiconductor device under test thereby, and checks whether there is any problem in the basic operation and function of the semiconductor device under test. The defect information is analyzed from the output data of the semiconductor device to be measured, and the electrical characteristics are inspected.

[0003] The tests in the semiconductor test apparatus are roughly classified into a direct current test (DC measurement test) and a function test (FC measurement test). In the DC test, a predetermined voltage or current is applied from a DC measuring means to an input / output terminal of a semiconductor to be measured to check whether there is any defect in the basic operation of the semiconductor to be measured. On the other hand, in the function test, predetermined test pattern data is given to the input terminal of the semiconductor to be measured from the pattern generating means, and the output data of the semiconductor to be measured is read, and there is no problem in the basic operation and function of the semiconductor to be measured. It is to check whether or not. That is, in the function test, the input timing and the amplitude of each input signal of the semiconductor device to be measured such as an address, data, a write enable signal, and a chip select signal are changed, and the output timing and the output amplitude are changed. The test is performed based on the signal and the strobe edge signal.

[0004]

When performing a function test on a semiconductor device under test using a semiconductor test apparatus, a rate signal serving as a reference clock under test and a strobe edge signal serving as a determination timing are normal. Must be working. Conventionally, in order to check whether or not each of these signals is operating normally, only the presence or absence of the output of the rate signal and / or the strobe edge signal within a predetermined period has been detected. Therefore, even in the case of an edge failure in which the number of outputs (number of outputs) of each signal does not reach the predetermined number, if at least one rate signal and strobe edge signal are output within a predetermined period, it is normal. Was determined. Further, even when the rate signal is output later or later than the strobe edge signal, it is determined that the output is normal if at least one of the rate signal and the strobe edge signal is output within a predetermined period.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances. Even when a rate signal is output with a delay of a predetermined time with respect to a strobe edge signal during a function test, or when a rate signal is output earlier by a predetermined time, the edge defect is generated. It is a first object of the present invention to provide an edge failure detection device of a semiconductor test device capable of detecting an error.

A second object of the present invention is to provide an edge failure detecting device of a semiconductor test device capable of detecting whether or not a predetermined number of rate signals and strobe edge signals are output during a function test. The purpose of.

[0007]

According to a first aspect of the present invention, there is provided an edge failure detecting apparatus for a semiconductor test apparatus according to the present invention, which receives a strobe edge signal and outputs the first to Nth strobe edge signals in accordance with the input order. A strobe edge selecting means for outputting a strobe selection signal; the first to Nth strobe selection signals output from the strobe edge selecting means being shared by respective enable terminals; and the strobe edge signal being shared by a clock terminal. First to N-th flip-flop circuit means configured to input the output of the inverting output terminal to the input terminal, and a rate signal, and input the first to N-th flip-flop circuit means in accordance with the input order. Rate selecting means for outputting the N-th rate selection signal; and the first to N-th flip-flop circuit means. From the first to the N-th outputs AND signals based on the same signal between the output signal and the first to the N-th rate selection signals output from the rate selection means. AND circuit means, a first OR circuit means for outputting a logical sum signal based on the outputs of the first to Nth AND circuit circuits, and the output from the rate selecting means A rate flip-flop circuit configured to input a first rate selection signal to a clock terminal and an output of an inverted output terminal to an input terminal; and a signal output from the first flip-flop circuit means. A first exclusive-OR circuit means for outputting an exclusive-OR signal based on a signal outputted from the rate flip-flop circuit means and the first exclusive-OR circuit means; A rate error detection flip-flop circuit configured to input the output exclusive OR signal to an input terminal and the strobe edge signal to a clock terminal, and a signal output from the OR circuit unit Second exclusive-OR circuit means for outputting an exclusive-OR signal based on the signal output from the rate flip-flop circuit means, and
Flip-flop circuit means for strobe edge error detection configured to input the exclusive OR signal output from the second exclusive OR circuit means to an input terminal and to input the rate signal to a clock terminal; It is provided with.

The rate flip-flop circuit means outputs a signal having a cycle between the input of the first rate signal and the input of the Nth rate signal. If the strobe edge signal has been output, the logical product signals output from the first to Nth logical product circuit means match the output of the rate flip-flop circuit means. However, if the output of the rate signal is delayed or advanced with respect to the strobe edge signal when the strobe edge signal is normally output, the output is output from the first to Nth AND circuits. The logical product signal does not match the output of the rate flip-flop circuit means, the outputs of the first and second exclusive OR circuits become high level "1", and an error is detected. Similarly, when the output of the strobe edge signal is delayed or advanced with respect to the rate signal when the rate signal is normally output, the output from the first to N-th logical product circuit means is similarly obtained. The logical product signal to be output does not match the output of the rate flip-flop circuit means, the outputs of the first and second exclusive OR circuits become high level "1", and an error is detected.

According to a second aspect of the present invention, there is provided an edge failure detecting apparatus for a semiconductor test apparatus according to the first aspect, wherein timing for cyclically counting a timing edge signal based on the strobe edge signal during a function test is provided. A counting means, a strobe counting means for cyclically counting the strobe edge signal during the function test, and a count for comparing the count values of the timing counting means and the strobe counting means at the end of the function test and outputting the comparison result Error detecting means.

Since the strobe edge signal is generated based on the timing edge signal, the number of both of them is counted by the cyclic type timing counting means and the strobe counting means. If they are different, it means that the number of strobe edge signals is small, and the count error detecting means detects an error. In addition, since the cyclic counting means is used, it is not necessary to count all the numbers of the strobe edge signals, so that it is easy to realize in terms of hardware.

According to a third aspect of the present invention, in the edge failure detecting apparatus for a semiconductor test apparatus according to the second aspect of the present invention, the cyclic count values of the timing counting means and the strobe counting means are changed from the first to the Nth. And the minimum value including the total number N of the flip-flop circuit means up to this point. This is because, if the number of shots equal to or greater than the cyclic count value described in claim 2 is insufficient, accurate error detection by the counting means may not be possible. 3. The edge failure detecting device according to claim 2, wherein the count value of the cyclic counting means is set to a value including the total number of flip-flop circuit means described in (1). An error can be detected, and when the number of shots is smaller than the count value, the edge defect detection device according to the first aspect can detect the error.

According to a fourth aspect of the present invention, there is provided an edge failure detecting apparatus for a semiconductor test apparatus, comprising: timing counting means for cyclically counting a timing edge signal as a basis of a strobe edge signal during a function test; Strobe counting means for cyclically counting the edge signal during the function test, and count error detection means for comparing the count values of the timing count means and the strobe count means at the end of the function test and outputting the comparison result. It is a thing. This is a case where the edge failure detecting device is configured using only the cyclic counting means according to claim 2. In this case, it is possible to detect the edge failure below the count value of the counting means. Become.

[0013]

An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a block diagram schematically showing an overall configuration of the semiconductor test apparatus. The semiconductor test device is roughly composed of a tester unit 50 and a semiconductor mounting device 70. The tester unit 50 includes a control unit 51 and a DC measurement unit 5
2, timing generating means 53, pattern generating means 54,
It comprises pin control means 55, pin electronics 56, fail memory 57, and input / output switching means 58.
Although the tester unit 50 has various other components,
Only necessary parts are shown in this specification.

The tester unit 50 and the semiconductor mounting device 70 are connected by signal lines including a plurality of (a) coaxial cables or the like corresponding to the total number of input / output terminals (a) of the semiconductor mounting device 70. The connection relationship between the terminal and the coaxial cable is associated with each other by a relay matrix (not shown), and transmission of various signals is performed between a predetermined terminal and the coaxial cable. In addition,
The number of the signal lines is physically the same as the total number a of the input / output terminals of the semiconductor mounting device 70. Semiconductor mounting device 70
Is configured such that a plurality of semiconductor devices 71 to be measured can be mounted on a socket. The input / output terminals of the semiconductor device 71 to be measured and the input / output terminals of the semiconductor mounting device 70 are connected in one-to-one correspondence. For example, a semiconductor device 71 to be measured having 28 input / output terminals
In the case of the semiconductor mounting device 70 capable of mounting ten semiconductor devices, the semiconductor device has 280 input / output terminals in total.

The control means 51 controls, operates and manages the entire semiconductor test apparatus, and has a microprocessor structure. Therefore, although not shown, the control means 51 includes a ROM for storing a system program, a RAM for storing various data, and the like. The control unit 51 is connected to the DC measurement unit 52, the timing generation unit 53, the pattern generation unit 54, the pin control unit 55, and the fail memory 57 via a tester bus (data bus, address bus, control bus) 69. The control means 51 sends the data for the DC test to the DC measurement means 52,
The timing data for starting the function test is output to the timing generating means 53, the program and various data necessary for generating the test pattern are output to the pattern generating means 54, and the expected value data and the like are output to the pin control means 55.
In addition, the control means 51 transmits various data to the tester bus 6.
9 to each component. Also,
The control means 51 includes an internal register in the DC measurement means 52,
From the fail memory 57 and the pass / fail (PASS / FAIL) register 63 in the pin control means 55, data indicating test results (DC data or pass / fail data P
FD) are read and analyzed to determine the quality of the semiconductor device 71 to be measured.

The DC measuring means 52 receives the DC test data from the control means 51 and performs a DC test on the semiconductor device 71 to be measured of the semiconductor mounting apparatus 70 based on the data. The DC measurement means 52 starts a DC test by inputting a measurement start signal from the control means 51, and writes data indicating the test result to an internal register. When the writing of the test result data is completed, the DC measuring means 52 outputs an end signal to the control means 51. The data written in the internal register is transmitted to the control unit 51 via the tester bus 69.
Is read and analyzed there. Thus, the DC test is performed. Further, the DC measuring means 52 supplies the reference voltages VIH, VIL, VOH, VO to the driver 64 of the pin electronics 56 and the analog comparator 65.
L is supplied.

The timing generation means 53 includes a control means 51
Is stored in the internal memory, and a rate signal RATE, which is a high-speed operation clock, is output to the pattern generation means 54, the pin control means 55, and the fail memory 57 based on the timing data, and the timing for writing and reading data is obtained. The signal PH is output to the pin control means 55 and the fail memory 57, and the strobe edge signal STRB is output to the pin electronics 56. Therefore, the operation speed of the pattern generation means 54 and the pin control means 55 is determined by the rate signal RATE, and the timing of writing and reading data to and from the semiconductor device 71 to be measured is determined by the timing signal PH. The timing of writing the pass / fail data PFD to the fail memory 57 is also determined by the timing signal PH. Therefore, the output timing of the test signal P2 output from the formatter 60 to the pin electronics 56 and the output timing of the switching signal P6 output from the I / O formatter 61 to the input / output switching unit 58 are also the same as the rate signal RATE from the timing generation unit 53 and the timing. It is controlled according to signal PH. The timing generator 53 receives the timing switching control signal CH from the pattern generator 54, and switches the operation cycle, phase, and the like as appropriate based on the control signal CH.

The pattern generator 54 receives a pattern program (microprogram and pattern data) for pattern creation from the controller 51 and outputs pattern data PD based on the pattern program to the data selector 59 of the pin controller 55. That is, the pattern generating means 54
Is a program method of outputting regular test pattern data by various arithmetic processes according to a microprogram method, and the same data as the data to be written to the IC under test 71 is previously written in an internal memory (random pattern memory). Is read out at the same address as the semiconductor to be measured, and operates in a memory-stored manner in which irregular (random) pattern data (expected value data) is output. The test of the memory portion of the mixed memory type semiconductor device is executed by a program method, and the test of the logic portion is executed by a memory stored method.

The pin control means 55 includes a data selector 59,
Formatter 60, I / O formatter 61, comparator logic circuit 62, and pass / fail (PASS /
FAIL) register 63. The data selector 59 is composed of a memory storing various test signal creation data (address data / write data) P1, switching signal creation data P5 and expected value data P4, and stores the pattern data from the pattern generation means 54. Input as an address, and test signal creation data P corresponding to the address.
1 and the switching signal creation data P5 are output to the formatter 60 and the I / O formatter 61, and the expected value data P4 is output to the comparator logic circuit 62. The formatter 60 has a multi-stage configuration of flip-flop circuits and logic circuits. The formatter 60 processes test signal creation data (address data / write data) P1 from the data selector 59 to create a predetermined applied waveform. To the test signal P2
As the timing signal P from the timing generation means 53
It outputs to the driver 64 of the pin electronics 56 at the timing synchronized with H. Like the formatter 60, the I / O formatter 61 has a multi-stage configuration of flip-flop circuits and logic circuits.
The switching signal creation data P5 is processed to create a predetermined applied waveform, which is output as a switching signal P6 to the input / output switching means 58 at a timing synchronized with the timing signal PH from the timing generation means 53.

The comparator logic circuit 62 compares and determines the digital read data P3 from the analog comparator 65 of the pin electronics 56 with the expected value data P4 from the data selector 59, and passes / fails data PFD indicating the result of the comparison. Is output to the pass / fail register 63 and the fail memory 57. The pass / fail register 63 is set to fail (FAI) by the comparator logic circuit 62 in the function test.
L) is a register for storing whether or not it has been determined that
The number of bits corresponds to the number of semiconductor devices 71 to be measured that can be mounted on the semiconductor mounting device 70. That is, the semiconductor device 71 to be measured is
If a maximum of 32 devices can be mounted in the memory, the pass / fail register 63 has a 32-bit configuration. If the corresponding bit of the pass / fail register 63 is a low-level “0” pass (PASS), the semiconductor device under test 7
1 is determined to be non-defective, and in the case of a high-level “1” fail (FAIL), the semiconductor device 7 to be measured
1 has some defect and is determined to be defective. Therefore, when analyzing the defective portion in detail, it is necessary to use the fail memory 57.

The pin electronics 56 includes a plurality of drivers 64 and an analog comparator 65. One driver 64 and one analog comparator 65 are provided for each input / output terminal of the semiconductor mounting device 70, and one of them is connected via the input / output switching means 58. The input / output switching means 58 switches the connection state between one of the driver 64 and the analog comparator 65 and the input / output terminal of the semiconductor mounting device 70 in accordance with the switching signal P6 from the I / O formatter 61. is there. That is, when the number of input / output terminals of the semiconductor mounting device 70 is m, the driver 64, the analog comparator 65, and the input / output switching unit 5
8 is composed of m pieces. However, when measuring memory semiconductors etc., analog comparators are not required for address terminals, chip select terminals, etc.
The number of analog comparators and input / output switching means may be small.

The driver 64 is connected to input / output terminals of the semiconductor mounting device 70, that is, signal input terminals such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal of the semiconductor device 71 to be measured.
8, a high-level “H” or low-level “L” signal corresponding to the test signal P2 from the formatter 60 of the pin control unit 55 is applied, and a desired test pattern is written to the semiconductor device 71 to be measured. The analog comparator 65 inputs a signal output from the data output terminal of the semiconductor device 71 to be measured via the input / output switching means 58, and receives the signal at the timing of the strobe edge signal STRB from the timing generation means 53. VO
L, and compares the comparison result with the digital read data P3 of high level “PASS” or low level “FAIL”.
Is output to the comparator logic circuit 62. Normally, the analog comparator 65 is composed of two comparators for the reference voltage VOH and the reference voltage VOL, but is omitted in the figure.

The fail memory 57 stores pass / fail data PF output from the comparator logic circuit 62.
D is stored in an address position corresponding to the address signal AD from the pattern generation means at the input timing of the timing signal PH from the timing generation means 53.
The fail memory 57 is a CMOS readable and writable CMOS memory having the same storage capacity as the semiconductor device 71 to be measured.
It is constituted by a RAM, and is used when analyzing a defective portion or the like in detail when the semiconductor device under test 71 is determined to be defective. Therefore, the fail memory 57 is not used in the ordinary simple pass / fail judgment. Further, the fail memory 57 has a data input / output terminal fixedly corresponding to the data output terminal of the semiconductor mounting device 70. For example, the semiconductor mounting device 7
0 has 280 input / output terminals, of which 160
If the number is the data output terminal, the fail memory 5
Reference numeral 7 denotes a memory having data input terminals equal to or more than the number of data output terminals. The pass / fail data PFD stored in the fail memory 57 is read out by the control means 51, transferred to a data processing memory (not shown), and analyzed.

Hereinafter, the configuration and operation of the edge failure detecting device of the semiconductor test device according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of an edge defect detection device of a semiconductor test device according to an embodiment of the present invention.
The edge defect detection device shown in FIG. 1 checks whether the rate signal RATE and the strobe edge signal STRB output from the timing generation means 53 are output for a predetermined number of times, and the rate signal is output during the function test. An edge defect is detected when the edge signal is output with a predetermined time delay, is output earlier by a predetermined time, or is not output at all. FIG. 3 is a timing chart showing the operation of the edge defect detection device of FIG. The timing chart of FIG.
1 to 2N and 13 (N = 13) AND circuits 31 to 3N are shown. Accordingly, in the following description, the flip-flop circuit 213, the AND circuit 313, and the strobe synchronization circuit 2N, the AND circuit 3N, the strobe synchronization selection signal WCLKN, the rate synchronization selection signal RSELN, and the AND signal RWN of FIG. Selection signal WCLK13, rate synchronization selection signal RSEL
13 and the logical product signal RW13.

The edge defect detecting device shown in FIG. 1 includes an N cycle error detecting unit for detecting an error during a function test, and a count error detecting unit for detecting a number error after the function test is completed. The N-cycle error detector detects whether or not the rate signal RATE is input during the N cycles of the strobe edge signal STRB during the function test. The N-cycle error detector detects that the strobe edge signal STRB has a cycle shift of N cycles or more from the rate signal RATE. Occurs or is not output or the rate signal RATE
If is not output, detect an error. The N cycle error detection unit includes a rate select circuit 10, a strobe edge select circuit 20, flip-flop circuits 21 to
2N, 30, 44, and 45; AND circuits 31 to 3N; OR circuits 41 and 46; and exclusive OR circuits 42 and 43.

First, the configuration of the N-cycle error detector will be described. The strobe edge generation circuit 11 outputs a strobe edge signal STRB corresponding to the timing edge signal T_EDGE to the strobe edge counter circuit 8.
2. Output to the clock terminals of the strobe edge select circuit 20, the flip-flop circuits 21 to 213, and the flip-flop circuit 45 for detecting a rate output error. The strobe edge signal STRB output from the strobe edge generation circuit 11 is supplied to an analog comparator 65 connected to each semiconductor device 71 to be measured. As shown in FIG. 3, since the first four rate signals RATE1 to RATE4 are dummy cycles, the strobe edge generation circuit 11 outputs the rate signal R
The strobe edge signal STRB1 is output in response to ATE5.

The rate select circuit 10 outputs the rate signal R
ATE is input to a clock terminal, and corresponding rate synchronization selection signals RSEL1 to RSEL13 are output to the respective AND circuits 31 to 313, and the rate synchronization selection signal RSEL is output.
EL1 is output to the clock terminal of the flip-flop circuit 30 for detecting an error exceeding the cycle. As shown in FIG. 3, since the first four rate signals RATE1 to RATE4 are dummy cycles, the rate select circuit 10 rises in synchronization with the rise of the rate signals RATE5, RATE18, and the rate signals RATE6, RATE19.
And outputs a rate synchronization selection signal RSEL1 which falls in synchronization with the rising edge of the AND circuit 31 and the clock terminal of the flip-flop circuit 30. Further, the rate select circuit 10 rises in synchronization with the rise of the rate signals RATE6 and STRB19, and
7. A rate synchronization selection signal RSEL2 that falls in synchronization with the rise of RATE20 is output to the AND circuit 32. Similarly, the rate select circuit 10 rises in synchronization with the rise of the predetermined rate signal RATEn, and the next rate signal RAT of this rate signal RATEn.
The rate synchronization selection signals RSEL3 to RSEL13 falling in synchronization with the rise of E (n + 1) are sequentially output to the AND circuits 33 to 313, respectively.

The strobe edge select circuit 20 inputs a strobe edge signal STRB output from the strobe edge generation circuit 11 to a clock terminal, and synchronizes with the strobe edge select signal WCLK1 to WCLK1.
3 is output to the enable terminal of each of the flip-flop circuits 21 to 213. That is, as shown in FIG. 3, the strobe edge select circuit 20 rises in synchronization with the rise of the strobe edge signals STRB1 and STRB14, and the strobe edge signals STRB13 and STRB rise.
A strobe synchronization selection signal WCLK1 that falls in synchronization with the rising edge of the strobe edge signal STRB2 is input to the enable terminal of the flip-flop circuit 21.
A strobe synchronization selection signal WCLK that rises in synchronization with the rising edge of RB15 and falls in synchronization with the rising edges of strobe edge signals STRB14 and STRB27.
2 is output to the enable terminal of the flip-flop circuit 22. Similarly, the strobe edge select circuit 20
Rises in synchronization with the rise of a predetermined strobe edge signal STRBN, and this strobe edge signal S
The twelfth strobe edge signal STRB from TRBn
The strobe synchronization selection signals WCLK3 to WCLK13 falling in synchronization with the rise of (n + 12) are output to the enable terminals of the flip-flop circuits 23 to 213, respectively.

The flip-flop circuits 21 to 213 use the strobe synchronization selection signals WCLK1 to WCLK13 output from the strobe edge selection circuit 20 as active low enable terminals and clock the strobe edge signal STRB output from the strobe edge generation circuit 11 as clocks. The terminals output the output from the inverted output terminal to the input terminal, respectively, and output the strobe synchronization selection signals WCLK1 to WCL.
When K13 is at the low level "0", the output from the inverted output terminal thereof is synchronized with the rising of the strobe edge signal STRB and the strobe synchronization signals WCYC1 to WCYC are output.
13 to each of the AND circuits 31 to 313. That is, as shown in FIG.
Since 213 is set to active low, it is output from the output terminal Q in synchronization with the rising of the strobe edge signal STRB input to the clock terminal when the strobe synchronization selection signals WCLK1 to WCLK13 are at the low level “0”. Strobe synchronization signals WCYC1 to WCYC
13 are sequentially inverted. Therefore, the flip-flop circuit 2
The strobe synchronization signal WCYC1 output from 1 is inverted from the low level “0” to the high level “1” in synchronization with the rising edge of the strobe edge signal STRB1, and the high level “1” is synchronized in synchronization with the rising edge of the strobe edge signal STRB14. ”To the low level“ 0 ”. The strobe synchronization signal WCYC2 output from the flip-flop circuit 22 is inverted from a low level “0” to a high level “1” in synchronization with the rising of the strobe edge signal STRB2, and becomes high in synchronization with the rising of the strobe edge signal STRB15. Invert from level “1” to low level “0”. Similarly, the strobe synchronization signal WCY output from the flip-flop circuits 23 to 213
C3 to WCYC13 are the strobe edge signals STRB.
3 to invert from low level “0” to high level “1” in synchronization with the rise of STRB13, and invert from high level “1” to low level “0” in synchronization with the rise of strobe edge signals STRB16 to STRB26. . Similarly, the strobe synchronization signals WCYC1 to WCYC
The YC 13 repeats inversion at thirteen periods of the strobe edge signal STRB.

Each of the AND circuits 31 to 313 includes a strobe synchronization signal WCYC1 to WCYC13 output from the flip-flop circuits 21 to 213 and the rate select circuit 1
0, the rate synchronization selection signals RSEL1 to RSEL1
The AND signals RW1 to RW13 with the EL13 are output to the OR circuit 41. As shown in FIG. 3, the strobe synchronization signal W output from the flip-flop circuits 21 to 213
When the strobe edge signal STRB is normally output from the strobe edge generation circuit 1, the CYC1 to WCYC13 output the high level “1” in synchronization with the output of the strobe edge signal STRB for a time corresponding to 12 strobe edge signals STRB.
, So that each of the AND circuits 31 to 31
313 is a rate synchronization selection signal RSEL1 to RSEL13.
And outputs the same AND signals RW1 to RW13 to the OR circuit 41. The logical sum circuit 41 outputs the logical product signals RW1 to RW
13 to the exclusive OR circuit 43.
Therefore, the logical sum circuit 41 outputs the logical sum of the high level "1" from the rising point of the strobe edge signal STRB1 as the continuous logical product signals RW1 to RW13 as shown in FIG. 3 to the rising point of the strobe edge signal STRB14. The signal is output to exclusive OR circuit 42.

On the other hand, the flip-flop circuit 30 inputs the rate synchronization selection signal RSEL1 output from the rate selection circuit 10 to the clock terminal, and exclusively converts the rate synchronization signal RCYC obtained by inverting the signal from the output terminal Q accordingly. Output to the OR circuits 42 and 43. That is, the flip-flop circuit 30 outputs to the exclusive OR circuits 42 and 43 a rate synchronizing signal RCYC which is inverted at a period corresponding to 13 rate signals RATE. The reason that the rate synchronizing signal RCYC is inverted at a period corresponding to thirteen of the rate signals RATE is when the rate signal RATE is normally output and when the output of the rate signal RATE is abnormal, The relationship no longer holds.

The exclusive OR circuit 42 is provided with the OR circuit 41.
OR signal output from the flip-flop circuit 30
And outputs the exclusive OR signal R_EOR to the strobe edge output error detection flip-flop circuit 44. As shown in FIG. 3, AND signals RW1 to RW1
3 is the logical product of the strobe synchronization signals WCYC1 to WCYC13 and the rate synchronization selection signals RSEL1 to RATE13. Therefore, when the strobe edge signal STRB and the rate signal RATE are output normally, the rate synchronization selection signals RSEL1 to RSEL1 are output. RATE13 is used as the logical product signals RW1 to RW13 as logical product circuits 31 to 31
3 is output. Therefore, the logical sum signal output from the logical sum circuit 41 and the rate synchronization signal RCYC are the same, and the output of the exclusive logical sum circuit 42 is always at the low level “0”.

The exclusive OR circuit 43 outputs a strobe synchronization signal WCYC output from the flip-flop circuit 21.
1 and an exclusive OR of the rate synchronization signal RCYC output from the flip-flop circuit 30 and outputs the exclusive OR signal W_EOR to the flip-flop circuit 45 for detecting a rate output error. As shown in FIG. 3, the strobe synchronization signal WCYC1 is the strobe edge signal ST
This signal is a signal which rises to a high level “1” in synchronization with the rising of RB1 and falls to a low level “0” in synchronization with the rising of the strobe edge signal STRB14, and is inverted at a period corresponding to 13 strobe edge signals STRB. , The rate synchronizing signal RCYC is the rate signal RAT.
1 of the rate signal RATE that rises to a high level “1” in synchronization with the rise of E5 and falls to a low level “0” in synchronization with the rise of the rate signal RATE18
This signal is inverted at a period corresponding to three signals. Therefore, when the strobe edge signal STRB and the rate signal RATE are output normally, the strobe synchronization signal WC
YC1 and the rate synchronization signal RCYC are the same, and the output of the exclusive OR circuit 43 is always at the low level “0”.

The flip-flop circuit 44 outputs an exclusive OR signal R_EOR output from the exclusive OR circuit 42.
Is latched in synchronization with the rate signal RATE, and the strobe output error signal ERRR is output to the OR circuit 46. The flip-flop circuit 45 includes the exclusive OR circuit 4
3 is latched in synchronization with the strobe edge signal STRB, and the rate output error signal ERRW is output to the OR circuit 46.
The OR circuit 46 includes flip-flop circuits 44 and 45
Is output to the OR circuit 47.

Next, after the function test is completed, the rate signal RAT
The configuration of the count error detection unit that detects whether the E and strobe edge signals STRB have been output for a predetermined number of times will be described. The count error detecting unit counts the number of timing edge signals generated from the timing generation means 53 and the number of strobe edge signals for generating a determination timing based on the timing edge signals by a 5-bit counter while the semiconductor test apparatus is operating. Then, an error is detected by comparing the value of this counter at the end of the function test. The count error detector is
It comprises a timing edge counter circuit 81, a strobe edge counter circuit 82, a comparison circuit 83, and an AND circuit 84. FIG. 4 is a timing chart showing the operation of the counter error detection unit. The timing edge counter circuit 81 is a 5-bit counter circuit, receives the timing signal PH output from the timing generation unit 53, and receives the timing edge signal T_E.
The DGE is counted from “0” to “1f”, and the count value EDGE_CNT is output to the comparison circuit 83. The strobe edge counter circuit 82 is also a 5-bit counter circuit, receives a strobe edge signal STRB, and sets the strobe edge signal to "0" to "1f".
And outputs the count value STRB_CNT to the comparison circuit 83. The comparison circuit 83 counts the count value EDG output from the timing edge counter circuit 81.
E_CNT is compared with the count value STRB_CNT output from the strobe edge counter circuit 82, and if they are equal, a low-level “0” signal is output to the AND circuit 84 if they are not equal. I do. The AND circuit 84 outputs the comparison enable signal CMP_E
N is input, and a signal ERRCNT indicating the comparison result of the comparison circuit 83 is output to the OR circuit 47 in accordance with the timing. The OR circuit 47 outputs an OR signal of the OR signal ERR output from the OR circuit 46 and the AND signal ERRCNT output from the AND circuit 84. FIG.
(A) shows the case where the count value EDGE_CNT of the timing edge counter circuit 81 and the count value STRB_CNT of the strobe edge counter circuit 82 are equal, that is, normal. FIG. 4B shows a case where one strobe edge signal is insufficient. As is apparent from FIG. 4B, the count value S of the strobe edge counter circuit 82 due to the lack of the strobe edge signal.
TRB_CNT becomes “1f” when the comparison enable signal CMP_EN is input, and the count value EDGE_CNT of the timing edge counter circuit 81 is “0”.
And different. Therefore, at this time, the logical product circuit 84 outputs the logical product signal ERRCNT of the high level “1” to the logical sum circuit 4.
7 is output. Thus, the OR circuit 47 outputs
An OR signal ERR indicating an error is output.

Next, the operation of the edge defect detecting device of FIG. 1 for detecting an error will be described with reference to the drawings. FIGS. 5 and 6 are diagrams for explaining an error detection operation of the edge defect detection device of FIG. FIG. 5A shows that the n-th rate signal RATEn is n + (1).
3-4) The first strobe edge signal STRB (n +
It is a figure which shows the timing chart at the time of generating after (13-4)). Here, the numerical value "4" corresponds to the first four rate signals RATE1 to RATE4 being dummy cycles. In the figure, when n = 6, that is, when the rate signal RATE6 is the strobe edge signal STR
This shows a case where it occurs later than B15. In this case, the rate synchronization selection signal RSEL1 output from the rate selection circuit 10 is the strobe edge signal STR
B1 rises to the high level “1” at the same time as the rise of the rate signal RATE5, and the strobe edge signal S
When the rate signal RATE6 rises at the same time as TRB15, it falls to low level "0". Then, the next time that the rate synchronization selection signal RSEL1 rises to the high level "1" until the rate signal RATE18 is output. Therefore, the rate synchronizing signal RCYC output from the flip-flop circuit 30 is maintained at the high level “1” from the rising of the rate signal RATE5 to the high level “1” until the rate signal RATE18 is output. Become. Strobe edge signal S
When the TRB 14 is output, the AND circuits 31 to 313
Signals RW1 to RW13 (logical sum signals output from the logical sum circuit 41) output from the low level "0"
, The rate synchronization signal RCYC
Remains at the high level “1”, the exclusive OR circuit 4
Exclusive OR signal R_EOR from 2 to high level “1”
Is output. The flip-flop circuit 44 for detecting a strobe edge output error outputs the exclusive OR signal R of high level “1” output from the exclusive OR circuit 42.
_EOR is latched and output to the OR circuit 46 as a strobe edge output error signal ERRR. As a result, the OR circuits 46 and 47 output the OR signal ERR indicating an error.

FIG. 5B shows the n-th rate signal RAT.
En is n- (1 + 4) strobe edge signal ST
FIG. 9 is a diagram showing a timing chart when the error occurs before RB (n− (1 + 4)). In the figure, when n = 6, that is, when the rate signal RATE6 is the strobe edge signal S
This shows a case where the error occurs before TRB1. In this case, the rate synchronization selection signal RSEL1 output from the rate selection circuit 10 rises to a high level “1” at the rise of the rate signal RATE5, and the rate signal R
At the rise of ATE6, it falls to low level "0". The rate synchronization selection signal RSEL2 rises to a high level “1” at the rise of the rate signal RATE6, and falls to a low level “0” at the rise of the rate signal RATE7. At this time, the rate synchronizing signal RCYC output from the flip-flop circuit 30 rises to a high level “1” at the rise of the rate signal RATE5 and maintains the high level “1” until the rate signal RATE18 is output. become. However, since the strobe edge signal STRB1 is not output until the rate signal RATE7 is output, the strobe synchronization signals WCYC1 to WCYC13 remain at the low level “0” and the logic output from the AND circuits 31 to 313. The product signals RW1 to RW13 (logical sum signals output from the logical sum circuit 41) also remain at the low level “0”. On the other hand, since the rate synchronizing signal RCYC is at the high level “1”, the exclusive OR circuit 42 outputs the exclusive OR signal R_EOR at the high level “1”. The strobe edge output error detection flip-flop circuit 44 latches the high-level “1” exclusive-OR signal R_EOR output from the exclusive-OR circuit 42, and outputs the result as the strobe edge output error signal ERRR. Output to 46. Thereby, the OR circuit 4
From 6 and 47, a logical sum signal ERR indicating an error is output.

FIG. 6 shows the n-th strobe edge signal S
TRBn is the n- (13-4) th rate signal RATE
It is a figure showing a timing chart when it occurs before (n- (13-4)). The figure shows a case where n = 14, that is, a case where the strobe edge signal STRB14 occurs before the rate signal RATE5. In this case, the rate synchronization selection signal RSEL1 output from the rate selection circuit 10 is the strobe edge signal ST
It rises to a high level “1” at the rise of the rate signal RATE5 at the same time as RB14, and falls to low level “0” at the rise of the rate signal RATE6 at the same time as the strobe edge signal STRB15. Next, the rate synchronization selection signal RSEL1 rises to the high level "1" until the rate signal RATE18 is output. Therefore, the rate synchronizing signal RCYC output from the flip-flop circuit 30 is the strobe edge signal STCY.
It is at low level “0” from the output of RB1 until the rise of the rate signal RATE5. On the other hand, when strobe edge signal STRB1 is output, strobe synchronization signal WCYC output from flip-flop circuit 21 is output.
Since 1 is high level “1”, the exclusive OR signal W_EOR output from the exclusive OR circuit 43 becomes high level “1”. However, the strobe edge signal S
Even while TRB1 to STRB13 are being output, since the rate signal RATE5 has not been output yet, the flip-flop circuit 4 for detecting a rate output error
5 continuously outputs a low-level "0" rate output error signal. When the rate signal RATE5 is output, the flip-flop circuit 45 for detecting a rate output error latches the high level “1” exclusive OR signal W_EOR output from the exclusive OR circuit 43. , As a rate output error signal ERRW. Thereby, the OR circuits 46 and 4
7 outputs an OR signal ERR indicating an error.

In the above embodiment, N is "1".
Although the case where the timing edge counter circuit 81 and the strobe edge counter circuit 82 have a 5-bit configuration is described in “3”, this numerical value is an example, and when N is “13”, the timing edge counter circuit 81 and the strobe edge circuit It is preferable that the counter circuit 82 has a 4-bit configuration, and when N is "20", it is preferable that the timing edge counter circuit 81 and the strobe edge counter circuit 82 have a 5-bit configuration. However, it goes without saying that these values are arbitrary and may be set as appropriate. In the above-described embodiment, the case where the timing edge signal and the strobe edge signal are counted has been described. However, the rate signal and the strobe edge signal may be counted and the values of the two may be compared.

[0040]

According to the present invention, it is possible to detect whether or not a predetermined number of rate signals and strobe edge signals have been output during a function test. Even if the edge signal is output with a predetermined time delay or is output a predetermined time earlier than the edge signal, the edge defect can be detected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an edge defect detection device of a semiconductor test device according to an embodiment of the present invention.

FIG. 2 is a block diagram schematically showing an overall configuration of a semiconductor test apparatus.

FIG. 3 is a timing chart showing an operation of the edge defect detection device of FIG. 1;

FIG. 4 is a timing chart illustrating an operation of the counter error detector of FIG. 1;

FIG. 5 is a diagram for explaining an error detection operation of the edge defect detection device of FIG. 1;

FIG. 6 is a diagram for explaining an error detection operation of the edge defect detection device of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Rate select circuit 11 ... Strobe edge generation circuit 20 ... Strobe edge select circuit 21-2N, 30, 44, 45 ... Flip-flop circuit 31-3N, 84 ... AND circuit 41, 46, 47 ... OR circuit 42, 43 ... Exclusive OR circuit 81 ... Timing edge counter circuit 82 ... Strobe edge counter circuit 83 ... Comparison circuit

Claims (4)

[Claims] 1. A strobe edge selecting means for inputting a strobe edge signal and outputting first to Nth strobe selection signals in accordance with the input order, and the first strobe edge selecting means output from the strobe edge selecting means.
The first to Nth strobe selection signals are configured to input the strobe selection signal to the enable terminal, the strobe edge signal to the clock terminal in common, and the output of the inverted output terminal to the input terminal. N-th flip-flop circuit means, rate selection means for inputting rate signals and outputting first to N-th rate selection signals in accordance with the input order; Outputting a logical product signal based on the same signal between the signal output from the flip-flop circuit means and the first to Nth rate selection signals output from the rate selection means. A first to an N-th logical product circuit means, and a first logical sum signal based on an output of the first to the N-th logical product circuit means. Logical sum circuit means; rate flip-flop circuit means configured to input the first rate selection signal output from the rate selection means to a clock terminal and input the output of an inverted output terminal to an input terminal; A first exclusive-OR circuit means for outputting an exclusive-OR signal based on a signal output from the first flip-flop circuit means and a signal output from the rate flip-flop circuit means; A rate error detection flip-flop circuit means configured to input the exclusive OR signal output from the first exclusive OR circuit means to an input terminal and to input the strobe edge signal to a clock terminal; And an exclusive OR based on a signal output from the OR circuit and a signal output from the rate flip-flop circuit. A second exclusive-OR circuit means for outputting a signal, an exclusive-OR signal output from the second exclusive-OR circuit means being inputted to an input terminal, and the rate signal being inputted to a clock terminal. And a flip-flop circuit means for detecting a strobe edge error configured as described above. 2. A timing counting means for cyclically counting a timing edge signal as a basis of the strobe edge signal during a function test, and counting the strobe edge signal cyclically during a function test. An edge failure of a semiconductor test apparatus, comprising: a strobe count unit; and a count error detection unit that compares count values of the timing count unit and the strobe count unit at the end of the function test and outputs a result of the comparison. Detection device. 3. The method according to claim 2, wherein the cyclic count values of the timing count means and the strobe count means are constituted by a minimum value including the total number N of the first to N-th flip-flop circuit means. An edge failure detection device for semiconductor test equipment. 4. A timing counting means for cyclically counting a timing edge signal which is a basis of a strobe edge signal during a function test; a strobe counting means for cyclically counting the strobe edge signal during a function test; An edge failure detection device for a semiconductor test device, comprising: count error detection means for comparing the count values of the timing count means and the strobe count means at the end of a test and outputting the comparison result.