JP2001166002A - Boundary scan circuit - Google Patents

Abstract

(57) [Abstract] [Problem] An LSI incorporating a boundary scan circuit
In the case where the reset terminal TRST which is an optional function of the boundary scan is provided, a circuit for controlling the TRST on the substrate is required regardless of the necessity of the reset, and it is unnecessary particularly when the reset is not required. Circuit. In addition, TRS
This may affect the T terminal and cause an unexpected reset to the boundary scan circuit. SOLUTION: An L incorporating a boundary scan circuit is provided.
A detection circuit 5 for detecting that a TAP signal has been input and an arbitration circuit 6 for receiving a TRST if necessary to identify whether or not a boundary scan test is being performed; Accept / prohibit TRST.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a boundary scan circuit incorporated in an LSI (Large Scale Integrated Circuit) or the like.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of an LSI incorporating a conventional boundary scan circuit.

In FIG. 6, 1 is an LSI, 2 is an LSI 1
An internal circuit which functions as a center of the function 3 is a boundary scan cell which is composed of a shift register and a latch, and is disposed at each terminal of the LSI 1, and 4 is an input / output of test data for performing a boundary scan test. A TAP controller 7 is a serial interface for performing TAP signals (TDI, TDO, TC) for controlling the TAP controller 4 from outside the LSI 1.
K, TMS, TRST).

In the boundary scan circuit of the LSI 1 having the above-described components, test data is input by serial input from TDI in synchronization with signals of TCK and TMS, and data of a test result is output from TDO to perform boundary scan test. I do. If necessary, a reset signal is input from TRST to reset the TAP controller.

[0005]

In the above-described conventional boundary scan circuit, when the reset terminal TRST, which is an optional function, is provided in the LSI 1, it is possible to control the TRST on the substrate irrespective of the necessity of resetting. If it is necessary to provide a circuit and it is not necessary to perform a reset from TRST, the circuit becomes an unnecessary circuit. Further, during the boundary scan test, there is a possibility that the TAP controller may be accidentally reset due to noise mixing or the like in the TRST.

The present invention has been made in consideration of the above-mentioned conventional problems, and
Can be permitted / prohibited, and an accidental reset to the TAP controller due to noise contamination can be prevented.
If there is no need to reset from ST, TRST
It is an object of the present invention to provide a boundary scan circuit that does not require a circuit for controlling the boundary scan circuit.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention incorporates a detection circuit incorporated in an LSI for detecting that a TAP signal has been input, and accepts a TRST when necessary. Boundary scan circuit having an arbitration circuit for the purpose.

According to the present invention, it is possible to determine whether or not the boundary scan test is being performed and to accept / prohibit TRST.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a boundary scan circuit incorporated in an LSI, wherein the detection circuit can detect that a TAP signal has been input, A TAP controller and the T
A boundary scan circuit characterized by providing an arbitration circuit for controlling reset to an AP controller, wherein a reset to a TAP controller during a boundary scan test is prohibited, and an accidental reset to the TAP controller due to noise contamination is provided. Is prevented.

According to a second aspect of the present invention, in the boundary scan circuit according to the first aspect, a signal of the TCK pin, which is one of the TAP signals, is observed by a detection circuit, and the voltage level of the TCK pin is reduced. More than any number of times "Hig
This is a boundary scan circuit that prohibits resetting to the TAP controller when detecting that "h" .fwdarw. ". fwdarw." Low "is repeated. Similarly, resetting to the TAP controller during the boundary scan test is prohibited, and TAP due to noise contamination This has the effect that it is possible to prevent accidental reset to the controller.

According to a third aspect of the present invention, in the boundary scan circuit according to the first aspect, the signals of the TCK pin and the TMS pin of the TAP signal are observed by the detection circuit, and the TCK pin is provided an arbitrary number of times. The timing at which the voltage level changes (“High” ← → “Low”) and T
The reset to the TAP controller is prohibited when the timing of the change in the voltage level of the MS pin coincides. Similarly, the reset to the TAP controller during the boundary scan test is prohibited, and the T due to noise mixing is prohibited.
This has an effect that it is possible to prevent an accidental reset to the AP controller.

According to a fourth aspect of the present invention, in the boundary scan circuit according to the first aspect, the arbitration circuit observes and detects the signal of the TRST pin even when the reset to the TAP controller is prohibited. When the signal on the TCK pin is observed in the circuit, and the state of the voltage level on the TRST pin is maintained while the voltage level on the TCK pin has changed more than an arbitrary number of times (“High” ← → “Low”), This cancels the reset prohibition, and has the effect of eliminating the need to provide a circuit for controlling TRST.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an LSI in which a boundary scan circuit of the present invention is incorporated. FIG. 1
In FIG. 6, the same components as those in the conventional example shown in FIG.

As shown in FIG. 1, an LSI 1 in which a boundary scan circuit is incorporated is composed of an internal circuit 2 which plays a central role in the function of the LSI 1, a shift register, a latch, and the like. A boundary scan cell 3, a TAP controller 4, which is a serial interface for inputting and outputting test data for performing a boundary scan test,
A detection circuit 5 for detecting a TAP signal and an arbitration circuit 6 for controlling a reset input to the TAP controller 4 are provided. 7, the TAP controller 4 is an LSI
This is a TAP signal for external control.

(Embodiment 1) FIG. 2 is an explanatory diagram of an inspection environment of an LSI boundary scan test.

Next, referring to FIG. 1 and FIG.
In the case of performing the boundary scan test, the TAP
The signal 7 is connected to the boundary scan inspection machine 8 and the target substrate 9 via the connection cable 10. When an operation for starting an inspection is performed by the boundary scan inspection machine 8, a boundary scan test on the target substrate 9 is started. At the same time, the TAP signal 7 becomes active, and the detection circuit 5 of the LSI 1 detects that the TAP signal 7 has been input, and prohibits the arbitration circuit 6 from accepting the reset.
The reset to the AP controller 4 is prohibited.

(Embodiment 2) FIG. 3 is an explanatory diagram of a "TCK" signal pattern in a boundary scan test.

Next, the boundary scan test will be described with reference to FIGS.

When the detection circuit 5 detects that the TAP signal 7 has been input, the detection circuit 5 detects the TA signal 7 due to the influence of noise and the like.
In some cases, it is determined that the P signal 7 has been input. Therefore, attention is paid to TCK with the largest signal change from the start of the boundary scan inspection, and the change (High ← in voltage level)
If the number of times of (Low) changes by an arbitrary number or more, the arbitration circuit 6 prohibits the reception of the reset.

As shown in FIG. 3, when the boundary scan test is started, TCK repeatedly changes from High to Low. In the detection circuit 5, TCK changes from low to high.
A change is detected to igh, and the number of times is counted. In the example of FIG. 3, the reset is prohibited in the arbitration circuit 6 when the number of times becomes six or more.

(Embodiment 3) FIG. 4 is an explanatory diagram of "TCK" and "TRST" signal patterns in a boundary scan test.

Next, the boundary scan test will be described with reference to FIGS.

To further reduce the effect of noise, T
The reset is prohibited by observing not only the CK but also the TMS signal. As shown in FIG. 4, when the boundary scan test is started, TCK repeatedly changes from High to Low, and after the sixth rising, TMS
Becomes low for one clock. In the detection circuit 5, TCK changes from low to high six times, and TMS changes.
Is once low and then high again, and the arbitration circuit 6 prohibits reception of a reset.

(Embodiment 4) FIG. 5 is an explanatory diagram of "TCK" and "TRST" signal patterns in a boundary scan test.

Next, the boundary scan test will be described with reference to FIGS.

As shown in FIG.
RST is observed, and TCK is observed in the detection circuit 5 from the moment when the signal changes from High to Low, and from Low to Hi.
gh is an arbitrary number (10 in the example of FIG. 5).
At this point, if TRST remains Low, the arbitration circuit 6 releases the reset prohibition,
The TAP controller 4 is reset.

[0028]

As is apparent from the above description, the present invention determines whether or not the boundary scan test is being performed by T.
By identifying the AP signal by observing it, T
Since the reset to the AP controller can be permitted / prohibited, it is possible to prevent an accidental reset to the TAP controller due to noise mixing, and when it is not necessary to perform the reset from the TRST. , TRST need not be provided. Also, even if it is necessary to reset, T
The reset signal can be permitted by monitoring the RST signal, and the effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram in an LSI in which a boundary scan circuit of the present invention is incorporated.

FIG. 2 is an explanatory diagram of an inspection environment of an LSI boundary scan test.

FIG. 3 “TCK” in the boundary scan test
Illustration of signal pattern

FIG. 4 “TCK” in a boundary scan test
And explanatory diagram of "TRST" signal pattern

FIG. 5: “TCK” in the boundary scan test
And explanatory diagram of "TRST" signal pattern

FIG. 6 is a block diagram of an LSI in which a conventional boundary scan circuit is incorporated.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 LSI 2 Internal circuit 3 Boundary scan cell 4 TAP controller 5 Detection circuit 6 Arbitration circuit 7 TAP signal 8 Boundary scan inspection machine 9 Target board 10 Connection cable

Claims (4)

[Claims] 1. A boundary scan circuit incorporated in an LSI, for controlling a detection circuit capable of detecting that a TAP signal has been input, a TAP controller, and resetting the TAP controller. A boundary scan circuit characterized by providing an arbitration circuit of (1). 2. When a signal on the TCK pin, which is one of the TAP signals, is observed by a detection circuit and it is detected that the voltage level of the TCK pin has been repeatedly changed from "High" to "Low" an arbitrary number of times. 2. The boundary scan circuit according to claim 1, wherein reset to the TAP controller is prohibited. 3. A detection circuit observes the signals of the TCK pin and the TMS pin of the TAP signal, and changes the voltage level of the TCK pin an arbitrary number of times ("High" ← → "Lo").
2. The boundary scan circuit according to claim 1, wherein the reset to the TAP controller is prohibited when the timing of w ") coincides with the timing of the change in the voltage level of the TMS pin. 4. Even when reset to the TAP controller is prohibited, the arbitration circuit observes the signal at the TRST pin and the detection circuit observes the signal at the TCK pin, and the state of the voltage level of the TRST pin is TCK. The voltage level of the pin changes more than an arbitrary number of times (“High” ←
2. The boundary scan circuit according to claim 1, wherein reset prohibition is canceled when the state is maintained during "Low".