JP2001160000A - Memory control integrated circuit, memory card, memory device, information processor, clock setting method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem such that the clock phase in the memory with SDRAM has been adjusted in the most suitable timing by adjusting an outer line length and a pattern length. SOLUTION: A system is provided with the feed-back clock 137 and the reading clock 136 in addition to an SDRAM clock 134 for supplying SDRAM DIMM 132 to a clock distributing route 1315. Delay control terminals r1325 and w1326 for adjusting the delay amount of delay circuits A1316 and B1317 are adjusted with respect to the feed-back clock 137 and the reading clock 136 so that arrangement is performed to an optimum position with the minimum external change even in the case of a different frequency. The delay control terminals r1325 and w1326 can be set from the external part and set from another device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an SDRAM DI
The present invention relates to a computer system having an MM and a memory control integrated circuit having a clock adjustment circuit.

[0002]

2. Description of the Related Art At present, systems equipped with SDRAM DIMMs are increasing, and 100 MHz, 133 MHz and S
The speed of DRAM DIMMs is increasing. SDRAM
The clock of the interface part has a clock distributed to the SDRAM and a feedback clock for the PLL.
The feedback clock is adjusted by external line length adjustment and pattern length adjustment, and the clock is adjusted to an optimum timing.

Japanese Patent Application Laid-Open No. 11-167514 "Computer system with a memory control function capable of coping with DRAMs having different operation speeds" includes S operating at different clocks.
To interface a DRAM memory bank with a processor, based on information stored in the DRAM bank,
A computer system having a circuit for setting a clock frequency by a BIOS and synchronizing a processor and a memory is disclosed.

Japanese Patent Application Laid-Open No. 11-135920 “Printed-wiring board and clock skew adjustment method” includes a plurality of clock paths connecting between a clock output circuit and a clock input circuit, each of which is provided after the printed wiring board is designed. A technique of providing a dummy pad for mounting a resistor for adjusting a clock skew is disclosed.

[0005]

With the above method, even if the integrated circuit can operate at different frequencies, the SDRA
Since the clock adjustment of the interface portion of M is performed only outside the integrated circuit, there is a possibility that the printed circuit board cannot be used as it is. In the case of external adjustment, the adjustment is made based on the length of signal wiring or the like. However, it is difficult to accurately adjust the skew (phase) of the clock if the signal crosses between layers.

[0006] Japanese Patent Application Laid-Open No. 11-167514 "Computer system having a memory control function capable of coping with DRAMs having different operation speeds" has a synchronization circuit, so that the performance is reduced due to a synchronization loss.

In Japanese Patent Application Laid-Open No. 11-135920, "Method for Adjusting Printed Wiring Board and Clock Skew", it is necessary to observe a waveform, and the number of steps increases.

[0008]

According to a first aspect of the present invention, there is provided a memory control integrated circuit for inputting a signal from a host device and an input clock to control an SDRAM, wherein the memory control integrated circuit includes: , Memory controller and PLL
And a clock distribution unit. The memory control unit outputs a signal for controlling the SDRAM. The PLL receives the input clock and the feedback clock, and outputs a clock synchronized with the input clock and the feedback clock to the clock distribution unit. The SDRAM clock supplied to the SDRAM and supplied to the SDRAM by the clock distribution unit.
The feedback clock and the SDR
A read clock for latching data from the AM is output.

A second memory control integrated circuit of the present invention is a memory control integrated circuit for controlling a SDRAM by inputting a signal from an upper device and an input clock, wherein the memory control integrated circuit comprises a memory control unit and a PLL. And a clock distribution unit. The memory control unit outputs a signal for controlling the SDRAM. The PLL receives the input clock and the feedback clock, and outputs a clock synchronized with the input clock and the feedback clock to the clock distribution unit. The SDRAM clock supplied to the SDRAM by the clock distribution unit, the feedback clock to be input to the PLL, and the read clock for latching data from the SDRAM are output to the outside of the memory control integrated circuit. Can control the amount of delay by inputting a signal from A delay circuit and a second delay circuit,
The first delay circuit controls the feedback clock to a predetermined amount, and the second delay circuit controls the read clock to a predetermined amount.

[0010] A third memory control integrated circuit of the present invention comprises:
The first or second memory control integrated circuit of the present invention has an operating frequency setting terminal, and selects the performance of a buffer for driving a signal for controlling the SDRAM from the memory control unit by the operating frequency setting terminal. .

[0011] The memory card of the present invention is an SDRAM D
A memory card comprising an IMM and the first, second or third memory control integrated circuit of the present invention.

The first memory device of the present invention comprises a system bus interface unit connected to a central processing unit and an input / output device, an SDRAM DIMM, and the first, second or third memory control integrated circuit of the present invention. A memory device having a memory card.

A second memory device according to the present invention is a memory device comprising a system bus interface unit connected to a central processing unit and an input / output device, an SDRAM DIMM, and a memory control integrated circuit. The circuit receives a signal and an input clock from the central processing unit and the input / output device, has a memory control unit, a PLL, and a clock distribution unit. The memory control unit outputs a signal for controlling the SDRAM, and the PLL is The input clock and the feedback clock are input, and a clock synchronized with the input clock and the feedback clock is supplied to the clock distribution unit.
SDRAM clock supplied to RAM, feedback clock input to PLL, and SDRAM
A first delay circuit and a second delay circuit capable of outputting a read clock for latching data from the memory control circuit and inputting a signal from outside the memory control integrated circuit to control a delay amount; A memory control integrated circuit controls the feedback clock to a predetermined amount by a first delay circuit and controls the read clock to a predetermined amount by the second delay circuit.

According to a first information processing apparatus of the present invention, a central processing unit, an input / output device, and the first memory device of the present invention are connected by a bus.

A first information processing apparatus according to the present invention comprises a central processing unit, an input / output device, and a second memory device according to the present invention. The system bus interface unit can be set to a predetermined value from the central processing unit. And a memory device having a simple setting register and connecting the setting register with the first delay circuit and the second delay circuit.

According to the clock adjusting method of the present invention, a memory control integrated circuit for inputting a signal from an upper device and an input clock to control an SDRAM has a memory control unit, a PLL and a clock distribution unit, and the memory control unit is an SDRAM The PLL receives the input clock and the feedback clock, and supplies a clock synchronized with the input clock and the feedback clock to the clock distribution unit.
M output an SDRAM clock supplied to M, the feedback clock to be input to the PLL, and a read clock for latching data from the SDRAM;
A method of adjusting the feedback clock and the read clock to a memory control integrated circuit having a first delay circuit and a second delay circuit capable of controlling a delay amount by inputting a signal from outside the memory control integrated circuit. A first step of setting a minimum delay in the first delay circuit, a second step of setting a minimum delay in the second delay circuit, and a write / read test to a memory. A third step, a fourth step of storing the value of the delay of the first delay circuit and the second delay circuit at that time if the result of the write / read test to the memory is normal, and a delay time And a sixth step of repeating the third to fifth steps up to the maximum value of the first delay circuit and the second delay circuit. When, having a seventh step of setting a delay time recorded in said fourth step to said second delay circuit and said first delay circuit.

The recording medium of the present invention has recorded thereon a program for executing the first to seventh steps of the clock adjusting method of the present invention.

[0018]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a memory control chip and peripheral connections according to an embodiment of the present invention. The memory control chip 131 includes a memory control unit 1311, an output register driver 1312, an input register 1313, a PL
L1314, clock distribution circuit 1315, delay circuit A1
316, delay circuit B1317, selector 1318, operating frequency setting terminal 1321, read clock input terminal 13
22, input clock terminal 1323, feedback clock input terminal 1324, delay control terminal r1325, delay control terminal w1326, feedback clock PLL terminal 1327, DIMM interface terminal 1328,
Memory bus terminal 1329, read clock terminal 1330
Consists of

The memory control chip 131 is provided for the DIMM 13
2 and the DIMM interface 133. The input clock 138 is received from the oscillator 139, and the read clock 136 and the SDRAM clock 134 are output. The feedback clock 137 is received, and the read clock 136 and the SDRAM clock 134 are adjusted.

The memory control chip 131 has a memory bus 1
1, and a control signal for the memory is generated by the memory control unit 1311. This control signal is transmitted to the DIMM 132 through the DIMM interface 133.
Supplied to The DIMM interface 133 signal is:
A bidirectional signal is driven by the output register driver 1312, and stores data read from the DIMM 132 by the input register 1313 in synchronization with the read clock 136. The basic operating frequency is determined by the operating frequency setting terminal 1321, and the output register driver 1
Switch 312.

The input clock 138 is input to the PLL 1314, and is supplied to the DIMM 1 by the clock distribution circuit 1315.
32 to SDRAM clock 134, delay circuit A131
6 and the delay circuit B1317. PLL1314
Is the feedback clock 137 and the input clock 13
8 to the clock distribution circuit 1315.

The PLL 1314 receives the input clock 138 and the feedback clock 137. The phase difference between the input clock 138 and the feedback clock 137 is detected, and control is performed so that the phase difference is eliminated, that is, the input clock 138 and the feedback clock 137 are synchronized.

The delay circuit A1316 has a delay control terminal r
There are 1325 inputs and the delay can be adjusted. Delay circuit A1
316 receives the clock signal from the clock distribution circuit 1315, and the output of the delay circuit A1316 becomes the read clock 136. The delay circuit B1317 also has a delay control terminal w1326, and the delay amount can be adjusted. Delay circuit B
1317 receives the clock signal from the clock distribution circuit 1315, and the output of the delay circuit B1317 becomes the feedback clock 137. The read clock 136 is
Read clock input terminal 13 of memory control chip 131
22, the feedback clock 137 is supplied to the PLL 1314 through the feedback clock input terminal 1324.
And used for phase adjustment of the SDRAM clock 134.

Next, the operation of the read clock 136 will be described. FIG. 2 is a block diagram showing connection of a read clock of the memory control chip 131 according to the embodiment of the present invention.

The read clock 136 is used for reading data output from the DIMM 132. DIMM1
32, the timing of outputting data may vary depending on the type (capacity, vendor, etc.), and the memory control chip 131 adjusts the timing of receiving data at the time of reading so that a margin including the deviation can be secured. In FIG. 2, data is output at the rising edge of the SDRAM clock 134. However, since the output delay of the data and the load capacity of the DIMM 132 are different, the DIMM is output.
The time to reach 132 is different.

Input clock 1 of the memory control chip 131
38 and the SDRAM clock 134 are fixed at the same phase, the data received by the memory control chip 131 may fluctuate due to the delay, but the phase cannot be adjusted by the input clock 138 of the memory control chip 131. If the setup time and the hold time of the input register 1313 cannot be satisfied, data corruption occurs. In order to cope with this, in the present invention, by providing the read clock 136, the read clock 136 is set to the DIM even if the delay changes before and after the data.
Considering the delay of the M interface 133, the delay circuit A
The timing of the input register 1313 is optimally adjusted by adjusting the phase of the read clock 136 and the SDRAM clock 134 by 1316.

Next, the setting of the operating frequency will be described.
FIG. 3 is a block diagram showing selection of a driver when setting an operating frequency in the memory control chip 131 according to the embodiment of the present invention. The operating frequency setting terminal 1321 is a terminal for switching the output register driver 1312 of the DIMM interface 133 according to the operating frequency. When the frequency is high, the operation is switched to the high-speed buffer 1312b, and when the frequency is low, the operation is switched to the normal buffer 1312a. When switching by hardware, the operating frequency setting terminal 132
When the input of 1 is high, a normal buffer (eg, 100 MHz
z) and a low-speed buffer (eg 133 MHz)
z) is switched.

Next, in the memory control chip 131 of the present invention, the SDRAM clock 134,
Read clock 136, feedback clock 137
A method of adjusting the delay amount between the two will be described. FIG.
FIG. 14 is a diagram illustrating settings of a delay control terminal r1325 and a delay control terminal w1326 when setting an operating frequency in the memory control chip 131 according to the embodiment of the present invention. The delay control terminal r1325 and the delay control terminal w1326 are externally PUL
Set with L UP (high) and PULL DOWN (low) to adjust the delay time. It is included in the read clock 136 and the feedback clock 137, respectively. In the case of the table of FIG. 4, 16 adjustments are possible at 0.5 ns (500 ps) intervals.

Next, the operation of the memory control chip 131 of the present invention will be described with reference to FIGS. FIG. 5 is a timing chart showing a clock when setting the operating frequency in the memory control chip 131 according to the embodiment of the present invention. The memory control chip 131 receives a signal of the memory bus 11 to generate a DIMM interface 133,
The clock 134 is distributed. Memory control chip 131
Receives the input clock 138 and first enters the clock distribution circuit 1315 through the PLL 1314. SDRAM clock 134 from clock distribution circuit 1315, read clock 136 and delay circuit B through delay circuit A1316
It is distributed to a feedback clock 137 through 1317. The delay circuit A1316 of the read clock 136 has a delay control terminal r1325 input terminal, and the delay amount can be set, and the delay amount is adjusted in the + and-directions from the reference value (default). Delay circuit A131
The read clock 136, which is the output of No. 6, is connected to a read clock input terminal 1322, and adjusts the clock phase to an optimum position for loading data read from the DIMM 132 into the input register 1313. The delay circuit B1317 of the feedback clock 137 also has a delay control terminal w1326 input and can set the delay amount, and adjusts the delay amount in the + and-directions from the reference value (default). The feedback clock 137 output from the delay circuit B1317 is connected to the PLL 1314 through the feedback clock input terminal 1324 to adjust the timing.

FIG. 6 is a block diagram showing the configuration of the memory card 13 and the memory device 1 having the memory control chip 131 according to the embodiment of the present invention. The memory card 13 includes a memory control chip 131, an oscillator 139, and a DIMM.
132. The memory card 13 is connected to the system interface 12 via the memory bus 11. The system interface 12 is connected to the bus 4 by a bus bridge 122 and processes a memory request from another device.

The system interface 12 has a setting register 121. The output of the setting register 121 is connected to a delay control terminal r1325, a delay control terminal w1327, and an operating frequency setting terminal 1321 of the memory control chip 131, and these settings are made. . The setting register 121 can be set from another device via the bus 4.

FIG. 7 is a block diagram showing the configuration of the information processing apparatus according to the embodiment of the present invention.

The central processing unit 2, the input / output device 3, and the memory device 1 are connected via a system bus 2. The central processing unit 2 performs a test of the memory device 1 at startup, performs a memory read / write test, and sets the setting register 121 so that reading / writing can be performed normally. The instruction to perform the memory read / write test is sent to the central processing unit 2
Is stored in the ROM 201.

FIG. 8 is a flowchart showing the operation of the method for setting the read clock and the feedback clock in the information processing apparatus according to the embodiment of the present invention. A delay time of -3.5 ns is set to the delay control terminal r (step A
1). A delay time of -3.5 nS is set to the delay control terminal w (step A2). A write / read test to the memory is performed (Step A3). If the result of the write / read test to the memory is normal, the values of the delay control terminals r and w at that time are stored. (Steps A4 and A
5). Increase the delay time by +0.5 nS (step A
6), and execute steps A1 to A5 (step A)
7). An intermediate value between the maximum value and the minimum value of the delay control terminal r and the delay control terminal w recorded in step A6 is set in the setting register 121 for the delay control terminal r and the delay control terminal w.

Each of the steps A1 to A8 can be executed by a combination of instructions of the central processing unit. A combination of instructions, that is, a program is stored in the ROM 201 in the central processing unit 2.

[0037]

As described above, by using the memory control chip 131, it is possible to adjust the read clock and the feedback clock of the SDRAM DIMM so that the clock phase can be adjusted to the optimum clock phase without changing the external (substrate). is there.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory control chip and peripheral connections according to an embodiment of the present invention.

FIG. 2 is a block diagram showing connection of a read clock of the memory control chip according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating selection of a driver when setting an operating frequency in the memory control chip according to the embodiment of the present invention;

FIG. 4 is a diagram illustrating setting of an operation clock input terminal when setting an operation frequency in the memory control chip according to the embodiment of the present invention;

FIG. 5 is a timing chart showing a clock when setting an operating frequency in the memory control chip according to the embodiment of the present invention;

FIG. 6 is a block diagram illustrating a configuration of a memory card and a memory device having a memory control chip according to an embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 8 is a flowchart showing an operation of a method for setting a read clock and a feedback clock in the information processing apparatus according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 memory device 2 central processing unit 3 input / output device 4 bus 11 memory bus 12 system interface 13 memory card 121 setting register 122 bus bridge 131 memory control chip 132 DIMM 133 DIMM interface 134 SDRAM clock 136 read clock 137 feedback clock 138 input clock 139 Oscillator 201 ROM 1311 Memory controller 1312 Output register driver 1313 Input register 1314 PLL 1315 Clock distribution circuit 1316 Delay circuit A 1317 Delay circuit B 1318 Selector 1321 Operating frequency setting terminal 1322 Read clock input terminal 1323 Input clock terminal 1324 Feedback clock input terminal 1325 Delay control terminal r 1326 Extended control terminal w 1327 feedback clock PLL terminal 1328 DIMM interface terminal 1329 memory bus terminal 1330 read clock terminal 1312a usually buffer 1312b high-speed buffer

Claims (10)

[Claims] 1. A memory control integrated circuit that receives a signal from an upper device and an input clock and controls an SDRAM, the memory control integrated circuit having a memory control unit, a PLL, and a clock distribution unit, The section outputs a signal for controlling the SDRAM, the PLL receives the input clock and the feedback clock, and supplies a clock synchronized with the input clock and the feedback clock to the clock distribution section. SD
SDRAM clock supplied to RAM, feedback clock input to PLL, and SDRAM
A memory control integrated circuit for outputting a read clock for latching data from a memory. 2. A memory control integrated circuit for inputting a signal from an upper device and an input clock to control an SDRAM, the memory control integrated circuit having a memory control unit, a PLL, and a clock distribution unit, The section outputs a signal for controlling the SDRAM, the PLL receives the input clock and the feedback clock, and supplies a clock synchronized with the input clock and the feedback clock to the clock distribution section. SD
SDRAM clock supplied to RAM, feedback clock input to PLL, and SDRAM
A first delay circuit and a second delay circuit capable of outputting a read clock for latching data from the memory control circuit and inputting a signal from outside the memory control integrated circuit to control a delay amount; A memory control integrated circuit, wherein the first delay circuit controls the feedback clock to a predetermined amount, and the second delay circuit controls the read clock to a predetermined amount. 3. An SDRAM having an operating frequency setting terminal, wherein the operating frequency setting terminal allows the memory control unit to control the SDRAM.
3. The memory control integrated circuit according to claim 1, wherein a performance of a buffer for driving a signal for controlling the signal is selected. 4. A memory card comprising an SDRAM DIMM and the memory control integrated circuit according to claim 1. 5. A system bus interface unit for connecting to a central processing unit and an input / output device, and an SDRAM DIM.
A memory device comprising a memory card comprising M and the memory control integrated circuit according to claim 1. 6. A system bus interface for connecting to a central processing unit and an input / output device, and an SDRAM DI
A memory device comprising an MM and a memory control integrated circuit, wherein the memory control integrated circuit inputs signals and an input clock from the central processing unit and the input / output device, and distributes a memory control unit, a PLL, and a clock. A memory controller outputs a signal for controlling the SDRAM, the PLL inputs the input clock and the feedback clock, and supplies a clock synchronized with the input clock and the feedback clock to the clock distributor. The clock distribution unit outputs an SDRAM clock supplied to the SDRAM, the feedback clock input to the PLL, and a read clock for latching data from the SDRAM, and outputs a signal from outside the memory control integrated circuit. The first delay circuit that can input and control the amount of delay And having a second delay circuit, the feedback clock is controlled to a predetermined amount by the first delay circuit,
A memory device comprising a memory control integrated circuit that controls the read clock to a predetermined amount by the second delay circuit. 7. An information processing apparatus wherein a central processing unit, an input / output device, and the memory device according to claim 5 are connected by a bus. 8. A system comprising a central processing unit, an input / output device, and a memory device according to claim 6, wherein said system bus interface unit has a setting register which can be set to a predetermined value from said central processing unit. An information processing apparatus, wherein a register and a memory device connecting the first delay circuit and the second delay circuit are connected by a bus. 9. A memory control integrated circuit that receives a signal from a higher-level device and an input clock and controls an SDRAM has a memory control unit, a PLL, and a clock distribution unit, and the memory control unit outputs a signal that controls the SDRAM. And the PLL inputs the input clock and the feedback clock,
A clock synchronized with the input clock and the feedback clock is supplied to the clock distribution unit, and the clock distribution unit latches the SDRAM clock supplied to the SDRAM, the feedback clock input to the PLL, and data from the SDRAM. A read clock for performing the above operation, and a feedback signal to a memory control integrated circuit having a first delay circuit and a second delay circuit capable of inputting a signal from outside the memory control integrated circuit and controlling a delay amount. A method of adjusting a clock and the read clock, wherein a first step of setting a minimum delay in the first delay circuit, and a second step of setting a minimum delay in the second delay circuit A third step of performing a write / read test on a memory; A fourth step of storing the value of the first delay circuit and the second delay circuit if the result is normal, and a fifth step of increasing the delay time by a predetermined value. And a sixth step of repeating the third to fifth steps up to the maximum value of the first delay circuit and the second delay circuit, and the delay time recorded in the fourth step is the first delay And a seventh step of setting the second delay circuit and a circuit. 10. A recording medium recording a program for executing the first to seventh steps.