JP2001155429A - Automatic equalizing circuit and reproducing apparatus using the same - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide an automatic equalization circuit which prevents tap coefficients from diverging or delaying convergence of tap coefficients, and a reproducing apparatus using the same. A transversal filter having an even number (2 × n) taps, an error calculation circuit for determining a sign of a digital information signal from a signal after equalization, and calculating a value corresponding to an amplitude error based on the code, A reproduction signal is directly converted into a PR (1, 0, -1) signal by using an automatic equalizing circuit 8 including an output signal of an arithmetic circuit and a tap coefficient updating circuit for updating a tap coefficient from an output signal of each tap. And supply it to the decoding circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic equalizing circuit for digital information signals and a reproducing apparatus for a recording medium using the same, and more particularly to an automatic equalizing circuit suitable for reproducing using a partial response detection system. And a reproducing apparatus using the same.

[0002]

2. Description of the Related Art Partial response class IV (PR
FIG. 11 shows a conventional reproducing apparatus using the 4) method. The signal reproduced from the magnetic recording medium 1 by the magnetic head 2 is
The signal is amplified to a predetermined level by the reproduction amplifier 3, the high-frequency noise component is removed by the low-pass filter 4, converted to a digital signal by the AD conversion circuit 5, and an odd number (2 × n−1: n is an integer of 2 or more) ) The partial response PR (1, −−) is obtained by the automatic equalization circuit 6 using a transversal filter having taps.
1) Equalized to a signal. And this PR (1, -1)
The equalized signal is converted into a partial response PR (1, 0, -1) signal by a (1 + D) circuit 7 at the subsequent stage, and is decoded by a Viterbi decoding circuit 9. That is, the conventional automatic equalizing circuit is configured to only equalize the reproduced signal to the PR (1, -1) signal.

[0003] Incidentally, those related to this kind of automatic equalizing circuit include, for example, Japanese Patent Application Laid-Open No. 10-134513,
JP-A-10-269701, JP-A-10-275422, and JP-A-10-275423.

[0004]

However, in the above-mentioned conventional automatic equalizing circuit, tapping is performed in a state where the signal-to-noise ratio (SN ratio) of the equalized PR (1, -1) signal is small and there are many code errors. Since the coefficients are updated, the tap coefficients diverge or the convergence of the tap coefficients slows down.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide an automatic equalizing circuit which prevents tap coefficients from diverging or delaying the convergence of tap coefficients, and a reproducing apparatus using the same. To provide.

[0006]

In order to achieve the above object, an automatic equalizing circuit according to the present invention discriminates the sign of a digital information signal from a 2 × n tap transversal filter and an equalized signal. , An error calculation circuit for calculating a value corresponding to an amplitude error based thereon, and a tap coefficient update circuit for updating a tap coefficient from an output signal of the error calculation circuit and an output signal of each tap. The signal is equalized to a partial response signal, and the output signal is directly supplied to a decoding circuit.

A second automatic equalizing circuit according to the present invention determines the sign of a digital information signal from a transversal filter having 2 × n + 1 taps and an equalized signal, and responds to an amplitude error based on the signal. An error calculation circuit for calculating a value, and a tap coefficient update circuit for updating a tap coefficient from an output signal of the error calculation circuit and an output signal of each tap, and equalizes a transmitted digital information signal to a partial response signal. , And supplies the output signal directly to the decoding circuit.

Further, the reproducing apparatus according to the present invention comprises: reproducing means for reproducing a digital information signal recorded on a magnetic recording medium; an equalizing circuit for equalizing the reproduced digital information signal; And a decoding circuit for decoding the digital information signal. The equalization circuit determines a sign of the digital information signal from a 2 × n tap transversal filter and a signal after the equalization, and determines a value corresponding to an amplitude error based on the digital information signal. , And a tap coefficient update circuit that updates a tap coefficient from an output signal of the error operation circuit and an output signal of each tap, and transmits the transmitted digital information signal to the partial response PR (1, 0). , -1) signal, and the output signal is directly supplied to the decoding circuit. Alternatively, the equalizer circuit in the playback device has 2
A transversal filter having × n + 1 taps is provided to equalize the transmitted digital information signal to a partial response PR (1, 1, −1, −1) signal.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a reproducing apparatus using an automatic equalizing circuit according to the present invention, and 8 shows an automatic equalizing circuit according to the present invention. In addition, the same reference numerals as those in FIG. As described above, this embodiment is characterized in that the reproduced signal is directly equalized to the PR (1, 0, -1) signal using the transversal filter having an even number (2 × n) taps. .

The PR (1, 0, -1) signal is PR (1, 0, -1).
-1) The SN ratio can be greatly improved as compared with the signal, and code errors can be reduced. Therefore, in the automatic equalization circuit according to the present invention, it is possible to update the tap coefficients in a state where the number of code errors is small, and as a result, it is possible to prevent a problem that the tap coefficients diverge or the tap coefficients converge slowly. can do.

In the automatic equalizing circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 10-134513, the code error rate is improved by using the maximum likelihood detection method. However, rather than the effect of improving the bit error rate using this maximum likelihood detection method, S
Needless to say, the effect of improving the bit error rate based on the improvement of the N ratio is greater. In particular, when the SN ratio of the reproduced signal itself is poor, the effect of improving the bit error rate using the maximum likelihood detection method decreases, whereas the effect of improving the bit error rate based on the improvement of the SN ratio remains unchanged. .

Hereinafter, an embodiment of the automatic equalizing circuit according to the present invention will be described in detail with reference to FIG. In this embodiment, 6 (n =
3) An example of a tap is shown. In FIG. 2, 11-1
5 is a delay circuit, 21 to 26 are multiplication circuits, 30 is an addition circuit, 41 is a sign discrimination circuit, 42 is a subtraction circuit, 43 is a multiplication circuit, 51 to 56 are multiplication circuits, and 61 to 66 are LPFs.

The transversal filter comprises delay circuits 11 to 15, multiplier circuits 21 to 26, and an adder circuit 30. The equalization input signal and the output signals of the delay circuits 11 to 15 are respectively multiplied by the multiplier circuits 21 to 26. Weighting is performed, and an addition circuit 30 adds and combines them to output an equalized output signal YDT.

The sign discriminating circuit 41 outputs the equalized output signal YDT
Is compared with a threshold level based on the reference value A to output a ternary code discrimination signal ZDT. FIG. 3 shows the input / output relationship. The range of -Am to Am in the figure is the full scale range of the AD conversion circuit 5. Next, the subtraction circuit 42 calculates the sign discrimination signal Z from the equalized output signal YDT.
By subtracting DT, an equalization error signal EDT is output. Then, the multiplication circuit 43 multiplies the equalization error signal EDT by a predetermined coefficient −Δ to output an error signal ERR.
The error calculation circuit includes the sign determination circuit 41 and the subtraction circuit 4
2 and a multiplication circuit 43, and performs an operation according to the following equation.

ERR = −Δ × (YDT−ZDT) = Δ ×
(ZDT-YDT) As is clear from the above equation, the predetermined coefficient may be set to a positive value Δ, and the equalized output signal YDT may be subtracted from the sign determination signal ZDT.

The coefficient Δ must be set to a value smaller than 1. This is because if the control of updating the tap coefficients is performed directly from the equalization error signal EDT, the variation of the tap coefficients becomes too large and the control system becomes unstable, and the tap coefficients diverge or the convergence of the tap coefficients is slow. This is because there is a problem.

The tap coefficient updating circuit includes multiplication circuits 51 to 5
6 and the LPFs 61 to 66, the error signal ERR is multiplied by the equalization input signal and the output signals of the delay circuits 11 to 15 by the multiplication circuits 51 to 56, respectively.
Each is integrated by 61 to 66, and tap coefficients are output to the multiplication circuits 21 to 26 of the transversal filter. With the above operation, the tap coefficient is automatically updated,
It is equalized to a target PR (1, 0, -1) signal.

FIG. 4 is a block diagram showing an example of the LPF 63. The same applies to the other LPFs 61, 62, 64-66.
First, during normal operation, the multiplication value XP3 (XD3 × ER
R) is weighted by the coefficient Δ3 by the multiplication circuit 631 and integrated by the addition circuit 632 and the delay circuit 633 to output a tap coefficient update value CD3. The coefficient Δ3 is a value smaller than 1 like the coefficient Δ. Next, the output value CC3 of the adding circuit 632 is in the range of the limit value CL3 (CL3L to be described later).
When the value exceeds the range (CL3U range), the comparison circuit 634 controls the switching circuit 635 to stop the tap coefficient update operation.
That is, the previous value is output as the tap coefficient update value CD3. Then, in response to an external reset signal RST, the switching circuit 636 selects the initial value CA3,
And outputs the initial value CA3 as the tap coefficient update value CD3.

FIG. 5 is a diagram showing an example of a limited range of tap coefficients and an initial value. The coefficient CD3 of the n-th tap (n = 3 in this embodiment) which is the center tap is, for example, 0.
The range is limited to 5 to 2 (CL3L = 0.5, CL3U = 2), and the initial value CA3 is set to 1. Here, the limit value C
The reason that L3L is set to 0.5 is that if the tap coefficient CD3 falls below this value, the equalized output signal YDT becomes lower than the threshold level, and the code discrimination signal ZDT outputs only "0". This is because there is a possibility that the values may converge. The (n + 1) th tap coefficient CD4 is the same as the (n) th tap coefficient CD3, and incorporates the function of the (1 + D) circuit 7 of the conventional example shown in FIG.

The (n-1) th tap coefficient CD2 and the nth
The + 2nd tap coefficient CD5 is, for example, −
2 to 0 (CL2L = -2, CL2U = 0, CL5L =-
2, CL5U = 0), and the initial values CA2 and CA5 are set to -0.5. Here, the limit value CL2U
And CL5U are set to 0 because the tap coefficients CD2 and CD5 cannot be positive values due to the property of equalizing the reproduced signal, that is, the property of correcting the high-frequency characteristics.

The (n-2) th tap coefficient CD1 and the nth
The + 3rd tap coefficient CD6 is, for example, −
0.5 to 0.5 (CL1L = -0.5, CL1U = 0.
5, CL6L = -0.5, CL6U = 0.5), and the initial values CA1 and CA6 are set to 0.

As described above, by limiting each tap coefficient to a predetermined range, for example, there is an effect that it is possible to prevent the tap coefficient from diverging due to excessive noise or the like mixed in the reproduced signal.

Also, by resetting each tap coefficient to a predetermined value as needed by the reset signal RST, even when the reproduced signal is input in a burst state and the non-input state continues for a long time, the re-convergence can be achieved. There is an effect that the speed can be increased. For example, when a plurality of magnetic heads 2 are mounted on a rotating drum and these magnetic heads are switched and reproduced, a reset signal RST may be provided each time the switching is performed, and each tap coefficient may be initialized.

In the above embodiment, CA3 = CA4, CA2 = CA5, CA1 = CA as initial values of tap coefficients.
Although a left-right symmetric example of 6 is shown, the present invention is not limited to this. For example, if the reproduced signal has phase distortion, CA3 @ CA4, CA2 @ CA5, CA1 @ CA
6 may be asymmetric.

FIG. 6 is a block diagram showing another embodiment of the reproducing apparatus using the automatic equalizing circuit according to the present invention. 1a is an optical disk medium, 2a is an optical pickup composed of a laser, an optical lens, etc., 9a is a Viterbi decoding circuit, and the same reference numerals as those in FIG. The feature of the present embodiment lies in that the reproduced signal from the optical disk medium 1a is directly equalized to the partial response PR (1, 1) signal. The Viterbi decoding circuit 9a is a decoding circuit for the PR (1,1) signal.

In this embodiment, each time the optical pickup 2a performs a track jump, a reset signal RST may be given to initialize each tap coefficient.

As described above, the automatic equalization circuit according to the present invention converts the reproduction signal from the magnetic recording medium 1 into PR (1,0,-
1) The present invention can be applied not only to equalizing a signal but also to equalizing a reproduction signal from the optical disk medium 1a to a PR (1, 1) signal.

FIG. 7 is a block diagram showing still another embodiment of the reproducing apparatus using the automatic equalizing circuit according to the present invention. 8
a is an automatic equalizing circuit of the present invention having a 2 × n + 1 tap configuration, 9b is a Viterbi decoding circuit, and the same reference numerals as those in FIG. 1 denote the same components. The feature of this embodiment is that the reproduced signal from the magnetic recording medium 1 is directly equalized to a PR (1, 1, -1, -1) signal. Viterbi decoding circuit 9b
Is a decoding circuit for the PR (1, 1, -1, -1) signal.

This PR (1, 1, -1, -1) signal system is called a so-called extended PR4 system, and has a higher S than the PR4 system.
It is known as a method having an excellent N ratio. Therefore, in the present embodiment, it is possible to update the tap coefficients in a state with less code errors, and it is possible to improve the effect of preventing the tap coefficients from diverging or delaying the convergence of the tap coefficients. it can.

FIG. 8 is a diagram showing the input / output relationship of the code discriminating circuit 41 used in the automatic equalizing circuit 8a. As described above, in the extended PR4 method, quinary determination is performed.

FIG. 9 is a diagram showing an example of a limited range of tap coefficients and an initial value in the automatic equalizing circuit 8a. The n-th (n = 3 in this embodiment) tap coefficient CD3, the n + th tap coefficient
For the first tap coefficient CD4 and the (n + 2) th tap coefficient CD5, initial values CA3, CA4, and CA5 are set so as to have the function of (1 + D) 2, and are limited to positive coefficient values. The (n-1) th tap coefficient CD2 and the (n +) th tap coefficient
For the third tap coefficient CD6, initial values CA2 and CA6 are set so as to have predetermined equalization characteristics, and are limited to negative coefficient values.

FIG. 10 is a block diagram showing still another embodiment of the reproducing apparatus using the automatic equalizing circuit according to the present invention.
This embodiment is characterized in that a reproduced signal from the optical disk medium 1a is directly equalized to a partial response PR (1, 2, 1) signal. The Viterbi decoding circuit 9c is a decoding circuit for the PR (1, 2, 1) signal.

As described above, the automatic equalizing circuit according to the present invention not only equalizes the reproduced signal from the recording medium to the PR (1, 0, -1) signal or the PR (1, 1) signal, but also
R (1,1, -1, -1) signal or PR (1,1,2,1)
1) The present invention can be applied to the case of equalizing a signal.

[0035]

As described above, according to the present invention, since the reproduced signal is directly equalized to a predetermined partial response signal, the tap coefficient is updated in a state where the SN ratio of the equalized signal is large and the code error is small. As a result, it is possible to prevent the tap coefficients from diverging or from slowing down the convergence of the tap coefficients. Also, by initializing each tap coefficient at any time and limiting its update range,
The effect of preventing tap coefficients from diverging or delaying convergence of tap coefficients can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a reproducing apparatus using an automatic equalizing circuit according to the present invention.

FIG. 2 is a configuration diagram showing an embodiment of an automatic equalization circuit according to the present invention.

FIG. 3 is a diagram illustrating an example of an input / output relationship of a code determination circuit 41.

FIG. 4 is a configuration diagram illustrating an example of an LPF 63;

FIG. 5 is a diagram illustrating an example of a limited range of a tap coefficient and an initial value.

FIG. 6 is a block diagram showing another embodiment of a reproducing apparatus using the automatic equalizing circuit according to the present invention.

FIG. 7 is a block diagram showing another embodiment of the reproducing apparatus using the automatic equalizing circuit according to the present invention.

FIG. 8 is a diagram showing another example of the input / output relationship of the code discrimination circuit 41.

FIG. 9 is a diagram illustrating another example of a limited range of tap coefficients and an initial value.

FIG. 10 is a block diagram showing another embodiment of the reproducing apparatus using the automatic equalizing circuit according to the present invention.

FIG. 11 is a configuration diagram showing an example of a reproducing apparatus using a conventional automatic equalizing circuit.

[Explanation of symbols]

8, 8a: automatic equalizing circuit, 11 to 15: delay circuit, 21
26 to a multiplication circuit, 30 to an addition circuit, 41 to a sign discrimination circuit, 42 to a subtraction circuit, 43 to a multiplication circuit, 51 to 56 to a multiplication circuit, 61 to 66 to an LPF.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H04B 3/06 H04B 3/06 C

Claims (16)

[Claims] An automatic equalization circuit connected to a decoding circuit, comprising: 2 × n (n is an integer of 2 or more) taps each having a predetermined tap coefficient; A transversal type filter for equalizing, an error calculating circuit for determining a sign of the digital information signal output from the transversal type filter, and calculating a value corresponding to an amplitude error based thereon, and an output of the error calculating circuit. A tap coefficient updating circuit for updating the respective tap coefficients from a signal and an output signal of each of the 2 × n taps, equalizing the transmitted digital information signal to a partial response signal, and outputting the same. An automatic equalizing circuit for supplying a signal directly to the decoding circuit. 2. The automatic equalizing circuit according to claim 1, further comprising a tap coefficient initializing circuit for initializing each of said 2 × n tap coefficients to a predetermined coefficient value. 3. The automatic equalizing circuit according to claim 2, further comprising a tap coefficient limiting circuit for limiting the n-th and (n + 1) -th tap coefficients to a value equal to or greater than the first coefficient value. 4. The automatic equalization circuit according to claim 3, wherein said tap coefficient limiting circuit further limits the (n-1) th and (n + 2) th tap coefficients to be equal to or less than a second coefficient value. . 5. The automatic tap coefficient limiting circuit according to claim 4, wherein the tap coefficient limiting circuit further limits the absolute values of the (n−2) -th and (n + 3) -th tap coefficients to a third coefficient value or less. Equalization circuit. 6. An automatic equalization circuit connected to a decoding circuit, comprising: 2 × n + 1 (n is an integer of 2 or more) taps each having a predetermined tap coefficient; A transversal type filter for equalizing, an error calculating circuit for determining a sign of the digital information signal output from the transversal type filter, and calculating a value corresponding to an amplitude error based thereon, and an output of the error calculating circuit. A tap coefficient update circuit for updating the respective tap coefficients from a signal and an output signal of each of the 2 × n + 1 taps, equalizing the transmitted digital information signal to a partial response signal, and outputting the same. An automatic equalizing circuit for supplying a signal directly to the decoding circuit. 7. The automatic equalization circuit according to claim 6, further comprising a tap coefficient initialization circuit for initializing each of said 2 × n + 1 tap coefficients to a predetermined coefficient value. 8. The method according to claim 7, wherein the (n + 1) th tap coefficient is equal to or larger than the first coefficient value, and
An automatic equalization circuit, comprising: a tap coefficient limiting circuit for limiting each of the (t) th and (n + 2) th tap coefficients to a value equal to or greater than a second coefficient value. 9. The automatic equalizing circuit according to claim 8, wherein said tap coefficient limiting circuit further limits the (n−1) -th and (n + 3) -th tap coefficients to a third coefficient value or less. . 10. The automatic tap coefficient limiting circuit according to claim 9, wherein the tap coefficient limiting circuit further limits the absolute values of the (n−2) -th and (n + 4) -th tap coefficients to be equal to or less than a fourth coefficient value. Equalization circuit. 11. A reproducing means for reproducing a digital information signal recorded on a magnetic recording medium, an equalizing circuit for equalizing the reproduced digital information signal, and a decoding circuit for decoding the equalized digital information signal. Wherein the equalization circuit has 2 × n (n is an integer of 2 or more) taps each having a predetermined tap coefficient, and is a transversal type for equalizing the reproduced digital information signal. A filter; an error calculation circuit that determines a sign of the digital information signal output from the transversal filter and calculates a value corresponding to an amplitude error based on the code; and an output signal of the error calculation circuit and the 2 × n And a tap coefficient update circuit for updating the respective tap coefficients from the output signals of the respective taps, wherein the reproduced digital information signal is transmitted Le Response PR (1, 0, -1) equalization to the signal, the reproduction apparatus characterized by directly supplied to said decoding circuit its output signal. 12. A reproducing means for reproducing a digital information signal recorded on an optical disk medium, an equalizing circuit for equalizing the reproduced digital information signal, and a decoding circuit for decoding the equalized digital information signal. A transversal filter for equalizing the reproduced digital information signal, wherein the equalization circuit has 2 × n (n is an integer of 2 or more) taps each having a predetermined tap coefficient. An error calculating circuit that determines the sign of the digital information signal output from the transversal filter, and calculates a value corresponding to the amplitude error based on the code; and an output signal of the error calculating circuit and the 2 × n A tap coefficient updating circuit for updating the respective tap coefficients from output signals of the respective taps; Reproducing apparatus equalizes the catcher Le response PR (1, 1) signal, and supplying directly the decoding circuit its output signal. 13. The equalization circuit according to claim 11, further comprising a tap coefficient initialization circuit for initializing each of the 2 × n tap coefficients to a predetermined coefficient value, and scanning by the reproduction unit. A reproducing apparatus wherein the tap coefficient initialization circuit is operated every time a track is changed. 14. A reproducing means for reproducing a digital information signal recorded on a magnetic recording medium, an equalizing circuit for equalizing the reproduced digital information signal, and a decoding circuit for decoding the equalized digital information signal. Wherein the equalization circuit has 2 × n + 1 (n is an integer of 2 or more) taps each having a predetermined tap coefficient, and is a transversal type for equalizing the reproduced digital information signal. A filter, an error calculation circuit that determines the sign of the digital information signal output from the transversal type filter, and calculates a value corresponding to an amplitude error based on the signal; an output signal of the error calculation circuit and the 2 × n + 1 A tap coefficient update circuit for updating the respective tap coefficients from the output signals of the respective taps, wherein the reproduced digital information signal Partial response PR (1,1, -1, -1) equalization to the signal, the reproduction apparatus characterized by directly supplied to said decoding circuit its output signal. 15. A reproducing means for reproducing a digital information signal recorded on an optical disk medium, an equalizing circuit for equalizing the reproduced digital information signal, and a decoding circuit for decoding the equalized digital information signal. A transversal filter for equalizing the reproduced digital information signal, wherein the equalization circuit has 2 × n + 1 (n is an integer of 2 or more) taps each having a predetermined tap coefficient. An error calculation circuit that determines the sign of the digital information signal output from the transversal filter, and calculates a value corresponding to an amplitude error based on the code; and an output signal of the error calculation circuit and the 2 × n + 1 A tap coefficient updating circuit for updating the respective tap coefficients from an output signal of each tap, wherein the reproduced digital information signal is provided. The equalizing the partial response PR (1,2,1) signal, reproducing apparatus and supplying directly the decoding circuit its output signal. 16. The equalizing circuit according to claim 14, further comprising a tap coefficient initializing circuit for initializing each of said 2 × n + 1 tap coefficients to a predetermined coefficient value, wherein said reproducing means scans. A reproducing apparatus wherein the tap coefficient initialization circuit is operated every time a track is changed.