JP2001154860A - Memory managing method for operating system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the memory managing method of an operating system for preventing the occurrence of any cache miss against any writing in an adjacent memory block even when performing access to a memory block boundary part by cache line access, and for preventing the occurrence of memory destruction due to write back in a simple constitution. SOLUTION: A request for capturing a memory of which size is designated from a task 11 is received, and a memory block having an available area of which size is not less than the size designated from the task and adjusted by using the cache line size of an operating CPU 1 as a unit size by an operation system 12 is assigned to the request for capturing a memory. Also, a request for releasing a memory of which size is designated form the task 11 is received, and a memory block having the available are of which size is not more than the size designated from the task 11 and adjusted by the cache line size unit of the operating CPU 1 by the operating system 12 is released to the request for releasing a memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory management method for an operating system, and more particularly, to a memory management method for an operating system that accesses a memory space that can be accessed by a cache.

[0002]

2. Description of the Related Art In a conventional memory management method of an operating system, when a memory size of a work area is specified from an application program and an allocation request is issued, a memory block of the size requested to be allocated from the managed memory block is used. To read or write data.

On the other hand, there is a case where the CPU does not access the memory faithfully on the boundary of the memory block managed by the operating system, but accesses the memory by the boundary block according to the hardware specification. That is, in the cache access from the CPU to the memory, data is read or written from the memory in cache line size units. That is, even if the requested data has a smaller capacity than the cache line size, the data of the cache line size is read or written from the memory at once. Further, the CPU stores the address range of the real memory of the data read into the cache, and based on a method called write-back,
When writing occurs in the memory area read into the cache, data is written back to the real memory due to a cache miss for the cache line. Therefore, if an unused area corresponding to the cache line size is not provided at the boundary between two memory blocks, the contents of the memory may be destroyed as described below.

For example, a memory block A and a memory block B managed by the operating system are adjacent to each other, and this boundary does not coincide with the boundary of a cache line size area serving as a unit of cache access from the CPU.
It is assumed to be in the middle of the area. For example, when a portion including the boundary between the block A and the block B is read by the cache access, data of a cache line size is read from the memory at once, so that the cache memory includes a part of the block B. Next, assuming that data is written to the block B in a non-cache state, the contents of the cache and the contents of the real memory of a part of the cache line read by the cache access are different. At this time, if a cache miss occurs for that cache line, the old value read into the cache is written back to block B. This results in the destruction of the memory contents written in non-cache.

Japanese Patent Laid-Open Publication No. Hei 5-265864 discloses that a RAM is composed of an application use area and an operating system use area divided into two by a boundary address AW, and a memory write address output in response to a write request of an application program. And a boundary address are compared with each other, and when it is detected that writing to the operating system use area has occurred, this is prohibited.

[0006]

However, in this conventional technique, a process of comparing a write address of a memory access with a boundary address to detect whether or not to inhibit the memory access is performed. If there are a large number of access sources, the required processing becomes enormous, and there is a possibility that the performance may be deteriorated in terms of the speed of the memory management processing.

An object of the present invention is to prevent a cache miss from occurring in writing to an adjacent memory block even if a memory block boundary is accessed by a cache line access, thereby preventing the occurrence of memory corruption due to write-back. Another object of the present invention is to prevent memory destruction with a simple configuration.

Another object of the present invention is to prevent fragmentation of the memory when the memory block is released, and to prevent the memory from becoming worm-like.

[0009]

A memory management method for an operating system according to the present invention receives a memory acquisition request whose size is specified from a task, and responds to the memory acquisition request with a size equal to or greater than the size specified by the task. Allocate a memory block having an available area adjusted with the cache line size of the CPU on which the CPU operates as a unit size.

In addition, a memory release request specifying a size is received from a task, and the memory release request does not exceed the size specified by the task and has a size adjusted in cache line size units of a CPU on which an operating system operates. Release a memory block that has available space.

With these configurations, even if a memory block boundary is accessed by a cache line access, a cache miss does not occur for writing to an adjacent memory block, and memory corruption due to write-back can be prevented. With a simple configuration, memory destruction can be prevented.

If the size adjusted in cache line size units of the CPU is smaller than the cache line size, release may not be performed.

According to this configuration, it is possible to prevent fragmentation of the memory when the memory block is released, and to prevent the memory from becoming wormy.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, an operating system that operates on the CPU of the controller of the laser printer will be described. However, the present invention can be applied to any system that accesses a memory space in which a cache access method can be used.

FIG. 1 is a diagram showing an example of a hardware configuration of a controller of a laser printer on which an operating system according to the present invention operates. A controller of the laser printer includes a CPU 1 having a cache memory;
ROM 2 storing instruction codes for operating CPU 1
And a main memory 3 necessary for the operation of the CPU 1, a storage device 4 for storing information necessary for printing such as fonts, a memory controller 5 for controlling the main memory, and controlling an interruption in a predetermined time in the processing of the CPU 1. It includes a timer controller 6, an interrupt controller 7 for controlling an interrupt process connected to an external interrupt factor in the processing of the CPU 1, and a bus 8 connected to these.

The CPU 1 performs appropriate processing for various external factors such as an interrupt at a fixed time by the timer controller 6 and an interrupt from the interrupt controller 7 connected to the external interrupt factor. Also, the CPU 1
A cache memory having a cache line size of, for example, 32 bytes is provided, and has a cache memory write-back function described in the related art.

Next, the configuration of the operating system according to the present invention will be described.

FIG. 2 is a block diagram showing the configuration of one embodiment of the present invention.

The operating system 12 is a real-time operating system for the purpose of guaranteeing processing time in the operating system.
A plurality of tasks 11 are connected to the main memory 3 divided into memory blocks of the size requested by the tasks. Operating system 12
Manages the main memory 3, and the task 11 executes the operation of acquiring the unused area of the required size in the main memory 3 and the processing of releasing the allocated area of the main memory 3 allocated to the operating system 12. Do through. When the operating system 12 receives a memory acquisition request or a release request from one of the tasks 11, the operating system 12 suspends the processing for the other tasks 11 and acquires an area in the main memory 3 in response to the memory acquisition request or the release request. The memory to be released or released may be allocated.

The task 11 is, for example, a host I / F module, an emulator, a font manager module, and a printing module in a laser printer controller. The host I / F module requests that a reception buffer for storing received data in the memory and a transmission buffer for storing data to be transmitted be secured for each several megabytes, and the emulator edits and stores the received data in the memory. Requesting to secure a number of memory blocks corresponding to the amount of data in units of hundreds of bytes of page data to be printed, and the font manager module reads characters necessary for printing from the CGROM,
In order to temporarily store the data in the memory, a request is made for the character cache to have a capacity of several bytes to the size of the character according to the size of the character, and the printing module stores the print data in the memory. Request that a few MBs be reserved for the buffer.

The operating system 12 includes a memory alignment control unit 13 for adjusting a memory block acquired / released by a task in the same size as the cache line size, for example, in units of 32 bytes. The operating system 12 also includes a memory control unit 14 that performs acquisition / release processing of a memory block adjusted by the memory alignment control unit 13 in units of a cache line size of the CPU 1, for example, in units of 32 bytes. Further, the memory control unit 14 includes a memory management table 15 for collectively managing a free memory and a used memory.

More specifically, in the case of acquiring a memory, the memory is acquired in a size larger than a specified size, for example, adjusted in units of 32 bytes. The size after adjustment is the size after adjustment = ((specified size + (32-
1)) / 32) * 32. When releasing the memory, the memory alignment control unit 13 releases a memory having a size not exceeding the release size specified by the task 14 and adjusted in 32-byte units. The size after adjustment is as follows: Size after adjustment = (specified size / 32 bytes) * 32 bytes.

When all (not partially) the acquired memory blocks are released, 32
Since it is adjusted on a byte-by-byte basis, no special adjustment is required.

The main memory 3 is divided into unused memory blocks 16 and used memory blocks 17. The unused memory block 16 is a currently unused memory block of the size requested by the task or a memory block that has never been used, and the used memory block 17 is
1 is a memory block acquired by one of the requests. Before the main memory 3 is used, 1
Three large unused memory blocks 16.

FIG. 3 is a diagram showing a specific memory configuration of the used memory block and the unused memory block of FIG. Each memory block includes a memory block management table 21 that records information on the memory block, and a task available area 22. In the memory block according to the present invention, the memory block management table 2
1 and the task usable area 22 each have a size adjusted to the cache line size unit of the CPU 1, for example, 32 bytes.

The memory block management table 21 has a next block address 23, a previous block address 24, a start address 25, an end address 26, a block use status flag 27, and memory block information 28, 29, 30. If the next block address 23 is the next memory block of the same type, that is, an unused memory block, the head address of an unused block having the next smaller address value after that memory block is recorded. For example, the head address of a used memory block having a smaller address value after the memory block is recorded. The previous block address 24 records the head address of the same type of memory block having the next largest numerical value of the address after that memory block. The start address 25 records the start address of the task usable area of the memory block, and the end address records the end address of the memory block. The block use status flag 27 is, for example, information indicating an empty memory block in an unused memory, for example, “F”, and “U” indicating an in-use memory block in an in-use memory.
Record the data. Also, the memory block information 27,
28, 29 are other information about the memory block,
For example, when there is a request from the task indicating that all of the acquired memory blocks have been released, information for specifying whether to release the memory blocks or to keep the acquisition is recorded. For example, eight data comprising the next block address 23, the previous block address 24, the start address 25, the last address 26, the block use status flag 27, and the memory block information 28, 29, 30 constituting the memory block management table May be 4 bytes each.

FIG. 4 is a diagram showing the relationship between the memory management table 15 of FIG. The main memory 3 includes memory blocks 31 to 3 arranged in order as shown in FIG.
6. The memory blocks 31, 34, and 35 are unused memory blocks 16, and "F" that is information indicating unused is recorded in the block use status flags 37, 38, and 39, respectively. The memory blocks 32, 33, and 36 are used memory blocks 17, and the block use status flags 40, 41, and 42 record “U”, which is information indicating that they are in use.

Each memory block does not have a buffer area that is not used as a memory at a boundary portion,
Adjacent.

The next block address 43 of the memory block 31 is, like the block use status flag 37 of the memory block 31, the next block address of the memory block 31 in which "F" indicating unused is recorded. The head address of the memory block 34 having a small head address is recorded.

The previous block address 44 of the memory block 33 is the same as the block use status flag 41 of the memory block 33, and among the memory blocks in which “U” indicating that the memory block 33 is being used is recorded, Block 3 having the next highest start address
2 is recorded at the beginning address.

The previous block addresses 45 and 46 of the head memory blocks 31 and 32 of the unused memory block 16 and the used memory block 17 and the next block addresses 47 and 48 of the last memory blocks 35 and 36 are NULL.
L.

As shown in FIG. 4, the memory management table 15 includes an empty memory head block 51 indicating the head of the unused memory block 16, that is, the head address of the memory block 31 having a smaller address.
The final, that is, the higher address memory block 35
, A free memory last block 52 indicating the start address of the first memory block 32 of the used memory blocks 17, and a start address of the last memory block 36. Used memory last block 54 is recorded. Also, the memory management table 15
Is the size rounded to the cache line size.

Next, the operation of the memory management of the operating system shown in FIG. 2 will be described.

FIG. 5 is a flowchart showing the memory management operation of the operating system of FIG. When a memory acquisition or release request from a task occurs (step S1), the operating system determines whether the request is a memory acquisition request (step S2). The size of the memory to be obtained is adjusted based on (step S3). At this time, the size is adjusted to a cache line size unit of the CPU 1, for example, a unit of 32 bytes, which is equal to or larger than the specified size. That is, the size after adjustment is the size after adjustment = ((specified size + (32-
1)) / 32) * 32. The memory block is traced from the free memory head block 42 of the memory management table 15 to detect a free memory block having a used area size that satisfies the adjusted size (step S4). At this time, the size of the memory block is detected by calculating the difference between the last address and the start address recorded in the memory block management table of each memory block. This size is always rounded to the cache line size. If the size requirement is not satisfied, the next block 31 is sequentially traced, the size of the memory block is calculated, and the search is performed until a memory block satisfying the size requirement can be detected.
The memory control unit 14 divides the entire detected unused memory block or a block obtained by dividing it by a necessary size from the head of the address range of the memory block to the used area size of the adjusted size. It is registered in the memory management table 15 as a memory block (step S5). At this time, the area information of the detected unused memory block is changed to area information indicating the other area.

If it is determined in step S2 that the memory is not acquired, it is determined that the memory is to be released, and then it is determined whether to partially release the memory in the specified memory block (step S6). To release all (not partially) the acquired memory block, 32
Since it is adjusted on a byte-by-byte basis, no special adjustment is required. When releasing the whole, the memory block whose release is requested by the task is registered as an unused block in the memory management table 15 (step S).
7). If the memory is partially released in step S6, the size to be released is adjusted (step S8).
The size after adjustment is as follows: Size after adjustment = (specified size / 32 bytes) * 32 bytes. Next, it is determined whether the size after the adjustment is smaller than the cache line size (step S9). If the size is smaller, the process is terminated without releasing the memory. If the size after the adjustment is larger than the cache line size, the memory control unit 14 divides the memory block requested by the task to be released and sets the size of the task usable area in the memory block area after the adjustment. The memory block having the size is registered as an unused memory block in the memory management table 15 (step S10). At this time, in the memory management table 15, the area information of the memory block using the memory block requested to be released by the task is changed.

As described above, according to the memory management method of the present invention, it is possible to manage the access size to the memory in the same unit as the cache access from the CPU, and incorporate a complicated correspondence into the operating system. There is no necessity, and memory destruction can be prevented without any special measures for preventing destruction of the contents stored in the memory on the task side.

When the cache line size of the CPU is 32 bytes, the memory size adjusted by the memory alignment control unit 13 is specified to be any multiple of 32. As a result, it is possible to set the most optimal size for the system so that adjacent memory blocks do not destroy the memory contents even by different memory access methods. If sufficient memory is provided, the larger the adjustment unit, such as the unit of 256 bytes, the lower the management and cost of the memory, and the higher the speed.

[0038]

As described above, according to the memory management method of the operating system of the present invention, the memory block dynamically acquired / released by the operating system is used for operating the operating system.
By managing the PU1 in units of cache line size, for example, in units of 32 bytes, even if a memory block boundary is accessed by cache line access, a cache miss does not occur for writing to an adjacent memory block, and write back is performed. Can prevent the occurrence of memory destruction. Also, in order to prevent memory destruction, it is not necessary to provide a buffer area that cannot be used as a memory at the boundary between two memory blocks for performing cache access, and the two memory blocks can be adjacent to each other, thus improving the memory efficiency. Further, at the time of cache access, there is no need to perform a process of performing a check for preventing memory destruction due to straddling a memory block boundary, so that the process is simple and memory management can be performed at high speed.

Furthermore, when the release size is smaller than the cache line size, the release is not performed, thereby preventing a task from acquiring / releasing a memory block in a small size of several bytes, thereby preventing the memory from being wormy. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a hardware configuration of a controller of a laser printer on which an operating system according to the present invention operates.

FIG. 2 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 3 is a diagram showing a specific memory configuration of a used memory block and an unused memory block of FIG. 2;

FIG. 4 is a diagram showing a relationship between a memory management table 15 of FIG.

FIG. 5 is a flowchart showing an operation of acquiring and releasing memory of the operating system of FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 Main memory 4 Storage device 5 Memory controller 6 Timer controller 7 Interrupt controller 8 Bus 11 Task 12 Operating system 13 Memory alignment control unit 14 Memory control unit 15 Memory management table 16 Unused block memory 17 Used block memory 21 Memory Block management table 22 Task available area 23, 43, 47, 48 Next block address 24, 44, 45, 46 Previous block address 25 Start address 26 End address 27, 37, 38, 39, 40, 41, 42 Block usage status Flags 28, 29, 30 Memory block information 31, 32, 33, 34, 35, 36 Memory block 51 Free memory first block 52 Free memory last block 53 Usage memo Top block 54 use memory the last block

Claims (6)

[Claims] 1. A method in which a memory acquisition request whose size is designated by a task is received, and the memory acquisition request is used in which a cache line size of a CPU which is equal to or more than the size designated by the task and which runs an operating system is adjusted as a unit size. A memory management method for an operating system, wherein a memory block having a possible area is allocated. 2. A memory release request having a size specified by a task is received. In response to the memory release request, a size smaller than the size specified by the task and adjusted by a cache line size unit of a CPU on which an operating system operates. A memory management method for an operating system, wherein a memory block having an available area is released. 3. The memory management method for an operating system according to claim 2, wherein the release is not performed when the size adjusted in cache line size units of the CPU is smaller than the cache line size. 4. A memory block having a usable area which is equal to or larger than a size designated by the task and has an available area obtained by adjusting a cache line size of a CPU on which an operating system operates as a unit size is searched from the memory. Item 4. The memory management method for an operating system according to any one of Items 1 to 3. 5. A flag indicating a use status, a next block address, and information indicating a size of an available area are recorded in each of the plurality of memory blocks, and address information of a head memory block of the used memory block is recorded. Holds the address information of the head of the unused memory block, and sequentially uses the usage status of the used memory block or the unused memory block from the head of the used memory block or the head of the unused memory block. Detecting a memory block having a usable area which is detected and adjusted as a unit size of a cache line size of a CPU on which an operating system operates and which is equal to or larger than a size specified by the task, from the memory; 5. The memory management method for an operating system according to claim 4. 6. The memory system according to claim 1, wherein the size of the plurality of memory blocks other than the usable area is a size in which a cache line size of a CPU on which an operating system operates is used as a unit size. The memory management method for an operating system according to claim 1.