JP2001148482A - Method for manufacturing field effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate an SiGe layer where Ge of sufficient concentration exists in a channel area even if the ion implanting quantity of Ge is less when ion- implanting Ge to an Si layer in an SOI wafer, to improve carrier moving degree in a field effect semiconductor device, and to improve current driving force on the manufacture method of the field effect semiconductor device. SOLUTION: A process for implanting Ge ions in an Si layer 3 in an SOI wafer, thermally oxidizing the Si layer 3, forming a SiO2 layer 4 on a surface and converting it into a thinned SiGe layer 3G is included.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for increasing the carrier mobility and improving the current driving force by using SiG
The present invention relates to a method suitable for manufacturing a field-effect semiconductor device using e.

[0002]

2. Description of the Related Art A fine MOSFET (metal oxi)
de semiconductorfield eff
act transistor, especially p-type MOSFE
At T, attempts have been made to increase the mobility of holes by using SiGe for the channel region and to improve the current driving force.

Further, in an ultra-fine MOSFET having a gate length of 0.1 [μm] or less, the SOI (silver)
Icon-on-insulator structures are being adopted.

Therefore, taking the above technical tendency into account, SO
It has been considered to replace the Si layer on the insulating layer in the I wafer with a SiGe layer. For example, a method of ion-implanting Ge into the Si layer (if necessary, see Japanese Patent Application Laid-Open No. 6-310719).
No. 2).

However, according to the above-mentioned conventional technique, a high-performance fully depleted SO having a thickness of 50 nm in the Si layer is used.
It is difficult to make an I-MOSFET.

The reason is that Ge must be implanted into an extremely thin Si layer. Even if ion implantation can be performed, it is necessary to increase the Ge concentration in the Si layer to a practically necessary level. A realistic implantation dose is required, and even if recrystallization is performed, crystalline deterioration is unavoidable, and the through-put in manufacturing is significantly reduced. Since the parasitic resistance increases when the thickness of the Si layer is reduced, the increase in carrier mobility due to the presence of a small amount of Ge, that is, the improvement in the current driving force is canceled out. Discloses reducing the parasitic resistance by silicidizing the source and drain,
Since the Si layer is thinned, there is a problem that silicidation proceeds to a buried oxide layer which is a base of the Si layer, thereby increasing resistance.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a method for producing a SiGe layer by ion-implanting Ge into a Si layer in an SOI wafer, even if the ion implantation amount of Ge is small.
SiGe in which sufficient concentration of Ge exists in the channel region
An attempt is made to increase the carrier mobility in a field-effect semiconductor device by improving the ability to generate a layer and to improve the current driving force.

[0008]

According to the present invention, SO is used.
After ion implantation of Ge into the Si layer of the I-wafer, the Si layer is thermally oxidized to make it thinner.
Ge segregated at the interface between the i-layer and the thermal oxide film
It is fundamental to obtain a channel region having a high concentration.

In the present invention, it is not necessary to reduce the thickness of the Si layer of the SOI wafer to which Ge is to be ion-implanted from the beginning. it can.

When the Si layer is thermally oxidized, Ge becomes Si
Since segregation at the interface between the layer and the oxide film is utilized, the Si concentration is high even if the Ge ion implantation amount is low.
Since the Ge layer can be generated, the problems in the above-mentioned known technology can be solved.

[0011] As will be described later in the "embodiment of the invention",
By selectively ion-implanting Ge only in the channel region and then thermally oxidizing it, the channel layer can be made thinner and the source and drain regions can be left thicker. A MOSFET having an elevated source / drain structure formed in a self-aligned manner with respect to the channel region is realized, and the problems and problems in the above-described known technology can be solved.

As described above, in the field effect type semiconductor device according to the present invention, (1) a Si layer (for example, a Si layer 3) in an SOI wafer
Implanting Ge ions into the Si layer, thermally oxidizing the Si layer to form a SiO ₂ layer (eg, SiO ₂ layer 4) on the surface, and converting the Si layer into a thinned SiGe layer (eg, SiGe layer 3G). It is characterized by being included.

(2) In the above (1), the implantation of the Ge ions may include a portion where a channel region is to be formed, a portion where an extension source region is to be formed, and an
The present invention is characterized in that the process is limited to a portion where a drain region is to be formed.

The field effect type semiconductor device having the SOI structure manufactured by employing the above means has a high Ge concentration and has a channel region made of thinned SiGe.
The carrier mobility is high, and therefore, the current driving force is large.

The means necessary for realizing the structure exhibiting the excellent characteristics is the Si film which was initially in a thick state.
The layer is only ion implanted with Ge and then thermally oxidized, after which the SiGe layer is thinned and Ge is present at a high concentration on the surface acting as the channel region. Moreover, no special technique is required to obtain the result, and therefore, its implementation is extremely simple and can be easily dealt with within the range of conventionally used techniques.

[0016]

1 and 2 are cutaway side views of a main part of a field effect type semiconductor device at a key point in a process for explaining an embodiment of the present invention. This will be described with reference to FIG.

1 (A) 1- (1) By applying a normal technique, the Si semiconductor substrate 1,
An SOI wafer including a buried insulating layer 2 made of SiO ₂ and a Si layer 3 is prepared. Here, the Si layer 3 is set to be, for example, 100 [nm] thicker than the normal case.

[0018] 1- (2) depending on applying an ion implantation method, 30 an ion acceleration energy [keV], perform implantation of Ge ions and the dose amount of 3 × 10 ¹⁶ [cm ^-2].

1- (3) Thermal oxidation is performed at a temperature of 1000 ° C. for a time of 5 minutes to form an SiO ₂ layer 4 having a thickness of 50 nm on the surface.

It should be noted that when Ge is present in Si, the oxidation rate of Si increases. When the oxidation is performed, the Si layer 3 is converted to the SiGe layer 3G. However, since Ge has a property of segregating in Si, the Ge concentration particularly increases at the interface between the Si layer 3 and the SiO ₂ layer 4, Therefore, the carrier mobility in the channel created therein is improved. It is.

2 (A) 2- (1) After immersion in a hydrofluoric acid solution to remove the SiO ₂ film 4, a thickness of 3 [nm] is obtained by applying a thermal oxidation method. The gate insulating film 5 made of SiO ₂ is formed.

2- (2) CVD (Chemical Vapor Deposition)
A polycrystalline Si layer having a thickness of 180 [nm] is formed on the gate insulating film 5 by applying the (tion) method.

2- (3) A resist process in a normal lithography technique,
Further, by applying a dry etching method using HBr as an etching gas, the polycrystalline Si layer formed in step 2- (2) is etched to form a gate electrode 6G made of polycrystalline Si.

2 (B) 2- (4) By applying the ion implantation method, the ion acceleration energy is set to 5 [keV] and the dose is set to 2 × 10 ¹⁴ [cm ⁻² ].
F ₂ ions are implanted and the extension
Source region 7E and extension / drain region 8
Form E.

2- (5) By applying the CVD method, a 60 nm thick S
By applying a dry etching method in which an iO ₂ layer is formed and the etching gas is CF ₄ ,
By performing anisotropic etching of _two layers, side walls 9 are formed on the side surfaces of the gate electrode 6G.

2- (6) By applying the ion implantation method, the ion acceleration energy is set to 7 [keV] and the dose is set to 2 × 10 ¹⁵ [cm ⁻² ].
By implanting ions, a source region 7S and a drain region 8D are formed.

2- (7) Thereafter, by applying a normal technique, for example, heat treatment for activating the implanted ions, formation of an insulating film, formation of each electrode and wiring, and the like are performed to form an SOI-MOSFET. Complete.

FIGS. 3 and 4 are cutaway side views showing a main part of a field-effect semiconductor device in a process step for explaining another embodiment of the present invention. It will be described with reference to FIG. 1 and 2 represent the same parts or have the same meaning.

FIG. 3 (A) 3- (1) By applying a normal technique, the Si semiconductor substrate 1,
An SOI wafer including a buried insulating layer 2 made of SiO ₂ and a Si layer 3 is prepared. Here, the Si layer 3 is set to be, for example, 100 [nm] thicker than the normal case.

3- (2) By applying a resist process in the lithography technique, a resist film 11 having an opening 11A including a portion where a channel region, an extension source region and an extension drain region are to be formed is formed. Form.

3- (3) By applying the ion implantation method, the ion acceleration energy is set to 30 [keV], the dose is set to 3 × 10 ¹⁶ [cm ⁻² ], and the resist film 11 is used as a mask to form Ge ions. Make a drive.

3 (B) 3- (4) After immersion in a resist stripper to remove the resist film 11, thermal oxidation is performed at a temperature of 1000 ° C. for 5 minutes. An SiO ₂ film 4 is formed.

As described above, when Ge is present in Si, the oxidation rate of Si is increased, and therefore, as shown in the figure, a portion where Ge is ion-implanted, that is, a portion where a channel region is to be formed, is shown. In other words, the SiO ₂ layer 4 becomes thicker, and the other portions become thinner.

Therefore, the SiGe layer 3G to be the channel region, the extension source region, and the extension / drain region becomes thin, and the Si layers 3 on both sides thereof become thin.
That is, the portions that should become the source and drain regions are:
It remains thicker than the SiGe layer 3G.

4 (A) 4- (1) After removing the SiO ₂ film 4 by immersion in a hydrofluoric acid solution, a thickness of 3 [nm] is obtained by applying a thermal oxidation method. The gate insulating film 5 made of SiO ₂ is formed.

4- (2) A polycrystalline Si layer having a thickness of 180 nm is formed on the gate insulating film 5 by applying the CVD method.

4- (3) A resist process in a normal lithography technique,
Further, by applying a dry etching method using HBr as an etching gas, the polycrystalline Si layer formed in step 4- (2) is etched to form a gate electrode 6G made of polycrystalline Si.

4 (B) 4- (4) By applying the ion implantation method, the ion acceleration energy is 5 [keV] and the dose is 2 × 10 ¹⁴ [cm ⁻² ].
F ₂ ions are implanted and the extension
Source region 7E and extension / drain region 8
Form E.

4- (5) By applying the CVD method, a 60 nm thick S
By applying a dry etching method in which an iO ₂ layer is formed and the etching gas is CF ₄ ,
By performing anisotropic etching of _two layers, side walls 9 are formed on the side surfaces of the gate electrode 6G.

4- (6) By applying the ion implantation method, the ion acceleration energy is set to 7 [keV] and the dose is set to 2 × 10 ¹⁵ [cm ⁻² ].
By implanting ions, a source region 7S and a drain region 8D are formed.

4- (7) Thereafter, by applying a normal technique, for example, heat treatment for activating the implanted ions, formation of an insulating film, formation of each electrode and wiring, and the like are performed to perform an elevated source. SOI having a region and an elevated drain region
Complete the MOSFET.

In the present invention, many modifications can be realized without being limited to the above-described embodiment and without departing from the scope of the claims.

For example, the elevated source region and the elevated drain region may be metal silicide.

In the above embodiment, Ge was ion-implanted to form the SiGe layer. However, when Ge is ion-implanted,
Any of C, N, B, P, and As or two or more of them may be simultaneously ion-implanted to perform impurity doping on a channel portion, form a SiGeC layer, and form a SiGeN layer.

The thermal oxidation after the implantation of Ge ions can be performed in either a dry atmosphere or a wet atmosphere.

In the above embodiment, the thickness of the Si layer in the SOI wafer was set to 100 [nm].
It may be selected in the range of [nm] to 200 [nm].

[0047] In the embodiment, although the gate insulating film formed by applying the thermal oxidation method may be formed depending on the CVD method, also, as the material of the gate insulating film not only SiO _2, For example, a high dielectric material such as Ta ₂ O ₅ may be used.

The method for manufacturing a field-effect semiconductor device according to the present invention can be carried out without any problem when manufacturing either an n-type MOSFET or a p-type MOSFET.

[0049]

According to the method of manufacturing a field-effect semiconductor device according to the present invention, a Ge layer is formed on a Si layer of an SOI wafer.
After implanting ions, the Si layer is thermally oxidized to
An O ₂ layer is formed and converted to a thinned SiGe layer.

The SOI structure field-effect semiconductor device manufactured by adopting the above-described structure has a high Ge concentration and has a channel region made of thinned SiGe.
The carrier mobility is high, and therefore the current driving force is large.

The means necessary for realizing the structure exhibiting the excellent characteristics is that the initially thick Si
The layer is only ion implanted with Ge and then thermally oxidized, after which the SiGe layer is thinned and Ge is present at a high concentration on the surface acting as the channel region. Moreover, no special technique is required to obtain the result, and therefore, its implementation is extremely simple and can be easily dealt with within the range of conventionally used techniques.

[Brief description of the drawings]

FIG. 1 is a fragmentary sectional side view showing a field-effect semiconductor device at an important point in a process for describing an embodiment of the present invention.

FIG. 2 is a fragmentary side view showing a field-effect semiconductor device at a key step in the process for describing one embodiment of the present invention.

FIG. 3 is a fragmentary side view showing a field-effect semiconductor device at a key step in a process for explaining another embodiment of the present invention.

FIG. 4 is a fragmentary sectional side view showing a field-effect semiconductor device at a main point of a process for explaining another embodiment of the present invention.

[Description of Signs] 1 Si semiconductor substrate 2 embedded insulating layer made of SiO ₂ 3 Si layer 3G SiGe layer 4 SiO ₂ layer 5 gate insulating film made of SiO ₂ 6G gate electrode made of polycrystalline Si 7E extension source region 7S source Region 8E Extension / drain region 8D Drain region 9 Side wall 11 Resist film 11A Opening

Claims (2)

[Claims] A step of implanting Ge ions into a Si layer of an SOI wafer, thermally oxidizing the Si layer to form a SiO ₂ layer on the surface, and converting the Si layer into a thinned SiGe layer. A method for manufacturing a field-effect semiconductor device, comprising: 2. The electric field according to claim 1, wherein the implantation of the Ge ions is performed only in a portion where a channel region is to be formed, a portion where an extension / source region is to be formed, and a portion where an extension / drain region is to be formed. Manufacturing method of effect type semiconductor device.